Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
3. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
In claim 12: instruction stream transmission unit
In claim 13: first instruction segmentation unit
In claim 15: second instruction segmentation unit
In claim 15: block unit
In claim 17: reading unit
In claim 17: marking unit
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
4. Claims 12-17 are rejected. The claim limitations listed above of claim 12 and its dependents invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Keller et al (US 2003/0182543) in view of Chou et al (US 2018/0121200, herein Chou).
In the following rejections, the processor embodiment of claim 12 will be addressed first.
Regarding claim 12, Keller teaches a processor, comprising an instruction data cache ([0041], instruction cache), an instruction stream transmission unit ([0073], fetch unit), and a branch prediction error determination unit ([0072], branch predictor),
wherein the instruction stream transmission unit is configured to write an instruction stream into the instruction data cache and the branch prediction error determination unit ([0043], fetch instructions to icache and branch predictor); and
the branch prediction error determination unit is configured to:
determine a branch instruction in the instruction stream and whether a branch prediction error exists for the branch instruction ([0130], [0134], [0136], determine if branch was mispredicted); and
Keller fails to teach wherein the instruction stream is written into the instruction data cache and the branch prediction error determination unit in parallel in an instruction processing pipeline, or wherein in response to a branch prediction error existing for a branch instruction, perform a flush operation on an object instruction in the instruction processing pipeline that is fetched due to the branch prediction error.
Chou teaches a processor, comprising an instruction data cache ([0002], instruction cache), an instruction stream transmission unit ([0025], fetch unit), and a branch prediction error determination unit ([0025], branch prediction unit),
wherein the instruction stream transmission unit is configured to write an instruction stream into the instruction data cache and the branch prediction error determination unit in parallel in an instruction processing pipeline ([0057], instruction blocks sent to branch predictor and instruction cache in parallel); and
in response to a branch prediction error existing for a branch instruction, perform a flush operation on an object instruction in the instruction processing pipeline that is fetched due to the branch prediction error ([0021], [0030], flushing instructions associated with mispredicted branch).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Keller and Chou in order to provide instruction information to the cache and branch predictor in parallel and flush instructions that result from a misprediction. While Keller does not explicitly state that the instruction cache and branch predictor are written to in parallel, these units are embodied as working together to drive instruction fetching, and Keller does state that they work in parallel to provide next fetch addresses and branch predictions (Keller [0011]). Also, while Keller does not explicitly state that instructions are flushed as a result of a misprediction, one of ordinary skill in the art would understand that incorrectly fetched instructions resulting from a branch misprediction must be cleared from a pipeline in order to maintain accurate execution results, and taught by Chou. As both of these aspects of Chou are routine and conventional mechanisms in the microprocessor art, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 13, the combination of Keller and Chou teaches the processor according to claim 12, wherein the branch prediction error determination unit comprises: a first instruction segmentation unit, configured to perform a first instruction segmentation on the instruction stream written into the branch prediction error determination unit to obtain a first set of instructions (Keller [0009], [0042], locate instruction boundaries for variable-length instructions); and a branch result computation and checking unit, configured to, in response to the branch instruction existing in the first set of instructions, compute a computation target address of the branch instruction, and check whether the computation target address is consistent with a branch prediction target address for the branch instruction (Keller [0067], [0071], branch target address prediction), and in response to the computation target address being inconsistent with the branch prediction target address, determine that the branch prediction error exists for the branch instruction (Keller [0128], [0130], verify accuracy of branch prediction or return status of misprediction).
Claim 19 refers to an apparatus embodiment of the processor embodiment of claim 12. Therefore, the above rejection for claim 12 is applicable to claim 19.
Claims 1-2 refer to a method embodiment of the processor embodiment of claims 12-13. Therefore, the above rejections for claims 12-13 are applicable to claims 1-2, respectively.
Regarding claim 3, the combination of Keller and Chou teaches the method according to claim 2, wherein the computing a computation target address of the branch instruction comprises computing the computation target address based on instruction jump information of the branch instruction (Keller [0070], target address formed by branch displacement included with instruction).
Regarding claim 9, the combination of Keller and Chou teaches the method according to claim 1, further comprising: further comprising: performing an instruction fetch operation to acquire the instruction stream in the instruction processing pipeline (Keller [0073], instruction fetching, Chou [0025], instruction fetching).
Regarding claim 10, the combination of Keller and Chou teaches the method according to claim 9, wherein the performing an instruction fetch operation to acquire the instruction stream comprises: in response to receiving an instruction acquisition request, based on a tag part of a destination address comprised in the instruction acquisition request, querying a tag memory of an instruction cache to determine whether the tag part hits the tag memory (Keller [0083], [0113], cache lookups using tags; in response to the tag part hitting the tag memory, reading instruction data corresponding to the instruction acquisition request from a data memory of the instruction cache as the instruction stream; or in response to the tag part not hitting the tag memory, reading instruction data corresponding to the instruction acquisition request from a main memory or a next level cache (Keller [0041], [0044], fetching instructions and data from caches using tags & [0029], [0034], fetch from memory when necessary, [0053], [0055], handling cache misses).
Regarding claim 11, the combination of Keller and Chou teaches the method according to claim 1, wherein the instruction stream comprises a plurality of non-fix length instructions (Keller [0009], [0042], variable length instructions).
Claim 20 refers to a medium embodiment to implement the method embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 20.
6. Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Keller and Chou as applied to claims 1 and 12 above, and further in view of Nye et al (US 2006/0095750, herein Nye).
Regarding claim 4, the combination of Keller and Chou teaches the method according to claim 1. Keller and Chou fail to teach the method comprising in response to the branch prediction error existing, correcting a write pointer of the instruction data cache to move the write pointer to a location of the object instruction in the instruction data cache.
Nye teaches a method for operating a processor wherein in response to a branch prediction error existing, correcting a write pointer of an instruction data cache to move the write pointer to a location of the object instruction in the instruction data cache ([0145], [0295], [0312-0313], [0334-0343] write pointer of branch target address FIFO to fetch into instruction cache updated in response to prediction and misprediction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Keller and Chou with those of Nye to update a write pointer in response to branch misprediction events. While Keller and Chou do not explicitly teach a structure that uses a write pointer to handle fetching into an instruction cache, one of ordinary skill in the art would understand that read/write or head/tail pointers are a routine and conventional aspect of the microprocessor art. Therefore, updating such structures in a processor that makes use of them would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
7. Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gong (US 2021/0311744) discloses a processor that flushes a pipeline in response to a branch prediction error and performs fetching and branch prediction in parallel.
McDonald (US 2004/0139281) discloses a processor with a branch predictor that operates in parallel to instruction fetching.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183