DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species II encompassing claims 1-20 in the reply filed on 12/26/2025 is acknowledged. Since, there were the generic claim and the linking claim. Therefore, the election/restriction filed 11/07/2025 was withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kim e al. (US 2021/0027696, herein after Kim '696) in view of Kim et al. (US 2022/0208088, herein after Kim '088).
As to claim 1, Kim '696 teaches a display apparatus (a display device 100, see abstract, figures 1, 2A, 2B) comprising:
a plurality of pixels (pixels, see Fig 2B), each of the plurality of pixels including a pixel circuit (pixel unit 100, see ¶84), the pixel electrode is connected to the pixel circuit (see ¶90, Fig 2A);
a plurality of data lines (jth data lines Dj, ¶88) respectively connected to the plurality of pixels (pixels Pxi, Pxi+1, Fig 2B);
wherein a data signal is supplied to each of the plurality of pixels via the plurality of data lines (see ¶104) once per one frame (1 frame RR=60Hz, see Fig 7C);
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an initializing voltage is supplied to the pixel electrode in each of the plurality of pixels at least twice per one frame (three initializing voltages periods in one frame, or one refresh rate, e.g., RR = 60Hz. See Fig 14C, ¶254- ¶262);
wherein a time taken for the data signal to be supplied to each of the plurality of pixels during one frame is less than or equal to a period during which the initializing voltage is supplied to the pixel electrode in each of the plurality of pixels during one frame (one display scan period DSP is less than three self-scan periods during one frame, or one refresh rate, e.g., RR= 60Hz, see Fig 7C, ¶193 ).
Kim '696 fails to teach "at least one pixel electrode overlaps with a data line among the plurality of data lines".
Kim '088 teaches two pixel electrodes PE1 and PE3 overlap two data lines DL1 and DL2. See Kim '088 ¶147, and Fig 9.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to modify the two pixel electrodes PE1 and PE3 overlap the two data lines DL1 and DL2 taught by Kim '088 for the display device of Kim '696 because this would prevent the stains due to coupling between a pixel electrode and a data line from being visually recognized in a display area affected by coupling at a rising edge or a falling edge of a data voltage. (See Kim '088 ¶05).
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim '696 and Kim '088 as applied to claim 1 above, and further in view of Shin et al. US 2020/0184900.
As to claim 2, Kim '696 and Kim '088 fail to teach the plurality of data lines includes first data lines connected to pixels arranged in odd pixel rows and second data lines connected to pixels arranged in even pixel rows, and one of the first data lines and one of the second data lines are arranged adjacent to each other in each pixel column.
Shin teaches pixels PXL included in a single pixel column alternately coupled to a pair of data lines, the pixels included in odd-numbered rows (or first pixels), among pixels PXL included in a first column, coupled to a first odd-numbered data line Dka (or a first data line), and pixels included in even-numbered rows (or second pixels), among the pixels PXL included in the first column, coupled to a first even-numbered data line Dkb (or a second data line). See Shin ¶58, ¶80, and Figs 2A, 2B.
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a single pixel column alternately coupled to a pair of data lines, the pixels included in odd-numbered rows, among pixels PXL included in a first column, coupled to a first odd-numbered data line Dka, and pixels included in even-numbered rows, among the pixels PXL included in the first column, coupled to a first even-numbered data line Dkb, as teaches by Shin, to modify the pixel circuit of Kim '696 and Kim '088. The motivation for doing so would improve the high quality of the image being displayed, while reducing the time suitable to charge a data signal in each pixel, and saving power consumption. Shin ¶5.
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim '696 and Kim '088 as applied to claim 1 above, and further in view of Lin et al. US 2018/0061311.
As to claim 3, Kim '696 and Kim '088 fail to teach the pixel circuit comprises a driving transistor, a first transistor connected between a corresponding data line and a gate electrode of the driving transistor, the first transistor is turned on in response to a first gate signal and transmits the data signal from the corresponding data line to a gate of the driving transistor; a second transistor connected between the pixel electrode and an initializing voltage line to which the initializing voltage is supplied, wherein the second transistor is turned on in response to a second gate signal and transmits the initializing voltage to the pixel electrode.
Figure 14 of Lin teaches the pixel circuit 40, a driving transistor (a driving transistor 100, ¶65); a first transistor (TFT 110, ¶67) connected between a corresponding data line (a data line 46), a gate electrode (a gate electrode of the driving transistor 100), the first transistor is turned on in response to a first gate signal and transmits the data signal from the corresponding data line to a gate of the driving transistor (See ¶67); a second transistor (TFT 114, see ¶70) connected between the pixel electrode (node 66 of LED 54) and an initializing voltage line (reset voltage at node 66, ¶71) to which the initializing voltage (reference voltage 108, ¶70) is supplied, the second transistor is turned on in response to a second gate signal and transmits the initializing voltage to the pixel electrode (See Fig 14 and ¶70-¶71 explained the scan line 44 turns on the TFT 114 to operate, and control to affect reset of the voltage at anode 66 at a prescribed rate that differs from the refresh rate of the display).
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the details pixel circuit to control the reset voltage at the anode at the predetermined rate that differs from the refresh rate of the display, as teaches by Lin in Fig. 14, to modify the pixel circuit of Kim '696 and Kim '088. The motivation for doing so would improve the better display without flickering by the prescribed refresh rate, and allow for true black to be achieved while maintaining a low refresh rate for the LED display. Lin ¶32.
As to claim 4, Kim '696 teaches the time taken for the data signal to be supplied to each of the plurality of pixels during one frame is a time during which the first gate signal is supplied to first transistor of each of the plurality of pixels ( Kim '696 [0093] The second transistor M2 is connected between the data line Dj and the first node N1. A gate electrode of the second transistor M2 is connected to an i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the second transistor M2 is turned on to electrically connect the data line Dj and the first node N1);
wherein the period during which the initializing voltage is supplied to the pixel electrode in each of the plurality of pixels during one frame is a period during which the second gate signal is supplied to the second transistor of each of the plurality of pixels.
( Kim '696 [0101] The seventh transistor M7 is connected between the first electrode of the light-emitting element LD and the initialization power source Vint. A gate electrode of the seventh transistor M7 is connected to the i-th first emission control line E1i. When an emission control signal is supplied to the i-th first emission control line E1i, the seventh transistor M7 is turned on to supply the voltage of the initialization power source Vint to the first electrode of the light-emitting element LD.)
Claim(s) 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim '696, Kim '088 and Lin as applied to claim 3 above, and further in view of Lee et al. US 2021/0202759.
As to claim 5, Kim '696, Kim '088 and Lin fail to teach the driving transistor comprises a lower gate electrode supplied with a driving voltage; an upper gate electrode supplied with a voltage corresponding to the data signal; and
a semiconductor layer arranged between the lower gate electrode and the upper gate electrode.
Figure 7 of Lee teaches the driving transistor (T1) has a lower gate electrode (G1a) supplied with a driving voltage; an upper gate electrode (G1b) supplied with a voltage corresponding to the data signal, a semiconductor layer (C1) arranged between the lower gate electrode (G1a) and the upper gate electrode (G1b). See Lee ¶142, ¶174-¶175.
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the driving transistor (T1) has a lower gate electrode (G1a) supplied with a driving voltage; an upper gate electrode (G1b) supplied with a voltage corresponding to the data signal, a semiconductor layer (C1) arranged between the lower gate electrode (G1a) and the upper gate electrode (G1b), as teaches by Lee in Fig. 7, to modify the pixel circuit of Kim '696, Kim '088 and Lin. The motivation for doing so would improve the high resolution, while reducing area of pixel circuit. Lee ¶172.
As to claim 6, Lee teaches the display apparatus of claim 5, wherein the semiconductor layer of the driving transistor comprises a silicon semiconductor. (Lee [0013] the first semiconductor layer may include a silicon semiconductor material or an oxide semiconductor material.)
As to claim 7, Lee teaches the display apparatus of claim 5, wherein the first transistor comprises: a lower gate electrode; an upper gate electrode connected to the lower gate electrode; and a semiconductor layer arranged between the lower gate electrode and the upper gate electrode. (Lee [0084] Referring to FIG. 4, a thin-film transistor substrate TB according to an embodiment may include a thin-film transistor T having a semiconductor layer A, a lower gate electrode Ga, an upper gate electrode Gb, and an electrode layer E, wherein the semiconductor layer A may have a channel area C, a source area S, and a drain area D, and the electrode layer E may be disposed on or above the upper gate electrode Gb and may be electrically connected to at least one of the source area S and the drain area D. The lower gate electrode Ga may overlap the semiconductor layer A, but may overlap the channel area C and the drain area D.)
As to claim 8, Lee teaches the display apparatus of claim 7, wherein the semiconductor layer of the first transistor comprises an oxide semiconductor. (Lee [0013] the first semiconductor layer may include a silicon semiconductor material or an oxide semiconductor material.)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2018/0061311) in view of Kim e al. (US 2021/0027696, Kim '696).
As to claim 12, Lin teaches a display apparatus (a display 12, see ¶ 43, Fig 6 and Fig 14), a plurality of pixels (multiple display pixels 40, ¶ 44, fig. 6), a light-emitting device (LED 54, Fig 14);
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Figure 4 of Lin teaches a first transistor (a driving TFT 100, ¶70) configured to output a driving current to the light-emitting device (54);
a second transistor (110, ¶70) connected between a data line (46) and the first transistor (100), wherein the second transistor is turned on in response to a first gate signal and transmits a data signal from the data line to a gate of the first transistor (see ¶70);
a third transistor (114) connected between the light-emitting device (54) and an initializing voltage line (108), wherein the third transistor is turned on in response to a second gate signal and transmits an initializing voltage that is supplied through the initializing voltage line to an electrode of the light-emitting device (see ¶70).
Lin fails to teach
wherein the first gate signal is supplied to the second transistor in each of the plurality of pixels once per one frame, and the second gate signal is supplied to third transistor in each of the plurality of pixels at least twice per one frame, and
wherein a time taken for the first gate signal to be supplied to the second transistor in each of the plurality of pixels during one frame is less than or equal to a period during which the second gate signal is supplied to the third transistor in each of the plurality of pixels during one frame.
Kim '696 teaches the first gate signal is supplied to the second transistor in each of the plurality of pixels once per one frame ( ¶104 explained in low frequency driving in which a length of one frame period is increased, when on-bias is applied to the first transistor M1 using a signal supplied from the data line Djm by turning on the second transistor M2 ) once per one frame (1 frame RR=60Hz, see Fig 7C);
the second gate signal is supplied to third transistor in each of the plurality of pixels at least twice per one frame ( ¶131 and ¶133 explained the transistor M7 maintains a turn-on state in the first period P1, the voltage of the initialization power source Vint is supplied; transistor M7 maintains a turn-on state until the fourth period P4, the voltage of the initialization power source Vint is supplied during the fourth period P4. Fig 14C and ¶254- ¶262 explained three initializing voltages periods in one frame, or one refresh rate, e.g., RR = 60Hz );
a time taken for the first gate signal to be supplied to the second transistor in each of the plurality of pixels during one frame is less than or equal to a period during which the second gate signal is supplied to the third transistor in each of the plurality of pixels during one frame ( Fig 7C and ¶ 193 explained one display scan period DSP is less than three self-scan periods during one frame, or one refresh rate, e.g., RR= 60Hz ).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the three initializing voltages periods in one frame RR = 60Hz, one display scan period DSP is less than three self-scan periods during one frame RR= 60Hz as teaches by Kim '696, to modify the pixel circuit of Lin. The motivation for doing so would improve the high quality of the image being displayed, while driving at a low frequency. See Kim '696 ¶ 6.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin and Kim '696 as applied to claim 12 above, and further in view of Shin et al. US 2020/0184900.
As to claim 13, Lin and Kim '696 fail to teach first data lines connected to pixels arranged in odd pixel rows and second data lines connected to pixels arranged in even pixel rows, one of the first data lines and one of the second data lines are arranged adjacent to each other in each pixel column.
Shin teaches pixels PXL included in a single pixel column alternately coupled to a pair of data lines, the pixels included in odd-numbered rows (or first pixels), among pixels PXL included in a first column, coupled to a first odd-numbered data line Dka (or a first data line), and pixels included in even-numbered rows (or second pixels), among the pixels PXL included in the first column, coupled to a first even-numbered data line Dkb (or a second data line). See Shin ¶58, ¶80, and Figs 2A, 2B.
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a single pixel column alternately coupled to a pair of data lines, the pixels included in odd-numbered rows, among pixels PXL included in a first column, coupled to a first odd-numbered data line Dka, and pixels included in even-numbered rows, among the pixels PXL included in the first column, coupled to a first even-numbered data line Dkb, as teaches by Shin, to modify the pixel circuit of Lin and Kim '696. The motivation for doing so would improve the high quality of the image being displayed, while reducing the time suitable to charge a data signal in each pixel, and saving power consumption. Shin ¶5.
Claim(s) 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Kim '696 and Shin as applied to claim 13 above, and further in view of Lee et al. US 2021/0202759.
As to claim 14, Lin and Kim '696 and Shin fail to teach the first transistor comprises a lower gate electrode supplied with a driving voltage; an upper gate electrode supplied with a voltage corresponding to the data signal that is supplied through the data line; and a semiconductor layer arranged between the lower gate electrode and the upper gate electrode.
Figure 7 of Lee teaches the first transistor (a driving transistor T1) has a lower gate electrode (G1a) supplied with a driving voltage; an upper gate electrode (G1b) supplied with a voltage corresponding to the data signal that is supplied through the data line, a semiconductor layer (C1) arranged between the lower gate electrode (G1a) and the upper gate electrode (G1b). See Lee ¶142, and ¶174-¶175.
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the first transistor (a driving transistor T1) has a lower gate electrode (G1a) supplied with a driving voltage; an upper gate electrode (G1b) supplied with a voltage corresponding to the data signal that is supplied through the data line, a semiconductor layer (C1) arranged between the lower gate electrode (G1a) and the upper gate electrode (G1b), as teaches by Lee in Fig. 7, to modify the pixel circuit of Lin and Kim '696 and Shin. The motivation for doing so would improve the high resolution, while reducing area of pixel circuit. Lee ¶172.
As to claim 15, Lee teaches the display apparatus of claim 14, wherein the semiconductor layer of the first transistor comprises a silicon semiconductor.
( Lee [0013] the first semiconductor layer may include a silicon semiconductor material or an oxide semiconductor material. )
As to claim 16, Lee teaches the display apparatus of claim 14, wherein the second transistor comprises a lower gate electrode; an upper gate electrode connected to the lower gate electrode; and a semiconductor layer arranged between the lower gate electrode and the upper gate electrode.
( Lee [0084] Referring to FIG. 4, a thin-film transistor substrate TB according to an embodiment may include a thin-film transistor T having a semiconductor layer A, a lower gate electrode Ga, an upper gate electrode Gb, and an electrode layer E, wherein the semiconductor layer A may have a channel area C, a source area S, and a drain area D, and the electrode layer E may be disposed on or above the upper gate electrode Gb and may be electrically connected to at least one of the source area S and the drain area D. The lower gate electrode Ga may overlap the semiconductor layer A, but may overlap the channel area C and the drain area D.)
As to claim 17, Lee teaches the display apparatus of claim 16, wherein the semiconductor layer of the second transistor comprises an oxide semiconductor.
(Lee [0013] the first semiconductor layer may include a silicon semiconductor material or an oxide semiconductor material.)
Allowable Subject Matter
Claims 9-11 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of prior art of record teaches wherein the lower gate electrode of the first transistor is arranged between the upper gate electrode of the driving transistor and the semiconductor layer of the first transistor, and wherein the upper gate electrode of the driving transistor is arranged between the semiconductor layer of the driving transistor and the lower gate electrode of the first transistor.
Conclusion
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KEVIN M NGUYEN
Patent Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628 Telephone: (571) 272-7697
Email: kevin.nguyen2@uspto.gov