Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Vlaiko et al. (US 12,417,030), hereinafter Vlaiko.
Regarding claim 1, Vlaiko teaches an apparatus (Vlaiko, Fig. 1 & Fig. 3), comprising:
a number of dies including a first die and a second die (Vlaiko, Fig. 3, controller 302, memory 308 contains die 310);
the first die configured to:
receive data bits and error correction information from the second die via inter-die connectors (Vlaiko, Fig. 4 teaches data bytes being transmitted from the controller to a die via TM [Toggle Mode] Data Bus I/F and data integrity information being transmitted from the controller to a die via TM [Toggle Mode] DBI pins; col. 16, lines 53-54, “In some implementations, the data integrity information 424 may be implemented as a CRC bit”);
generate new error correction information corresponding to the data bits via error correction circuitry (Vlaiko, Fig. 7, block 702); and
write the data bits to data storage elements responsive to a determination that the error correction information matches the new error correction information (Vlaiko, Fig. 8, blocks 808, 810, & 812).
Vlaiko fails to explicitly teach implementing the controller and memory device as respective dies within a stack of memory dies, however this teaching is obvious to the teachings of Vlaiko because Vlaiko already teaches functional separation between a control component and a memory component, as well as the use of separate signal paths for data and error-correction information. Implementing these components as separate dies within a stacked-die memory architecture would be a predictable variation of the system taught in Vlaiko.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Vlaiko to implement the controller as a master die and the memory device as a target die within a stack of memory dies, wherein the target die writes data bits responsive to a determination that error correction information matches newly generated error correction information.
The suggestion/motivation for doing so would be to improve data integrity while reducing signal distance and latency in high speed memory systems.
Regarding claim 2, Vlaiko teaches the apparatus of claim 1, wherein the first die is configured to refrain from writing the data bits to the data storage elements responsive to a determination that the error correction information is different from the new error correction information (Vlaiko, Fig. 8 blocks 810 & 814 teach that when an error is detected, data is not written to the memory, instead an error indication is provided).
Regarding claim 3, Vlaiko teaches the apparatus of claim 2, wherein the first die is configured to provide the error correction information to the second die responsive to the determination that the error correction information is different from the new error correction information (Vlaiko, Fig. 8, blocks 808, col. 20, line 67 through col. 21, lines 1-4, “If the CRC checker 538 determines that the expected information does not match the data integrity information, then the CRC checker 538 may determine that an error occurred in the data transfer of the read operation”; col. 21, lines 4-8, “In response to detecting the error in the data transfer based on the data integrity information, then the controller 502 may store a record of the read error in a local register for subsequent access via the TM data bus 504 with a ‘check read’ command or a ‘status read’ command”).
Regarding claim 4, Vlaiko teaches the apparatus of claim 1, wherein the first die is configured to:
receive the data bits from the second die via inter-die data connectors of the inter-die connectors die (Vlaiko, Fig. 4 teaches data bytes being transmitted from the controller to a die via TM [Toggle Mode] Data Bus I/F); and
receive the error correction information corresponding to the data bits from the second die via inter-die error correction connectors of the inter-die connectors (Vlaiko, Fig. 4 teaches data integrity information being transmitted from the controller to a die via TM [Toggle Mode] DBI pins). Vlaiko teaches data bits being transmitted over toggle mode data buses and transmitting error correction information over separate DBI pins, which teaches receiving data bits via inter-die data connectors and receiving error correction information via separate inter-die error correction connectors.
Regarding claim 5, Vlaiko teaches the apparatus of claim 1, but fails to explicitly teach wherein at least some of the inter-die connectors comprise either wire bonds or through-silicon-vias (TSVs).
However, this teaching would have been obvious to one of ordinary skill in the art, because wire bonds and TSVs are well-known techniques for implementing physical interconnections between dies.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Vlaiko to implement the inter-die connectors using wire bonds or TSVs.
The suggestion/motivation for doing so would be to implement known physical interconnection techniques suitable for the desired performance of the interconnectors.
Regarding claim 6, Vlaiko teaches the apparatus of claim 1, wherein the first die is configured to:
receive additional data bits from the data storage elements (Vlaiko, col. 13, lines 6-9, “As shown in FIG. 3, a storage device may include a controller 302 having a set of flash interface modules (FIMs ), which may work in parallel or asynchronously with one other, e.g., to read and/or write data to the memory 308. The storage device may further include the memory 308 having a set of dies, and correspondingly, the dies may communicate with the FIMs”; col. 13, lines 26-31, “when the FIM 304 executes a read operation to read data in the die 310, the die 310 may transfer (or send) the data to the FIM 304 on the channel 315 (e.g., a read channel). Correspondingly, the FIM 304 may receive the data from the die 310 on the channel 316”);
generate additional error correction information corresponding to the additional data bits using the error correction circuitry (Vlaiko, col. 21, lines 32-33, “The integrity information generator 506 may generate data integrity information based on the read data”);
provide the additional data bits to the second die via the inter-die connectors (Vlaiko, col. 19, lines 65-67, “When the controller 502 is to read data (e.g., at least one byte of data) from the NAND die 510, the NAND die 510 may send the data through the TM data bus interface 514”); and
provide the error correction information corresponding to the additional data bits to the second die via the inter-die connectors (Vlaiko, col. 13, lines 46-51, “Illustratively, the FIM 304 may pass the data to the integrity information generator 306 as an input, and the integrity information generator 306 may output the data integrity information with the data so that the data is transferred to the die 310 with the data integrity information”).
Regarding claim 7, Vlaiko teaches an apparatus (Vlaiko, Fig. 1 & Fig. 3), comprising:
a master die (Vlaiko, Fig. 3, controller 302); and
a target die coupled to the master die (Vlaiko, Fig. 3, memory 308 & die 310) and configured to:
receive error correction information and write data bits from the master die (Vlaiko, Fig. 4 teaches data bytes being transmitted from the controller to a die via TM [Toggle Mode] Data Bus I/F and data integrity information being transmitted from the controller to a die via TM [Toggle Mode] DBI pins; col. 16, lines 53-54, “In some implementations, the data integrity information 424 may be implemented as a CRC bit”);
generate new error correction information responsive to the write data bits (Vlaiko, Fig. 7, block 702); and
provide error information to the master die responsive to the new error correction information being different than the error correction information (Vlaiko, Fig. 8, blocks 808, 810, 812, & 814).
Vlaiko fails to explicitly teach implementing the controller and memory device as respective dies within a stack of memory dies, however this teaching is obvious to the teachings of Vlaiko because Vlaiko already teaches functional separation between a control component and a memory component, as well as the use of separate signal paths for data and error-correction information. Implementing these components as separate dies within a stacked-die memory architecture would be a predictable variation of the system taught in Vlaiko.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Vlaiko to implement the controller as a master die and the memory device as a target die within a stack of memory dies, wherein the target die provides error information to the master die responsive to detecting an error.
The suggestion/motivation for doing so would be to enable efficient error handling and retry operations in stacked memory architectures.
Regarding claim 8, Vlaiko teaches the apparatus of claim 7, further comprising:
inter-die data connectors for providing the write data bits from the master die to the target die (Vlaiko, Fig. 4 teaches data bytes being transmitted from the controller to a die via TM [Toggle Mode] Data Bus I/F); and
inter-die error correction connectors for providing the error correction information from the master die to the target die (Vlaiko, Fig. 4 teaches data integrity information being transmitted from the controller to a die via TM [Toggle Mode] DBI pins).
Regarding claim 9, Vlaiko teaches the apparatus of claim 8, but fails to teach wherein at least some of the inter-die data connectors and the inter-die error correction connectors comprises wire bonds, through-silicon-vias (TSVs), or both.
However, this teaching would have been obvious to one of ordinary skill in the art, because wire bonds and TSVs are well-known techniques for implementing physical interconnections between dies.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Vlaiko to implement the inter-die connectors using wire bonds or TSVs.
The suggestion/motivation for doing so would be to implement known physical interconnection techniques suitable for the desired performance of the interconnectors.
Regarding claim 10, Vlaiko teaches the apparatus of claim 7, wherein the error correction information comprises cyclic redundancy check (CRC) bits (Vlaiko, col. 6, lines 9-10, “In one implementation, CRC information is used on both write and read paths accessing the NAND dies”).
Regarding claim 11, Vlaiko teaches the apparatus of claim 7, but fails to explicitly teach wherein the error correction information comprises two error correction bits for every sixteen bits of the write data bits.
However, selecting a particular number of CRC bits relative to a given data width, would have been an obvious design choice to one of ordinary skill in the art, because CRC bit widths are routinely selected based on desired error detection capability and implementation constraints.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Vlaiko to have the error correction information comprising two error correction bits for every sixteen bits.
The suggestion/motivation for doing so would be to balance error detection capability.
Regarding claim 12, Vlaiko teaches the apparatus of claim 7, further comprising control circuitry operably coupled to the master die, the control circuitry configured to receive the error information from the master die and repeat a write operation responsive to the error information (Vlaiko, col. 12, lines 41-52, “However, if the data integrity circuit(s) 115 determines that an error is detected in the at least one byte of data based on the data integrity information, then the data integrity circuit(s) 115 may indicate the detected error to the controller 123, such as by sending a write error response to a "status read" register with a "check write" command or as a "program" command. In response to receiving the write error response, e.g., on a "status read" register with "check write" command or a "program" command, the controller 123 may resend and/or reschedule the at least one data byte for transfer over the bus/interface to the respective one of the memory locations 112”).
Regarding claim 13, Vlaiko teaches the apparatus of claim 7, wherein the master die includes clock circuitry configured to clock target data shift registers of the target die to shift the write data bits from the master die to the target die (Vlaiko, col. 17, lines 3-7, “In some implementations, the data integrity information 424 may be a single bit that is toggled from across the TM DBI pins 406, 416 at the same clock rate as the data byte 422 across the TM data bus interfaces 404, 414”) but fails to explicitly teach in two bursts of eight bits each for every nine clock cycles of a clock provided to the clock circuitry.
This teaching would have been obvious to one of ordinary skill in the art, because selecting a particular burst size and clock-to-data ration represents a routine design choice dependent on interface timing requirements and data size/width.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Vlaiko to shift write data in two bursts of eight bits for every nine clock cycles.
The suggestion/motivation for doing so would be to meet desired timing and interface efficiency constraints.
Regarding claim 14, Vlaiko teaches the apparatus of claim 13, wherein the clock circuitry is further configured to clock target error shift registers of the target die to shift the error correction information from the master die to the target die (Vlaiko, col. 5, lines 18-23, “In some aspects, the CRC may be pre-calculated at the transmitter to generate a number of clock cycles for transferring the data along with transferring the serial CRC bitstream over the DBI interface with a number of clock cycles that corresponds to the amount of data bytes being transferred”) but fails to explicitly teach in a single burst of two bits for every nine clock cycles of the clock.
This teaching would have been obvious to one of ordinary skill in the art, because selecting a particular burst size and clock-to-data ration represents a routine design choice based on interface timing requirements and error detection requirements.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Vlaiko to shift write data in two bursts of eight bits for every nine clock cycles.
The suggestion/motivation for doing so would be to efficiently transmit error correction information.
Regarding claim 15, Vlaiko teaches an apparatus (Vlaiko, Fig. 1 & Fig. 3), comprising:
a master die (Vlaiko, Fig. 1, controller 123, Fig. 3, controller 302);
a target die (Vlaiko, Fig. 1, NVM 110, Fig. 3, memory 308 contains die 310) including error correction circuitry configured to generate error correction information based on data bits (Vlaiko, Fig. 1, data integrity circuit 115; col. 12, lines 63-66, “In the context of FIG. 1, for example, the controller 302 may be implemented as the controller 123, the memory 308 may be implemented as the NVM 110 [e.g., including or connected with the data integrity circuit(s) 115]”);
inter-die error correction connectors configured to provide the error correction information between the target die and the master die (Vlaiko, Fig. 4 teaches data integrity information being transmitted from the controller to a die via TM [Toggle Mode] DBI pins); and
inter-die data connectors configured to provide the data bits between the target die and the master dies (Vlaiko, Fig. 4 teaches data bytes being transmitted from the controller to a die via TM [Toggle Mode] Data Bus I/F), wherein the target die is configured to trigger the master die to obtain the data bits from the target die (Vlaiko, Fig. 8, blocks 808, 810, 812, & 814 teach the presence of an error determining whether data is written into memory).
Vlaiko fails to explicitly teach implementing the controller and memory device as respective dies within a stack of memory dies, however this teaching is obvious to the teachings of Vlaiko because Vlaiko already teaches functional separation between a control component and a memory component, as well as the use of separate signal paths for data and error-correction information. Implementing these components as separate dies within a stacked-die memory architecture would be a predictable variation of the system taught in Vlaiko.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Vlaiko to implement the controller as a master die and the memory device as a target die within a stack of memory dies, while maintaining separate inter-die data connectors and inter-die error correction connectors.
The suggestion/motivation for doing so would be to improve signal integrity.
Regarding claim 16, Vlaiko teaches the apparatus of claim 15, wherein the target die includes clock circuitry (Vlaiko, col. 17, lines 3-7, “In some implementations, the data integrity information 424 may be a single bit that is toggled from across the TM DBI pins 406, 416 at the same clock rate as the data byte 422 across the TM data bus interfaces 404, 414”), but fails to explicitly teach configured to trigger the master die to obtain the data bits from the target die.
However, this teaching would have been obvious to one of ordinary skill in the art because bi-directional clock-based communication between stacked dies is a known design technique for coordinating inter-die data transfers.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Vlaiko to implement clock-based triggered data transfers.
The suggestion/motivation for doing so would be to enable flexible timing coordination and synchronization in stacked die memory architectures.
Regarding claim 17, Vlaiko teaches the apparatus of claim 15, wherein the target die is configured to read the data bits from or write the data bits to data storage elements of the target die (Vlaiko, col. 13, lines 6-12, “As shown in FIG. 3, a storage device may include a controller 302 having a set of flash interface modules (FIMs), which may work in parallel or asynchronously with one other, e.g., to read and/or write data to the memory 308. The storage device may further include the memory 308 having a set of dies, and correspondingly, the dies may communicate with the FIMs”).
Regarding claim 18, Vlaiko teaches the apparatus of claim 15, but fails to teach wherein the error correction information comprises two error correction bits for every sixteen bits of the data bits.
However, selecting a particular number of CRC bits relative to a given data width, would have been an obvious design choice to one of ordinary skill in the art, because CRC bit widths are routinely selected based on desired error detection capability and implementation constraints.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Vlaiko to have the error correction information comprising two error correction bits for every sixteen bits.
The suggestion/motivation for doing so would be to balance error detection capability.
Regarding claim 19, Vlaiko teaches a method of operating a stack of memory dies, the method comprising:
receiving, by a master die of the stack of memory dies, data bits and error correction information associated with the data bits from control circuitry (Vlaiko, Fig. 3 & Fig. 4 teaches data bytes being transmitted from the controller to a die via TM [Toggle Mode] Data Bus I/F and data integrity information being transmitted from the controller to a die via TM [Toggle Mode] DBI pins);
sending the data bits and the error correction information to a target die of a stack of memory dies through inter-die data connectors (Vlaiko, Fig. 3 & Fig. 4);
generating, by the target die, new error correction information associated with the data bits (Vlaiko, Fig. 7, block 702);
comparing, by the target die, the error correction information to the new error correction information (Vlaiko, Fig. 8, blocks 808, col. 20, line 67 through col. 21, lines 1-4, “If the CRC checker 538 determines that the expected information does not match the data integrity information, then the CRC checker 538 may determine that an error occurred in the data transfer of the read operation”); and
generating error information responsive to a determination that the error correction information is different from the new error correction information (Vlaiko, col. 21, lines 4-8, “In response to detecting the error in the data transfer based on the data integrity information, then the controller 502 may store a record of the read error in a local register for subsequent access via the TM data bus 504 with a ‘check read’ command or a ‘status read’ command”).
Vlaiko fails to explicitly teach implementing the controller and memory device as respective dies within a stack of memory dies, however this teaching is obvious to the teachings of Vlaiko because Vlaiko already teaches functional separation between a control component and a memory component, as well as the use of separate signal paths for data and error-correction information. Implementing these components as separate dies within a stacked-die memory architecture would be a predictable variation of the system taught in Vlaiko.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have Vlaiko to implement the controller as a master die and the memory device as a target die within a stack of memory dies.
The suggestion/motivation for doing so would be to reduce latency and improve bandwidth in memory systems.
Regarding claim 20, Vlaiko teaches the method of claim 19, but fails to explicitly teach further comprising writing the data bits to data storage elements of the target die responsive to a determination that the error correction information matches the new error correction information.
However, Vlaiko teaches generating error correction information associated with write data and comparing the error correction information to determine whether an error condition exists. Vlaiko further teaches repeating a write operation when an error is detected (Vlaiko, col. 12, lines 41-52, “However, if the data integrity circuit(s) 115 determines that an error is detected in the at least one byte of data based on the data integrity information, then the data integrity circuit(s) 115 may indicate the detected error to the controller 123, such as by sending a write error response to a "status read" register with a "check write" command or as a "program" command. In response to receiving the write error response, e.g., on a "status read" register with "check write" command or a "program" command, the controller 123 may resend and/or reschedule the at least one data byte for transfer over the bus/interface to the respective one of the memory locations 112”).
The teaching of the limitation would have been obvious to one of ordinary skill in the art, because completing a write operation only when error detection indicates valid data is a fundamental principle of reliable memory operation.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Vlaiko to write data in response to the error detection operation indicating valid data.
The suggestion/motivation for doing so would be to ensure data integrity by preventing corrupted data from being written to memory storage elements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bains et al. (US 12,181,966) teaches on-die ECC circuitry, with error correction circuitry in both a controller component and a memory die component.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112