DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 9 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 9 and 15 of U.S. Patent No. 12,163,995.
Although the claims at issue are not identical, they are not patentably distinct from each other because they merely omit features that is recited in the claim 1 of US Patent No. 12,163,995 such as “wherein the high and low side transistors, the high and low side drivers, and the integrated driver circuit are all fabricated on a same semiconductor device layer, and wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer”. The omission of the features results in claims that are broader in scope than claims of the Patent. It would have been an obvious to one of the ordinary skill in the art to remove or not include limitation “wherein the high and low side transistors, the high and low side drivers, and the integrated driver circuit are all fabricated on a same semiconductor device layer, and wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer” particularly where the remaining elements of the claimed invention are otherwise identical or substantially similar (see table below).
Instant application 18/936841
US Patent No. 12,163,995
1. A reliability testing apparatus for stacked transistors, comprising: a high side transistor; a low side transistor; a high side driver coupled to the high side transistor; a low side driver coupled to the low side transistor; an integrated driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side transistors, wherein the high and low side transistors are connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter.
1. A reliability testing apparatus for stacked transistors, comprising: a high side transistor; a low side transistor; a high side driver coupled to the high side transistor; a low side driver coupled to the low side transistor; an integrated driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side transistors, wherein the high and low side transistors are connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter,
wherein the high and low side transistors, the high and low side drivers, and the integrated driver circuit are all fabricated on a same semiconductor device layer, and wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
9. A built-in self-test circuit for testing reliability of one or more transistors, comprising: a transistor test switch; a driver circuit coupled to a gate of the transistor test switch; an integrated chopper circuit coupled to the driver circuit and configured to generate a drive signal capable of driving the transistor test switch, wherein the transistor test switch is connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure a dynamic on-state resistance (Rdson) of the transistor test switch, wherein the dynamic on-state resistance (Rdson) is determined by: a first voltage probe configured to measure drain to source voltages of the transistor test switch, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter.
9. A built-in self-test circuit for testing reliability of one or more transistors, comprising: a transistor test switch; a driver circuit coupled to a gate of the transistor test switch; an integrated chopper circuit coupled to the driver circuit and configured to generate a drive signal capable of driving the transistor test switch, wherein the transistor test switch is connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure a dynamic on-state resistance (Rdson) of the transistor test switch, wherein the dynamic on-state resistance (Rdson) is determined by: a first voltage probe configured to measure drain to source voltages of the transistor test switch, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the transistor test switch, the driver circuit, and the integrated chopper circuit are all fabricated on a same device semiconductor layer, and wherein interconnections that couple the integrated chopper circuit, the driver circuit, and the transistor test switch are patterned on a same metallization layer.
15. A method for reliability testing one or more transistors, the method comprising: generating drive signals by an integrated driver circuit; driving gates of high and low side transistors by a high and low side drivers, respectively, wherein the high and low side transistors are connected to a plurality of monitoring pads and wherein the high and low side drivers receive the drive signals from the integrated driver circuit; and measuring dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) of the high and low side transistors are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter.
15. A method for reliability testing one or more transistors, the method comprising: generating drive signals by an integrated driver circuit; driving gates of high and low side transistors by a high and low side drivers, respectively, wherein the high and low side transistors are connected to a plurality of monitoring pads and wherein the high and low side drivers receive the drive signals from the integrated driver circuit; fabricating the high and low side transistors, the high and low side drivers, and the integrated driver circuit on a same device semiconductor layer; and measuring dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) of the high and low side transistors are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
Claims 2-8, 10-14 and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-8, 10-14 and 16-20 of U.S. Patent No. 12,163,995.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842