Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-20 are presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12165739. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-11 of the examined application are anticipated and the same scope of invention by claims 1-11 of the reference such as a memory circuit comprising: a first latch circuit configured to receive a sleep signal and a first bit line pre-charge signal and to generate a first delayed sleep signal; and first logic circuitry configured to generate a second bit line pre-charge signal in response to the first delayed sleep signal.
Claims 12-19 of the examined application are anticipated and the same scope of invention by claims 12-19of the reference such as a method comprising: generating, at first logic circuitry, a first bit line pre-charge signal in response to a sleep signal; and generating, at a first latch circuit, a first delayed sleep signal in response to the sleep signal and the first bit line pre-charge signal.
Claim 20 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory circuit comprising: a latch configured to generate a delayed sleep signal in response to a sleep signal and a first bit line pre-charge signal; a bit line delay tracking element configured to delay operation of the latch; and logic circuitry configured to generate a second bit line pre-charge signal in response to the delayed sleep signal.
5. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11763863. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-11 of the examined application are anticipated and the same scope of invention by claims 1-11 of the reference such as a memory circuit comprising: a first latch circuit configured to receive a sleep signal and a first bit line pre-charge signal and to generate a first delayed sleep signal; and first logic circuitry configured to generate a second bit line pre-charge signal in response to the first delayed sleep signal.
Claims 12-19 of the examined application are anticipated and the same scope of invention by claims 12-19of the reference such as a method comprising: generating, at first logic circuitry, a first bit line pre-charge signal in response to a sleep signal; and generating, at a first latch circuit, a first delayed sleep signal in response to the sleep signal and the first bit line pre-charge signal.
Claim 20 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory circuit comprising: a latch configured to generate a delayed sleep signal in response to a sleep signal and a first bit line pre-charge signal; a bit line delay tracking element configured to delay operation of the latch; and logic circuitry configured to generate a second bit line pre-charge signal in response to the delayed sleep signal.
6. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11309000. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-11 of the examined application are anticipated and the same scope of invention by claims 1-11 of the reference such as a memory circuit comprising: a first latch circuit configured to receive a sleep signal and a first bit line pre-charge signal and to generate a first delayed sleep signal; and first logic circuitry configured to generate a second bit line pre-charge signal in response to the first delayed sleep signal.
Claims 12-19 of the examined application are anticipated and the same scope of invention by claims 12-19of the reference such as a method comprising: generating, at first logic circuitry, a first bit line pre-charge signal in response to a sleep signal; and generating, at a first latch circuit, a first delayed sleep signal in response to the sleep signal and the first bit line pre-charge signal.
Claim 20 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory circuit comprising: a latch configured to generate a delayed sleep signal in response to a sleep signal and a first bit line pre-charge signal; a bit line delay tracking element configured to delay operation of the latch; and logic circuitry configured to generate a second bit line pre-charge signal in response to the delayed sleep signal.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-9, 12-13 and 15-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Choi et al. US Pub. No. 20050286322 (IDS).
As per claims 1 and 12, Figs. 5 and 6 of Choi are directed to a memory circuit (SRAM, par. 49) comprising: a first latch circuit (32) configured to receive a sleep signal (SC, par. 50 or Fig. 6) and a first bit line pre-charge signal (at 38, par. 52) to generate a first delayed sleep signal (SC1) and first logic circuitry (43) configured to generate a second bit line pre-charge signal (at 38 of the subsequent block, par. 56 or 62), in response to the first delayed sleep signal.
As claims 2, 4, 6, and 8, block 32 in Fig. 5 of Choi discloses wherein the first latch circuit is configured to cause a logic state transition in the first delayed sleep signal to occur after a logic state transition (VDD) in the first bit line pre-charge signal.
As per claims 3, 5, 7, 13, and 16-17, Fig. 5 and paragraphs 49 and 62 of Choi disclose further comprising: second logic circuitry configured to generate the first bit line pre-charge signal in response to the sleep signal; a second latch circuit configured to receive the first delayed sleep signal and the second bit line pre-charge signal and to generate a second delayed sleep signal; and third logic circuitry configured to generate a third bit line pre-charge signal in response to the second delayed sleep signal (a number of blocks 32 for corresponding to a plurality of blocks in SRAM, par. 49).
As per claim 9, Figs. 5-6 and paragraph 62 of Choi disclose further comprising: a second delay circuit (32, par. 62) configured to receive the second delayed sleep signal and to generate a third delayed sleep signal (SC2); and fourth logic circuitry (42) configured to generate a fourth bit line pre-charge signal in response to the third delayed sleep signal (par. 62).
As per claims 15 and 18, Fig. 6 of Choi discloses wherein the first delayed sleep signal, second delayed sleep signal, and third delayed sleep signal are generated sequentially.
As per claim 19, Fig. 5 of Choi discloses further comprising delaying operation of the first latch circuit in generating the first delayed sleep signal by a time delay corresponding to an RC delay of the one or more bit lines (a wire connecting from /BL to Sbit in Fig. 5, par. 52).
As per claim 20, Fig. 5 of Choi is directed to a memory circuit comprising: a latch (32) configured to generate a delayed sleep signal (SC1 at a node 39, Fig. 6) in response to a sleep signal (SC, Fig. 6) and a first bit line pre-charge signal (38, par. 52); a bit line delay tracking element (a wire connecting from /BL to Sbit, par. 52) configured to delay operation of the latch (Fig. 6); and logic circuitry (43) configured to generate a second bit line pre-charge signal (at 38 of the subsequent block, par. 56 or 62) in response to the delayed sleep signal.
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
11. Claim 11 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Choi et al. US Pub. No. 20050286322 (IDS).
Choi discloses all the subject matter except for wherein the first latch circuit includes an SR latch. However, the precharge delay circuit 32 of Choi is used to generate the first delayed sleep signal.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time invention was made to use either the SR latch of the invention or the precharge delay circuit 32 of Choi since these two elements were art-recognized equivalents and have the same functions to generate the first delayed sleep signal.
12. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
13. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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