DETAILED ACTION
1. This Office Action is responsive to claims filed for App. 18/937,249 on October 28, 2025. Claims 1-20 are pending.
America Invents Act
2. The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 12, 2025 has been entered.
Allowable Subject Matter
4. Claims 3-12 and 15-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The claimed limitations recite aspects relating to a demultiplexer which can alternately supply signals to different data lines based on respective control signals. This level of detail, in conjunction with earlier limitations focusing on the data signals, etc, are not taught by the prior art.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1, 2, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. ( US 2023/0108865 A1 ) in view of Toyada ( US 2021/0398487 A1 ).
Kim teaches in Claim 1:
A display apparatus ( Figure 1, [0046] discloses a display device 1000 ), comprising:
a plurality of pixels ( Figure 1, [0058] shows a display panel which can include a plurality of pixels PX ), wherein each of the plurality of pixels comprises:
a light-emitting device ( Figure 2, [0079] disclose a light emitting element LD );
a first transistor configured to control a current supplied to the light-emitting device ( Figure 1, [0080]-[0081] discloses the first transistor T1 for generating a driving current to the light emitting element LD );
a second transistor connected to a data line ( Figure 2, [0084] discloses the second transistor T2 connected to a data line DLj );
a third transistor connected between a second terminal of the first transistor and a gate of the first transistor ( Figure 2, [0085] discloses the third transistor T3 connected between a second terminal of T1 as well as a gate of T1 );
a fourth transistor connected between a first terminal of the first transistor and a driving voltage line ( Figure 2, [0089] discloses the sixth transistor T6 connected between a first terminal of T1 and VDD ); and
a fifth transistor connected between the second terminal of the first transistor and the light-emitting device ( Figure 2, [0090] discloses the seventh transistor T7 connected between the second terminal of T1 and the light emitting element LD ),
wherein a first gate of the fourth transistor and a gate of the fifth transistor are connected to a first gate line that supplies a first gate signal having a gate-on voltage during an emission period ( Figure 2 shows the first gate of T6 and T7 are connected to emission control line Eli. Please note Applicant’s own Figure 4A with a connection to EML/EM in a similar manner. As for the gate-on during an emission period, please note Figure 3A for ELi ); but
Kim does not explicitly teach of a second gate for T6, namely “a gate of the third transistor and a second gate of the fourth transistor are connected to a second gate line that supplies a second gate signal.”
However, dual gate structures are well known in the art. To emphasize, in the same field of endeavor, pixel circuits, Toyoda teaches of a pixel circuit with multiple double gate structures, ( Toyoda, Figure 17, ( [0149] ). Notably, TRDS is a light emission transistor (akin to Kim’s T6) with a back gate connected to gate line VSB, as well as sharing this VSB gate line with TRAZ2 (read as a compensation transistor akin to Kim’s T3). As combined with Kim, the emission transistor T6 is provided a back gate connected to the same gate line as the claimed third transistor. Both T6 and T7 are emission control transistors and have a gate-on voltage during an emission period (which Kim already teaches in Figure 3A), for the front gate, and given the connection to VSB, the back gates have different, non-overlapping gate-on times with the front gate. To clarify, Kim’s T3 is not on at the same times as T6 and T7, given the different periods of operation.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the emission control transistor with two gates, one of which is connected to the same gate line as the compensation transistor, as taught by Toyoda, with the motivation that by controlling various transistors together, fluctuations in power to the circuit can be minimized, ( Toyoda, [0128] ).
Kim teaches in Claim 2:
The display apparatus of claim 1, wherein each of the plurality of pixels further comprises:
a first capacitor connected between the gate of the first transistor and the second transistor ( Figure 2, [0082] discloses the first capacitor C1 connected between the gate of T1 and T2 );
a second capacitor connected between the second transistor and the driving voltage line ( Figure 2, [0083] discloses the second capacitor C2 connected between T2 and VDD );
a sixth transistor connected between the gate of the first transistor and a first voltage line ( Figure 2, [0086] discloses the fourth transistor T4 connected between a gate of T1 and Vint );
a seventh transistor connected between the light-emitting device and a second voltage line ( Figure 2, [0092] discloses the eight transistor T8 connected between the light emitting element LD and Vaint );
an eighth transistor connected between the second transistor and a third voltage line ( Figure 2, [0087] discloses the fifth transistor T5 connected between T2 and VREF ); and
a ninth transistor configured to supply a bias voltage to the first terminal of the first transistor. ( Figure 2, [0094] discloses the ninth transistor T9 applying a bias power Vbs to the first terminal of T1 )
Kim teaches in Claim 13:
A display apparatus ( Figure 1, [0046] discloses a display device 1000 ), comprising:
a plurality of pixels ( Figure 1, [0058] shows a display panel which can include a plurality of pixels PX ), wherein each of the plurality of pixels comprises:
a light-emitting device ( Figure 2, [0079] disclose a light emitting element LD );
a first transistor configured to control a current supplied to the light-emitting device ( Figure 1, [0080]-[0081] discloses the first transistor T1 for generating a driving current to the light emitting element LD );
a second transistor connected to a data line ( Figure 2, [0084] discloses the second transistor T2 connected to a data line DLj );
a third transistor connected between a second terminal of the first transistor and a gate of the first transistor ( Figure 2, [0085] discloses the third transistor T3 connected between a second terminal of T1 as well as a gate of T1 );
a fourth transistor connected between a first terminal of the first transistor and a driving voltage line ( Figure 2, [0089] discloses the sixth transistor T6 connected between a first terminal of T1 and VDD ); and
a fifth transistor connected between the second terminal of the first transistor and the light-emitting device ( Figure 2, [0090] discloses the seventh transistor T7 connected between the second terminal of T1 and the light emitting element LD ),
[wherein a first gate signal having a gate-off voltage during an emission period is supplied to a gate of the third transistor and a first gate of the fourth transistor], and a second gate signal having a gate-on voltage during the emission period is supplied to a second gate of the fourth transistor and a gate of the fifth transistor. ( Figure 2 shows the first gate of T6 and T7 are connected to emission control line Eli. Please note Applicant’s own Figure 4A with a connection to EML/EM in a similar manner. As for the gate-on during an emission period, please note Figure 3A for ELi. Please see below for aspects of a first gate signal );
Kim does not explicitly teach of another gate of the fourth transistor, namely “a first gate signal having a gate-off voltage during an emission period is supplied to a gate of the third transistor and a first gate of the fourth transistor”.
However, dual gate structures are well known in the art. To emphasize, in the same field of endeavor, pixel circuits, Toyoda teaches of a pixel circuit with multiple double gate structures, ( Toyoda, Figure 17, ( [0149] ). Notably, TRDS is a light emission transistor (akin to Kim’s T6) with a back gate connected to gate line VSB, as well as sharing this VSB gate line with TRAZ2 (read as a compensation transistor akin to Kim’s T3). As combined with Kim, the emission transistor T6 is provided a back gate connected to the same gate line as the claimed third transistor. Both T6 and T7 are emission control transistors and have a gate-on voltage during an emission period (which Kim already teaches in Figure 3A), for the front gate, and given the connection to VSB, the back gates have different, non-overlapping gate-on times with the front gate. To clarify, Kim’s T3 is not on at the same times as T6 and T7, given the different periods of operation.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the emission control transistor with two gates, one of which is connected to the same gate line as the compensation transistor, as taught by Toyoda, with the motivation that by controlling various transistors together, fluctuations in power to the circuit can be minimized, ( Toyoda, [0128] ).
Kim teaches in Claim 14:
The display apparatus of claim 13, wherein each of the plurality of pixels further comprises:
a first capacitor connected between the gate of the first transistor and the second transistor ( Figure 2, [0082] discloses the first capacitor C1 connected between the gate of T1 and T2 );
a second capacitor connected between the second transistor and the driving voltage line ( Figure 2, [0083] discloses the second capacitor C2 connected between T2 and VDD );
a sixth transistor connected between the gate of the first transistor and a first voltage line ( Figure 2, [0086] discloses the fourth transistor T4 connected between a gate of T1 and Vint );
a seventh transistor connected between the light-emitting device and a second voltage line ( Figure 2, [0092] discloses the eight transistor T8 connected between the light emitting element LD and Vaint );
an eighth transistor connected between the second transistor and a third voltage line ( Figure 2, [0087] discloses the fifth transistor T5 connected between T2 and VREF ); and
a ninth transistor configured to supply a bias voltage to the first terminal of the first transistor. ( Figure 2, [0094] discloses the ninth transistor T9 applying a bias power Vbs to the first terminal of T1 )
Response to Arguments
8. Applicant’s arguments considered, but are respectfully moot in view of new grounds of rejection(s)>
In light of the claim amendments, please note the newly cited Toyoda reference. As a result, Applicant’s arguments are moot at this time.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621