Prosecution Insights
Last updated: July 17, 2026
Application No. 18/937,271

REUSING PARTIALLY FILLED SUPERBLOCKS FOR PROGRAMMING

Non-Final OA §103
Filed
Nov 05, 2024
Priority
Dec 14, 2023 — provisional 63/610,086
Examiner
REECE, CHRISTOPHER LANE
Art Unit
4100
Tech Center
4100
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
27 granted / 31 resolved
+27.1% vs TC avg
Strong +16% interview lift
Without
With
+15.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
19 currently pending
Career history
59
Total Applications
across all art units

Statute-Specific Performance

§103
88.3%
+48.3% vs TC avg
§102
8.3%
-31.7% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 31 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments. Priority The present application, 18/937271, claims priority to Provisional Application 63/610086, filed on December 14, 2023. The claim for priority through this chain is acknowledged as properly supported under 35 U.S.C. § 119(e). Information Disclosure Statement The Information Disclosure Statement (IDS) submitted on April 18, 2025 has been considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,219,776 B2 to Carl Forhan, et al. (hereafter Forhan) in view of US 8,199,583 B2 to You Sung Kim, et al. (hereafter Kim). Also referenced is Non-Patent Literature Kang, J.-U., Jo, H., Kim, J.-S., & Lee, J. (2006). A superblock-based flash translation layer for NAND flash memory. EMSOFT 2006: Proceedings of the Sixth ACM & IEEE International Conference on Embedded Software: October 22-25, 2006, Seoul, Korea, Embedded Systems Week 2006, 161–170. This literature is incorporated by reference in Forhan at col.3:31-37 but is identified separately for clarity of the record. Regarding Independent Claim 1, Forhan discloses a system comprising: a memory device (A flash memory storage system: Forhan, col.6:45); and a processing device (Flash controller 104: Forhan, Figure 2), operatively coupled with the memory device (The flash controller 104 operatively connected to the flash memory 118: Forhan, Figure 2), to perform operations comprising: initiating a programming operation (A write operation: Forhan, col.13:21-23) to write data to a set of pages of a superblock of the memory device (Writing data to a set of pages of the superblock: Forhan, col.13:23-25); determining whether to terminate the programming operation (Ending the write operation: Forhan, col.13:44-45); in response to determining to terminate the programming operation, causing the superblock to be closed to obtain a partially filled superblock comprising a set of closed pages (Disclosing maintaining a free page pointer to the next free page within the partially written superblock: Forhan, col.10:10-15; Partially filling and subsequently writing new data to a block inherently suggests closing the partial subblock to uncontrolled writes between the two operations); causing a second subset of closed pages of the set of closed pages to be reopened for programming to obtain a set of reopened pages (Allowing data to be written to the next available page in a partially filled superblock: Forhan, col.6:60-63). Forhan does not expressly disclose causing dummy data to be written to a first subset of closed pages of the set of closed pages to obtain a set of dummy pages. Kim, however, expressly teaches causing dummy data to be written to a first subset of closed pages of the set of closed pages to obtain a set of dummy pages (Writing dummy data to logical pages: Kim, col.6:14-17). Kim teaches writing dummy data to pad out unfilled pages converts the partially filled pages into a readable state (Kim, col.6:22-25). Kim discloses performing this padding operation on partially filled pages prior reading, thereby this inherently means performing the padding operation on otherwise closed pages. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the dummy padding operation of Kim, which is necessary to convert the partially filled pages into a readable state, with the partial fill operation of Forhan, with a reasonable expectation of success. Both inventions are well known in the field of managing partially filled data blocks and the combination of known inventions with predictable results is obvious and not patentable. Regarding Claim 2 and the substantially similar limitations of claims 9 and 16, Kang discloses the system of claim 1, wherein the operations further comprise causing programmed data to be migrated from a set of programmed pages of the partially filled superblock to a second set of pages of a second superblock (Disclosing a garbage collection process: Kang, §2.3 ¶5). Regarding Claim 3 and the substantially similar limitations of claims 10 and 17, Forhan discloses the system of claim 1, wherein the operations further comprise initiating a second programming operation to write second data to the set of reopened pages (Subsequent write operations to the next available page: Forhan, col.3:8-9). Regarding Claim 4 and the substantially similar limitations of claims 11 and 18, Forhan discloses the system of claim 1, wherein determining whether to terminate the programming operation comprises determining whether an amount of time that has elapsed from when the programming operation was initiated exceeds a threshold amount of time (Disclosing a periodic summary page update, therefore requiring a time based element: Forhan, col.15:53-57). Regarding Claim 5 and the substantially similar limitations of claims 12 and 19, Kim discloses the system of claim 1, wherein causing the first subset of closed pages to be programmed with dummy data comprises causing the dummy data to be written to at least one page associated with at least one wordline of the partially filled superblock (Writing data to at least one residual page of the superblock that has not been programmed: Kim, col.6:14-17). Regarding Claim 6 and the substantially similar limitations of claim 13, Kim discloses the system of claim 5, wherein the at least one page associated with the at least one wordline of the partially filled superblock comprises a last programmed page associated with a last written wordline prior to termination of the programming operation (Disclosing accessing the stored page may be the page that was programmed last: Kim, col.5:60-63). Regarding Claim 7 and the substantially similar limitations of claim 14, Forhan discloses the system of claim 6, wherein the set of reopened pages further comprises an initial page associated with a next wordline following the last written wordline (Pointer to the next available page within the superblock: Forhan, col.10:10-12). Regarding Independent Claim 8, Forhan discloses a method comprising: initiating, by a processing device (A memory controller: Forhan, Figure 2), a programming operation (A write operation: Forhan, col.13:21-23) to write data to a set of pages of a superblock of a memory device (Writing data to a set of pages of the superblock: Forhan, col.13:23-25); determining, by the processing device, whether to terminate the programming operation (Ending the write operation: Forhan, col.13:44-45); in response to determining to terminate the programming operation, causing, by the processing device, the superblock to be closed to obtain a partially filled superblock comprising a set of closed pages (Disclosing maintaining a free page pointer to the next free page within the partially written superblock: Forhan, col.10:10-15; Partially filling and subsequently writing new data to a block inherently suggests closing the partial subblock to uncontrolled writes between the two operations); causing, by the processing device, a second subset of closed pages of the set of closed pages to be reopened for programming to obtain a set of reopened pages (Allowing data to be written to the next available page in a partially filled superblock: Forhan, col.6:60-63). Forhan does not expressly disclose causing dummy data to be written to a first subset of closed pages of the set of closed pages to obtain a set of dummy pages. Kim, however, expressly teaches causing dummy data to be written to a first subset of closed pages of the set of closed pages to obtain a set of dummy pages (Writing dummy data to logical pages: Kim, col.6:14-17). Kim teaches writing dummy data to pad out unfilled pages converts the partially filled pages into a readable state (Kim, col.6:22-25). Kim discloses performing this padding operation on partially filled pages prior reading, thereby this inherently means performing the padding operation on otherwise closed pages. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the dummy padding operation of Kim, which is necessary to convert the partially filled pages into a readable state, with the partial fill operation of Forhan, with a reasonable expectation of success. Both inventions are well known in the field of managing partially filled data blocks and the combination of known inventions with predictable results is obvious and not patentable. Regarding Independent Claim 15, Forhan discloses a non-transitory computer-readable storage medium comprising instructions (Instructions in a processing device are inherent) that, when executed by a processing device (A memory controller: Forhan, Figure 2), cause the processing device to perform operations comprising: initiating a programming operation (A write operation: Forhan, col.13:21-23) to write data to a set of pages of a superblock of a memory device (Writing data to a set of pages of the superblock: Forhan, col.13:23-25); determining whether to terminate the programming operation (Ending the write operation: Forhan, col.13:44-45); in response to determining to terminate the programming operation, causing the superblock to be closed to obtain a partially filled superblock comprising a set of closed pages (Disclosing maintaining a free page pointer to the next free page within the partially written superblock: Forhan, col.10:10-15; Partially filling and subsequently writing new data to a block inherently suggests closing the partial subblock to uncontrolled writes between the two operations); and causing a second subset of closed pages of the set of closed pages to be reopened for programming to obtain a set of reopened pages (Allowing data to be written to the next available page in a partially filled superblock: Forhan, col.6:60-63). Forhan does not expressly disclose causing dummy data to be written to a first subset of closed pages of the set of closed pages to obtain a set of dummy pages. Kim, however, expressly teaches causing dummy data to be written to a first subset of closed pages of the set of closed pages to obtain a set of dummy pages (Writing dummy data to logical pages: Kim, col.6:14-17). Kim teaches writing dummy data to pad out unfilled pages converts the partially filled pages into a readable state (Kim, col.6:22-25). Kim discloses performing this padding operation on partially filled pages prior reading, thereby this inherently means performing the padding operation on otherwise closed pages. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the dummy padding operation of Kim, which is necessary to convert the partially filled pages into a readable state, with the partial fill operation of Forhan, with a reasonable expectation of success. Both inventions are well known in the field of managing partially filled data blocks and the combination of known inventions with predictable results is obvious and not patentable. Regarding Claim 20, Forhan and Kim disclose the non-transitory computer-readable storage medium of claim 19, wherein the at least one page associated with the at least one wordline of the partially filled superblock comprises a last programmed page associated with a last written wordline prior to termination of the programming operation (Disclosing accessing the stored page may be the page that was programmed last: Kim, col.5:60-63), and wherein the set of reopened pages further comprises an initial page associated with a next wordline following the last written wordline (Pointer to the next available page within the superblock: Forhan, col.10:10-12). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 12,386,524 B2 to Kuan-Chieh Peng, et al.: Disclosing writing dummy data to partially filled superblocks prior to erase operations. US 2015/0117100 A1 to Hyun-Wook Park, et al.: Disclosing writing dummy data to partially filled data page prior to writing to the next page in a superblock. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /PHO M LUU/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Nov 05, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12670962
ANALOG BITSCAN TECHNIQUES IN A MEMORY DEVICE
2y 10m to grant Granted Jun 30, 2026
Patent 12658261
DYNAMIC WORD LINE RAMP UP KICK FOR MEMORY DEVICES
2y 4m to grant Granted Jun 16, 2026
Patent 12658266
PATTERN ANALYSIS ENABLED READ OPERATION IN NAND COMPONENT
2y 2m to grant Granted Jun 16, 2026
Patent 12646571
MEMORY CIRCUIT
2y 2m to grant Granted Jun 02, 2026
Patent 12640178
METHOD FOR OPERATING A DATA PROCESSING SYSTEM
2y 5m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+15.5%)
2y 4m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 31 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month