DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 11/05/2024. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 9,478,271 B2 (Chen et al.) and further in view of US 7,911,836 B2 (Zilberman).
Claim 1: Chen teaches a memory device configured to restore data based on power supply being blocked during programming of a storage device (e.g. Abstract), the memory device comprising:
a first area comprising a first data column (e.g. Pages/R-pages within the R-bloc) that is to be programmed (e.g. Chen teaches programming user data into an R-block, which is a stripe-like structure formed from blocks across multiple dies and written in a "striped fashion." See col. 11, lines 55 – Col. 12, line. 7; FIG. 2). The stream of data being programmed into the sequential pages of this R-block constitutes the "first data column.");
and
a processor configured to:
identify a program state of the first data column programmed in a first stripe of the storage device and determine that the programming of the first data column has stopped (e.g. Chen teaches determining if the last power-down was unsafe (col. 10, lines 1-7) and scanning the memory to find the "first erased lower page" to locate where programming stopped (col. 10, lines 8-15; col. 12, line 58 – col. 13, line 18). This defines the "program state" and stoppage point within an "R-block," which is a stripe-like structure combining blocks from multiple dies. See FIG. 2, col. 11, line 55 – col. 12, line 7).
Not explicitly taught by Chen is:
a second area configured to store restoration data of the first data column. However, Zilberman teaches a data buffer (e.g., a page buffer) that holds the original target data to be programmed (Abstract; Col. 13, l. 1-6). This buffer serves as the "second area" storing "restoration data."
complete programming of the first data column based on the program state of the first data column and generate a second data column by combining the restoration data with a stopped portion of the first data column. However, Zilberman directly teaches completing the programming task by reconstructing the original data. Upon a program failure, Zilberman restores the data buffer by combining its present state with the present state of the memory cells (the "stopped portion") using a logic operation (e.g., AND or OR). (Abstract; Col. 12, l. 1-22; FIG. 8). This generates the correct, intended data set—i.e., the "second data column."
and program the second data column in a second stripe. While Chen teaches resuming programming in the same R-block after a pad zone, it also discusses managing multiple R-blocks (stripes) for different data streams (Col. 12, l. 8-18). It would have been an obvious design choice to a person of ordinary skill in the art (POSITA), for enhanced reliability and wear leveling, to program the reconstructed data from Zilberman’s method into a fresh, new stripe (a "second stripe") rather than the potentially compromised original stripe. This is a predictable optimization within Chen's disclosed multi-stripe architecture.
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to employ Zilberman’s data-buffer restoration technique within Chen’s power-failure recovery framework to achieve a more complete solution; one that not only isolates the failure but also recovers and completes the intended data set.
As per claims 8 and 15, the claimed features are rejected similarly to claim 1 above.
Claim 2: Chen and Zilberman teach the memory device of claim 1, wherein the processor is further configured to: determine a program stop position of the first data column, based on the power supply being resumed (Chen: col. 10, lines 1-15; step 148, col. 12, line 58).
Claim 3: Chen and Zilberman teach the memory device of claim 1, but fail to teach the processor is further configured to: configure first programming information (e.g., metadata, headers, ECC settings) of the first data column to be same as second programming information of the second data column. However, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to ensure data consistency and compatibility within the storage system's management layer.
As pe claims 4 & 6, generating parity data, including via XOR operations, is a conventional technique for data integrity in storage systems. Chen teaches using R-blocks with redundant information for fault tolerance, akin to RAID (col. 15, lines 8-22). Applying such conventional parity generation to a newly programmed data column would have been obvious.
As per claim 5, configuring the second data column by adding restoration data to valid completed data is the exact process taught by Zilberman. The "valid data... that has completed the programming" corresponds to successfully programmed cells, and the "restoration data" corresponds to the buffer state, which are combined to restore the original data set (col. 12, lines 7-22).
As per claim 7, determining stoppage based on pre-configured variable data (e.g., timestamps, sequence numbers) is taught by Chen, which describes using "self-journaling metadata (e.g., a timestamp or sequence number) stored in each written R-block" to identify the last block being programmed (col. 12, lines 41-48).
Claims 9-14 and 16-20: These dependent method claims add steps corresponding to the features of apparatus claims 2, 3, 4, 5, 6, and 7 respectively. For the identical reasons stated in the rejection of claims 2, 3, 4, 5, 6, and 7, these method steps are also rendered obvious by the combined prior art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUERRIER MERANT whose telephone number is (571)270-1066. The examiner can normally be reached Monday-Friday 8:00 Am - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 1/28/2026