Prosecution Insights
Last updated: October 01, 2026
Application No. 18/937,697

CIRCUIT BOARD AND METHOD FOR MANUFACTURING MOUNTING BOARD

Non-Final OA §102§103
Filed
Nov 05, 2024
Priority
May 18, 2022 — JP 2022-081600 +1 more
Examiner
DINH, TUAN T
Art Unit
Tech Center
Assignee
TDK Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
944 granted / 1198 resolved
+18.8% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
29 currently pending
Career history
1229
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.0%
+5.0% vs TC avg
§102
38.5%
-1.5% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1198 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6, and 9 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Alcoe et al. (U.S. 2002/0135063) cited by the applicant. As to claim 1, Alcoe discloses a circuit board (10) as shown in figure 3 comprising: a substrate (the body of the circuit board 10); at least a pair of terminals (47, para-0056) provided on the substrate (10); a bonding material (43, para-0065) disposed on the terminals (47) and containing a metal element (solder material); and a wall (20, para-0049) of an insulating material (glass, silicon, polymer, or ceramic, para-0049)disposed on the substrate (10), wherein the pair of terminals (47) and the bonding material (43) are disposed inside the wall (20), and at least one wall-frame portion of the wall (20, figure 3) has at least one groove portion (not label, the gaps formed between the elements 20, figures 3 and 5, hereafter called G) passing through an outer peripheral surface from an inner peripheral surface. As to claim 6, Alcoe discloses in figure 3 that a recess (the gap formed between the corner of the wall and the side of the chip 30) recessed toward an outer peripheral side from an inner peripheral surface of the wall-frame portion (20) is located at a corner portion where a pair of the wall-frame portions are connected to each other as viewed in the height direction. As to claim 9, Alcoe discloses a method for manufacturing a mounting board (10), the method comprising mounting an electronic component (30) on the circuit board according to claim 1 to manufacture a mounting board, wherein a filling material (60) is disposed on the substrate (10), the electronic component (30) is disposed, and then the electronic component (30) is bonded to the terminal (47) by using a pressurization reflow device, para-0015+. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alcoe (‘063). Regarding claim 3, Alcoe discloses when an occupied area of the wall-frame portion (20) as viewed in the thickness direction of the wall-frame portion is designated as S, an opening area of the groove portion is designated as Sc, a width of the wall-frame portion in a width direction orthogonal to the thickness direction and the height direction is designated as W, and a length of the wall-frame portion in the thickness direction is designated as L, except for the following Formulas (1) and (2) are established: [Math. 1] 0.015 < Sc/S< 0.75 - (1) 0.1 <= ∑ W n L n < 12.6 It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the formulas (1) and (2) as taught by Alcoe as above in order to achieve the amount of filling material flow into the groove portion of the frame-wall mounted on the circuit board, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 8, Alcoe discloses all the limitations of the claimed invention except for a dimension of a short side of an inner peripheral surface inside the wall is 8 µm or more, and a dimension of a long side of the inner peripheral surface is 68 µm or less. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitations of claim 8 in order to provide accurate size of the wall on the inner peripheral side for mounting on the circuit board, since it has been held that discovering an optimum value of a result effective variable involves only routine Skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Claim(s) 2, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alcoe in view of Shen (U.S. 2014/0167243). Regarding claim 2, Alcoe discloses the groove portion (30) extends from a distal end portion of the wall-frame portion (20) in a height direction orthogonal to a main surface of the substrate (10) toward the substrate side as viewed in a thickness direction of the wall-frame portion (20), except for a bottom surface of the groove portion is disposed at a position separated from the substrate. Shen teaches semiconductor packages using a chip constraint means as shown in figure 6B comprising a bottom surface of the groove portion (the groove portion where the chip 340 mounted on) is disposed at a position separated from the substrate. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Shen employed in the circuit board of Alcoe in order to provide support structure for the chip mounting. Regarding claim 7, Alcoe discloses all the limitations of claimed invention except for an edge portion of the groove portion is rounded. Shen teaches semiconductor packages using a chip constraint means as shown in figure 7B comprising edge portion of the groove portion is rounded (at the element 275). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Shen employed in the circuit board of Alcoe in order to easy of the smoothly filling material flowing through the groove portion. Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alcoe in view of Chen (U.S. Patent 11,521,939). Regarding claim 4, Alcoe discloses the groove portion (G) extends from the distal end portion of the wall-frame portion (20) in the height direction toward the substrate side as viewed in the thickness direction of the wall-frame portion (20), except for the width of the groove portion in the width direction orthogonal to the thickness direction and the height direction is larger on the distal end portion side than on the bottom surface side. Chen teaches a semiconductor device structure (1a) as shown in figures 3-5 comprising the width of the groove portion (at the element 20s1) in the width direction orthogonal to the thickness direction and the height direction is larger on the distal end portion side than on the bottom surface side (20u1). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Chen employed in the circuit board of Alcoe in order to provide more space for inserting chip or component mounted on the circuit board. Regarding claim 5, Alcoe discloses all the limitations of claimed invention except for the width of the groove portion in the width direction orthogonal to the thickness direction and the height direction is larger on an inner peripheral side than on an outer peripheral side as viewed in the height direction. Chen teaches a semiconductor device structure (1a) as shown in figures 3-5 comprising the width of the groove portion (at the element 20s1) in the width direction orthogonal to the thickness direction and the height direction is larger on an inner peripheral side than on an outer peripheral side as viewed in the height direction. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Chen employed in the circuit board of Alcoe in order to provide more space for inserting chip or component mounted on the circuit board. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Nov 05, 2024
Application Filed
Sep 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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EMBEDDED PACKAGE STRUCTURE, POWER SUPPLY APPARATUS, AND ELECTRONIC DEVICE
3y 0m to grant Granted Sep 29, 2026
Patent 12740147
ELECTRONIC DEVICE
2y 8m to grant Granted Sep 15, 2026
Patent 12733099
ELECTRONICS PACKAGING FOR MOVING PLATFORMS
4y 5m to grant Granted Sep 08, 2026
Patent 12733100
REDUCING PRINTED CIRCUIT BOARD AREA FOR SINGLE-SIDED PRINTED CIRCUIT BOARD
3y 9m to grant Granted Sep 08, 2026
Patent 12727086
FLEXIBLE CIRCUIT BOARD AND METHOD OF MANUFACTURING THEREOF
2y 3m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.1%)
2y 11m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1198 resolved cases by this examiner. Grant probability derived from career allowance rate.

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