Prosecution Insights
Last updated: October 02, 2026
Application No. 18/937,936

ELECTRONIC DEVICE INCLUDING SUBSTRATE INCLUDING COATING LAYER

Non-Final OA §102§103
Filed
Nov 05, 2024
Priority
May 17, 2022 — RE 10-2022-0060506 +2 more
Examiner
DINH, TUAN T
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
944 granted / 1198 resolved
+18.8% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
29 currently pending
Career history
1229
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.0%
+5.0% vs TC avg
§102
38.5%
-1.5% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1198 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Tittle The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: AN ELECTRONIC DEVICE INCLUDING A SUBSTRATE AND METHOD OF MANUFACTURING OF A SUBSTRATE. Abstract The abstract of the disclosure is objected to because: The Abstract does not contain “a method of manufacturing a substrate”. Please, revise. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 16-19 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Zhang et al. (U.S. 2017/0265298). As to claim 16, Zhang discloses a method of manufacturing of a substrate as shown in figures 1-11 including: disposing a first conductive layer (24) on a dielectric film (22); disposing a non-conductive layer (42) on the first conductive layer; coating a first coating layer (40) on the non-conductive layer (42); disposing a rigid portion (the left portion or right portion apart between the hole/opening or recess 50, hereafter RP) including a second conductive layer (8, 9) on a portion of the first coating layer (2); forming a via hole (60) in the rigid portion (RP) and removing a smear of the via hole (60); coating a second coating layer (32) on the second conductive layer (9); and removing a portion of the first coating layer (40) disposed in a flexible portion (the thinner portion formed between the left and right portion, hereafter FP) different from the rigid portion, in the first coating layer (40). As to claim 17, Zhang further comprising forming an opening (50) by removing a portion of the second coating layer (32), para-0016+. As to claim 18, Zhang further comprising disposing a third conductive layer (36), between the second coating layer (32) and the second conductive layer (9), and extending to the via hole. As to claim 19, Zhang discloses a material (prepreg material) of the first coating layer (2) is the same material (the prepreg material) as a material of the second coating layer (32), para-0014+. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 7-10, and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. Patent 10,838,458) in view of Zhang et al. (U.S. 2017/0265298). As to claim 1, Park discloses an electronic device (100)3 comprising: a first housing (110); a second housing (120); a hinge structure (164) comprising a hinge rotatably connecting the first housing (110) and the second housing (120); and a substrate (163, 171, and 172), extending from an inside of the first housing (110) across the hinge structure (164) to an inside of the second housing (120), the substrate including: a flexible portion (163), a rigid portion (171, 172). Park does not specifically disclose a stepped portion disposed at a boundary between the flexible portion and the rigid portion, wherein the substrate includes: a first conductive layer disposed in the flexible portion and the rigid portion, a first coating layer disposed on a portion of the first conductive layer corresponding to the rigid portion, a second conductive layer disposed on the first coating layer in the rigid portion, and a second coating layer (32) disposed on the second conductive layer (9), and wherein a portion of a boundary of the first coating layer is aligned with the stepped portion. Zhang teaches a PCB as shown in figures 1-11 comprising a stepped portion (formed in the recess or opening 50) disposed at a boundary between the flexible portion (FP, see claim 16) and the rigid portion (RP), wherein the substrate includes: a first conductive layer (24) disposed in the flexible portion and the rigid portion, a first coating layer (40) disposed on a portion of the first conductive layer (24) corresponding to the rigid portion, a second conductive layer (9) disposed on the first coating layer (40) in the rigid portion, and a second coating layer (32) disposed on the second conductive layer (9), and wherein a portion of a boundary of the first coating layer is aligned with the stepped portion. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Zhang employed in the method of Park in order to provide excellent protection and insulating polymer characteristic. Regarding claim 2, Park as modified by Zhang discloses the rigid portion includes: a first rigid portion (171) disposed closer to the first housing of the first housing and the second housing, and a second rigid portion (172) disposed closer to the second housing of the first housing and the second housing. Regarding claim 3, Park as modified by Zhang discloses the flexible portion (163) is disposed between the first rigid portion (171) and the second rigid portion (172). Regarding claim 4, Park as modified by Zhang teaches in figure 1 the first coating layer (40) includes: a first portion disposed on a first region (the left region) of the first conductive layer corresponding to the first rigid portion in the first conductive layer, and a second portion disposed on a second region (the right region) of the first conductive layer (40) corresponding to the second rigid portion in the first conductive layer, and wherein the first portion of the first coating layer and the second portion of the first coating layer are spaced apart each other. Regarding claim 5, Park as modified by Zhang teaches the substrate includes a non-conductive layer (42) dispose between the first coating layer (40) and the first conductive layer (24), and wherein a thickness of the non-conductive layer disposed in the flexible portion corresponds to a thickness of the non-conductive layer disposed in the rigid portion. Regarding claim 7, Park as modified by Zhang teaches the rigid portion of the substrate includes a conducive via (60) electrically connecting the first conductive layer (24) and the second conductive layer (9), and wherein the substrate includes a third conductive layer (36), disposed between the second coating layer (32) and the second conductive layer, connected to the conductive via (60). Regarding claim 8, Park as modified by Zhang teaches the second coating layer (32) includes an opening exposing the third conductive layer (36). Regarding claim 9, Park as modified by Zhang discloses the substrate is connected to a first printed circuit board (PCB-171) in the first housing and a second PCB (172) in the second housing, through the opening. Regarding claim 10, Park as modified by Zhang teaches a material of the first coating layer (40) is the same material as a material of the second coating layer (32). Regarding claim 14, Park as modified by Zhang further comprising a display (130), wherein the first housing (110) includes: a first surface facing the display, and a second surface opposite to the first surface, wherein the second housing (120) includes: a third surface facing the display (130), and a fourth surface opposite to the third surface, and wherein the hinge structure (164) is configured to provide an unfolded state of the electronic device in which a direction of the first surface of the first housing corresponds to a direction of the third surface of the second housing, or a folded state of the electronic device in which the first surface of the first housing faces the third surface of the second housing, by rotatably connecting the first housing and the second housing. Regarding claim 15, Park as modified by Zhang discloses a shape of at least a portion of the flexible portion (163) of the substrate is configured to be deformed based on a state change of the electronic device. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (‘298) in view of Chung et al. (U.S. 2013/0056250). As to claim 20, Zhang discloses a material of the first coating layer (2) and a material of the second coating layer (32) except for each comprise a photo solder resist (PSR) ink. Chung teaches a method for manufacturing a double-sided printed circuit board as shown in figures 2-4 comprising a coverlay layer made from PSR ink, para-0070+. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Chung employed in the method of Zhang in order to provide excellent protection and insulating polymer characteristic (harden when exposed to light) on the PCB. Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Zhang (‘298), and further in view of Chung et al. (U.S. 2013/0056250). As to claim 11, Park as modified by Zhang discloses a material of the first coating layer (2) and a material of the second coating layer (32) except for each comprise a photo solder resist (PSR) ink. Chung teaches a method for manufacturing a double-sided printed circuit board as shown in figures 2-4 comprising a coverlay layer made from PSR ink, para-0070+. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Chung employed in the method of Park and Zhang in order to provide excellent protection and insulating polymer characteristic (harden when exposed to light) on the PCB. Regarding claim 12, Park as modified by Zhang and Chung discloses a first PCB (171) disposed in the first housing (110); and a second PCB (172) disposed in the second housing (120), wherein the substrate is connected to the first PCB and the second PCB. Regarding claim 13, Park as modified by Zhang and Chung discloses at least a portion of the substrate is disposed in the hinge structure (164). Allowable Subject Matter Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Nov 05, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12750955
EMBEDDED PACKAGE STRUCTURE, POWER SUPPLY APPARATUS, AND ELECTRONIC DEVICE
3y 0m to grant Granted Sep 29, 2026
Patent 12740147
ELECTRONIC DEVICE
2y 8m to grant Granted Sep 15, 2026
Patent 12733099
ELECTRONICS PACKAGING FOR MOVING PLATFORMS
4y 5m to grant Granted Sep 08, 2026
Patent 12733100
REDUCING PRINTED CIRCUIT BOARD AREA FOR SINGLE-SIDED PRINTED CIRCUIT BOARD
3y 9m to grant Granted Sep 08, 2026
Patent 12727086
FLEXIBLE CIRCUIT BOARD AND METHOD OF MANUFACTURING THEREOF
2y 3m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.1%)
2y 11m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1198 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month