DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7 and 9-10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ku (US 2012/0218849 A1), and further in view of Cho (US 2023/0377672 A1).
For claim 8,
Ku teaches a memory system comprising: a memory media including a plurality of memory chips, each of the plurality of memory chips including a plurality of memory units and each of the plurality of memory units including a plurality of memory cells (see figures 2, 6, paragraphs [0045-0047], and other locations: view apparatus 200 as said system; view combination of memory cell array 210 and control circuit 220 as said memory media; a memory cell is the basic memory component); and a controller configured to detect a fail memory unit from among the plurality of memory units included in the memory media (see figure 6 and other locations: view mode setting circuit 110 as said controller), and transmit to the memory media a fail flag set command for setting a fail flag for the fail memory unit (see figure 6, [0018], and other locations: view MPD0_F or MPD1_F as said flags), wherein the memory media receives the fail flag set command, and sets the fail flag in at least one of the plurality of memory cells included in the fail memory unit (see [0033] and other locations: view disabling power to specific failed memory as said), []
Ku does not explicitly teach “the memory media receives the fail flag set command, and sets the fail flag in at least one of the plurality of memory cells in the fail memory unit”
However, Cho teaches the memory media receives the fail flag set command, and sets the fail flag in at least one of the plurality of memory cells in the fail memory unit (see [0109] and other locations)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ku to include “the memory media in the fail memory unit”, as taught by Cho, because each one of Ku and Cho teach media cards of memory chips therefore they are analogous arts and because memory chips usually contain registers which are also memory cells (see [0109] and other locations).
For claim 2,
The combination of Ku and Cho teaches the limitations of claim 1.
Ku further teaches the controller determines the fail memory unit, from among the plurality of memory units included in the memory media, as a memory unit in which a number of failed memory cells is equal to or greater than a threshold (see abstract and other locations: view at least one failure/any failure as said threshold).
For claim 4,
The combination of Ku and Cho teaches the limitations of claim 1.
Ku further teaches the controller reads an N number of data units from an N number of memory units among the plurality of memory units included in the memory media, one of the N number of memory units is the fail memory unit, and N is a natural number of 2 or greater (see figure 2 and other locations: view k as said N; view dashed line: word size read depends on k; fail can occur on any chip and rank number).
For claim 5,
The combination of Ku and Cho teaches the limitations of claim 4.
Ku further teaches the memory media transmits, in response to a read request for the fail memory unit, a preset pattern data to the controller (see [0033] and other locations: view DQ signal as said pattern, as it describes the failed location).
For claim 6,
The combination of Ku and Cho teaches the limitations of claim 1.
Ku further teaches all bits of the preset pattern data are 0 (see figure 4: DQ described which unit is faulty; by example, one of the combination of bits that describes a specific location is all zeros).
For claim 7,
The combination of Ku and Cho teaches the limitations of claim 5.
Ku further teaches the controller restores data of the fail memory unit including the preset pattern data using remaining data units, except the fail memory unit, among the N number of data units (see [0007-0013] : view using redundancy as said recovery/restorations).
For claim 9, the claim recites essentially similar limitations from the combination of claims 1 and 3. Claim 9 is a method.
For claims 10 and 12-15, Ku teaches the limitations of claim 9 for the reasons above. The claims recite essentially similar limitations as claims 2 and 4-7 respectively.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ku (US 2012/0218849 A1), in view of Cho (US 2023/0377672 A1), and further in view of Kriic (US 2018/0166116 A1).
For claim 8,
The combination of Ku and Cho teaches the limitations of claim 7.
The combination of Ku and Cho does not explicitly teach the controller restores the data of the fail memory unit using an erasure coding algorithm
However, Kriic teaches the controller restores the data of the fail memory unit using an erasure coding algorithm (see title and [0011] and other locations)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ku to include “the controller restores the data of the fail memory unit using an erasure coding algorithm”, as taught by Kriic, because each one of Ku and Kriic teach media cards of memory chips therefore they are analogous arts and because erasure codes are commonly used in DIMMs (see title and [0011] and other locations).
For claim 16,
the claim recites essentially similar limitations as claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIR LEIBOVICH whose telephone number is (571)270-3796. The examiner can normally be reached 8:00am-5:00pm.
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/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114
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