DETAILED ACTION
1. This Office Action is responsive to amendments filed for No. 18/938,567 on December 8, 2025. Please note Claims 1-7 are pending and have been examined.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 7, 2025 has been entered.
Drawings
4. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first and second pixels must be shown or the feature(s) canceled from the claim(s). Furthermore, while the second pixel precedes the first pixel, no timing diagram exists which shows the relationship of initialization/data voltages between the two pixels. While Figure 3 provides a general overview of the various periods, no description of these signals applied to the first and second pixels are detailed. Furthermore, and to further clarify, the amendments further focus on actions in response to scan signals applied on various scan lines. However, while this could be understood as for one pixel, relating to anther pixel, on another row, is not found in these drawings and requires too far of a stretch to satisfy the drawing requirements. To expand further on the arguments presented in the 12/8/25 response, relying on Figures 2 and 5A is insufficient here because even if the pixel has connections to these scan lines, etc, there is insufficient detail to the specific transistors using those specific scan lines. Figure 2 shows only one pixel, but the claim details two pixels and connections of at least one of the pixels which is not shown in any drawing. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
5. Claims 1-7 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites aspects of a first and second pixel. However, the actual pixels and how they interact with each other are not detailed. Figures 5A/5B show a rather generic layout of a pixel matrix and does not detail how these two pixels are connected/related. This is especially important given the driving method/timing of Claim 1 because the claim requires scan signals to be applied to at least two pixels in response to a variety of scan signals. While it could be within ordinary skill examining this disclosure to realize aspects of a one pixel, for two pixels, it seems difficult. While Figure 2 shows the layout of one pixel, no figure shows the second pixel, which is important here because the claim requires connections of scan lines to different elements within two pixels and this level of detail is not described. Applicant points to [0158] of the disclosure for support, but this simply notes the pixel has connections to scan lines, but it’s not specific enough.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. ( US 2019/0189053 A1 ).
Kim teaches in Claim 1:
A method of driving a display device including a first pixel (Pxi) disposed on an i-th horizontal line and a second pixel (PXi-1) disposed on a horizontal line immediately preceding the i-th horizontal line, wherein the first pixel and the second pixel are each connected to the (i-1)-th first scan line ( Figures 2 and 3, [0077] disclose a method of driving a pixel PXL. As for the first and second pixel, please note Figure 1 shows each pixel PXL is connected to S1i and S2i, as well as S1i-1 (to clarify, each pixel shares common scan lines, such as the first scan line). As such, the pixel shown in Figure 2 is interpreted as the first pixel and the pixel corresponding to S1i-1 is for a preceding row (read as a horizontal line) ), the method comprising:
diode-connecting a first transistor of the first pixel in response to a second scan signal supplied to an i-th second scan line ( Figure 2, [0069] discloses the first transistor T1 may be connected in the form of a diode when the third transistor T3 is turned on, in response to S2i. Please note the similarities to Applicant’s Figure 2 in this sense as well );
diode-connecting a first transistor of the second pixel in response to a second scan signal supplied to an (i-1)-th second scan line ( Respectfully, the same pixel PXL repeats for all of the pixel PXL. As such, Figure 2 shows the layout for the interpreted second pixel as well, turning on in response to S2i as well );
supplying an initialization voltage to the diode-connected first transistor of the second pixel in response to a first scan signal supplied to an (i-2)-th first scan line ( Figure 2, [0070] discloses the fourth transistor T4 is coupled between the second electrode of first transistor T1 and the initialization power source Vint. Please note this is under the control of S1i-1, i.e. the previous scan line corresponding to the interpreted second pixel. Please note the similarities of this to Applicant’s Figure 2 with regards to M7 being controlled by S1i-1 and providing Vint as well. To point out, Applicant’s Figure 2 teaches of writing an initialization voltage with Sli-1 and Kim teaches likewise );
writing a data voltage to the diode-connected first transistor of the second pixel in response to the first scan signal supplied to the (i-1)-th first scan line and supplying the initialization voltage to the diode-connected first transistor of the first pixel in response to the first scan signal supplied to the (i-1)-th first scan line ( Figure 2, [0071] discloses the second transistor T2 receives a data voltage from Dj and provides this to first transistor T1 and this is under the control of S1i. To clarify, this would correspond to S1i-1 for the initialization power voltage Vint for the interpreted second pixel as well as for controlling the second transistor T2. Please note the similarities to Applicant’s Figure 2 with regards to M2 being controlled by S1i. To point out, Applicant’s Figure 2 teaches of writing a data voltage with Sli and Kim teaches likewise and notably, since this is the preceding pixel, it would be with the (i-1)-th scan line, as one of ordinary skill in the art would realize ); and
writing a data voltage to the diode-connected first transistor of the first pixel in response to an i-th first scan signal supplied to an i-th first scan line ( Figure 2, [0071] discloses the second transistor T2 receiving the data voltage from Dj and this is under the control of S1i. To point out, Applicant’s Figure 2 teaches of writing a data voltage with Sli and Kim teaches likewise ) and
wherein a first period during which writing a data voltage to the diode-connected first transistor of the second pixel in response to the first scan signal supplied to the (i-1)-th first scan line and a second period during which supplying the initialization voltage to the diode-connected first transistor of the first pixel in response to the first scan signal supplied to the (i-1)-th first scan line are overlapped. ( [0080] discloses the initialization of T4 and at this same time, the first scan line is supplied to T2 (and then T1, the interpreted diode-connected first transistor, i.e.. Please note these are at the same time, i.e. the scan signal is applied when node N1 is initialized, and are overlapping in time )
Kim teaches in Claim 2:
The method of claim 1, wherein the supplying the initialization voltage to the diode-connected first transistor of the second pixel comprises:
supplying a second scan signal to a third transistor of the second pixel ( Figure 2 and keeping in mind the interpretation of the preceding and repeating second pixel: The third transistor T3 is connected to S2i. Please note the similarities to Applicant’s Figure 2 with regards to M3 being controlled by S2i ), and
wherein the third transistor of the second pixel is connected between a drain electrode and a gate electrode of the first transistor of the second pixel. ( Figure 2 shows the third transistor T3 is connected between a drain and gate electrode of the first transistor T1 )
Kim teaches in Claim 3:
The method of claim 2, wherein, in the supplying the second scan signal to the third transistor of the second pixel, the second scan signal is a logic high level. ( Figures 2 and 3, [0079] disclose an example of S2i controlling to turn the third transistor T3 on. Please note the high level for G1i-1 )
Kim teaches in Claim 4:
The method of claim 1, wherein the first pixel further comprises a seventh transistor connected between an initialization power source to which the initialization voltage is supplied and the first transistor ( Figure 2, [0070] discloses the fourth transistor T4 (read as the seventh transistor) which is connected between Vint and the first transistor T1. Please note the similarities to Applicant’s Figure 2 with regards to M7 )
the second pixel further comprises a second transistor connected between a data line to which the data voltage is supplied and the first transistor ( Figure 2, [0071] discloses the second transistor T2 connected between data line Dj which is applied to the first transistor T1 ), and
in the writing the data voltage to the diode-connected first transistor of the second pixel and supplying the initialization voltage to the diode-connected first transistor of the first pixel, a same scan signal is supplied to the seventh transistor of the first pixel and the second transistor of the second pixel. ( Figure 2 shows the data voltage is applied through the second transistor T2 (and on to the first transistor T1) and the initialization voltage is applied to the first transistor T1 through the fourth transistor T4 (and through T3 as well, making T1 diode-connected). As detailed above, this is under control of S1i and S1i-1, which correspond to the same scan signal when comparing the first pixel and second pixel )
Kim teaches in Claim 5:
The method of claim 4, wherein the scan signal is a logic low level. ( Figure 3, [0074] disclose that for the initialization voltage, etc, it is when the scan line are at a low level, as shown )
Kim teaches in Claim 7:
The method of claim 1, wherein the diode-connecting the first transistor of the first pixel overlaps the diode-connecting the first transistor of the second pixel. ( Figure 3, [0081]-[0082] disclose the overlap of the scan signals for when the first transistor T1 is diode-connected, i.e. during the initialization voltage application phase using transistors T4 and T3. Please note T1, T3, T4 are turned on at the same time as well )
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claim 6 rejected under 35 U.S.C. 103 as being unpatentable over Kim et al.
( US 2019/0189053 A1 ), as applied to Claim 1, further in view of Park et al.
( US 2019/0221165 A1 ).
As per Claim 6:
Kim does not explicitly teach of “turning on a fourth transistor of the first pixel connected between the first transistor of the first pixel and a bias power source, wherein the diode-connecting the first transistor of the first pixel is performed after the turning on of the fourth transistor of the first pixel.”
However, in the same field of endeavor, pixel circuits with initialization aspects, Park teaches of an eighth transistor T8, ( Park, Figure 3, [0089] ). Notably, T8 is referred to as an “on-bias transistor” and is connected between transistor T1 and VN1/VDD. This on-bias transistor is configured to apply a first driving voltage to the first node in response to reception of an on-bias control signal in the first period. Figure 6 discloses T8 is turned on by GSi-1 and this is before GSi, which is where akin T3/T1 are turned on, [0083]. As combined with Kim, an on-bias transistor can be incorporated.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the on-bias transistor, as taught by Park, with the motivation that this would enhance the functionality of the drive transistor, avoiding a deterioration in display quality, ( Park, [0028] ).
Response to Arguments
11. Applicant’s arguments considered, but are respectfully not persuasive.
Please note the updated rejection in light of the claim amendments.
As for the drawing objection and 112 rejection, while Examiner appreciates Applicant’s arguments, Figures 2 and 5A are insufficient as these figures lack the specific connections of lines to transistors. To clarify, even assuming the first and second pixels have the same layout, it is unclear or unreasonable to assume the claimed level of detail being supported by this. For example, Figure 5A could show two pixels with connections to scan lines, but the claim requires specific scan line connections to elements. However, Figure 2 only shows one such pixel and the second pixel is missing, along with its specific connections.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621