DETAILED ACTION
1. This Office Action is responsive to amendments filed for No. 18/938,567 on June 18, 2026. Please note Claims 1-6 are pending and have been examined.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claim 1-5 rejected under 35 U.S.C. 103 as being unpatentable over Kim et al.
( US 2019/0189053 A1 ) in view of Kim ( US 2020/0135091 A1 ), hereinafter referred to as Kim2.
Kim teaches in Claim 1:
A method of driving a display device including a first pixel disposed on an i-th horizontal line ( Figures 2 and 3, [0077] disclose a method of driving a pixel PXL. As for the first pixel, note Figure 1 shows each pixel PXL is connected to S1i and S2i, as well as S1i-1 (to clarify, each pixel shares common scan lines, such as the first scan line). As such, the pixel shown in Figure 2 is interpreted as the first pixel and a corresponding line S1i-1 is for a preceding row (read as a horizontal line) ), the method comprising:
diode-connecting a first transistor of the first pixel in response to a second scan signal supplied to an i-th second scan line during a first period, wherein the first period includes an initialization period and a compensation period ( Figure 2, [0069] discloses the first transistor T1 may be connected in the form of a diode when the third transistor T3 is turned on, in response to S2i (read as a second scan signal) and this is for a compensation process, [0082]. Please note the similarities to Applicant’s Figure 2 in this sense as well. As for a first period, please note Figure 3 which shows multiple gate/scan signals applied. To clarify, Figure 2, [0070] discloses the fourth transistor T4 is coupled between the second electrode of first transistor T1 and the initialization power source Vint. Please note the similarities of this to Applicant’s Figure 2 with regards to M7 being controlled by S1i-1 and providing Vint as well. To point out, Applicant’s Figure 2 teaches of writing an initialization voltage with Sli-1 and Kim teaches likewise. Figure 3 shows the interpreted initialization and compensation signals during the interpreted first period );
supplying the initialization voltage to the diode-connected first transistor of the first pixel in response to the first scan signal supplied to the (i-1)-th first scan line during the initialization period ( As disclosed above, Figures 2 and 3 teaches of S1i-1 applying Vint to T4 during the initialization period ); and
writing a data voltage to the diode-connected first transistor of the first pixel in response to an i-th first scan signal supplied to an i-th first scan line during a writing period ( Figure 2, [0071] discloses the second transistor T2 receiving the data voltage from Dj and this is under the control of S1i. To point out, Applicant’s Figure 2 teaches of writing a data voltage with Sli and Kim teaches likewise ) and
wherein the writing period and the compensation period are overlapped ( Figure 3 shows G2i (compensation period) overlapping G1i-1 and G1i (data writing period ); but
Kim does not explicitly teach “wherein the compensation period ends later than the writing period”.
However, in the same field of endeavor, compensation for driving transistors, Kim2 teaches of a pixel circuit with a driving transistor, Tdr, ( Kim2, Figure 2, [0088] ). Notably, Kim2 teaches in Figure 4 of a similar driving method in which periods P1-P4 can define driving states of the pixel, as shown in Figures 5A-5C, [0088]. Period P1 is defined as an initialization and programming period (or data writing) in which the data voltage Vdata can be written to Tdr, as detailed in [0094]. Afterwards, during P2, [0096] discloses threshold voltage is compensated for and this occurs/ends later than the data writing period P1, as shown in Figure 4. Respectfully, please note the combination in which Kim teaches of overlapping and Kim2 teaches to further extend the compensation to end after the data writing aspects.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the compensation timing process, as taught by Kim2, with the motivation that with this specific driving, the characteristics of the driving transistor Tdr can be significantly improved, ( Kim2, [0100] ).
Kim teaches in Claim 2:
The method of claim 1, wherein the supplying the initialization voltage to the diode-connected first transistor of the first pixel comprises:
supplying a second scan signal to a third transistor of the first pixel ( Transistor T3 is connected to S2i. Please note the similarities to Applicant’s Figure 2 with regards to M3 being controlled by S2i ), and
wherein the third transistor of the first pixel is connected between a drain electrode and a gate electrode of the first transistor of the first pixel. ( Figure 2 shows the third transistor T3 is connected between a drain and gate electrode of the first transistor T1 )
Kim teaches in Claim 3:
The method of claim 2, wherein, in the supplying the second scan signal to the third transistor of the first pixel, the second scan signal is a logic high level. ( Figures 2 and 3, [0079] disclose an example of S2i controlling to turn the third transistor T3 on. Please note the high level for G1i-1 )
Kim teaches in Claim 4:
The method of claim 1, wherein the first pixel further includes:
a seventh transistor connected between an initialization power source to which the initialization voltage is supplied and the first transistor ( Figure 2, [0070] discloses the fourth transistor T4 (read as the seventh transistor) which is connected between Vint and the first transistor T1. Please note the similarities to Applicant’s Figure 2 with regards to M7 ) and
a second transistor connected between a data line to which the data voltage is supplied and the first transistor ( Figure 2, [0071] discloses the second transistor T2 connected between data line Dj which is applied to the first transistor T1 ),
Kim2 teaches in Claim 5:
The method of claim 4, wherein each of the second transistor and the seventh transistor is a P-type transistor. ( Figure 2, [0079] discloses P-type semiconductor material for the akin T2 and T4. Furthermore, P-type transistors are well known in the art and Examiner asserts Official Notice to this )
6. Claim 6 rejected under 35 U.S.C. 103 as being unpatentable over Kim et al.
( US 2019/0189053 A1 ) and view of Kim2 ( US 2020/0135091 A1 ), as applied to Claim 1, further in view of Park et al. ( US 2019/0221165 A1 ).
As per Claim 6:
Kim does not explicitly teach of “turning on a fourth transistor of the first pixel connected between the first transistor of the first pixel and a bias power source, wherein the diode-connecting the first transistor of the first pixel is performed after the turning off of the fourth transistor of the first pixel.”
However, in the same field of endeavor, pixel circuits with initialization aspects, Park teaches of an eighth transistor T8, ( Park, Figure 3, [0089] ). Notably, T8 is referred to as an “on-bias transistor” and is connected between transistor T1 and VN1/VDD. This on-bias transistor is configured to apply a first driving voltage to the first node in response to reception of an on-bias control signal in the first period. Figure 6 discloses T8 is turned on by GSi-1 and this is before GSi, which is where akin T3/T1 are turned on, [0083]. As combined with Kim, an on-bias transistor can be incorporated.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the on-bias transistor, as taught by Park, with the motivation that this would enhance the functionality of the drive transistor, avoiding a deterioration in display quality, ( Park, [0028] ).
Response to Arguments
7. Applicant’s arguments considered, but are respectfully moot in view of new grounds of rejection(s).
Please note the updated rejection in light of the claim amendments, notably a reliance on Kim2. As a result, Applicant’s arguments are moot at this time.
Conclusion
8. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621
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