Notice of Pre-AIA or AIA Status
The present application, filed on or after March DETAILED ACTION
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Pub # 2021/0191656).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Hong teaches a memory system, comprising: a memory controller including a seed generator configured to generate a seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where 200/201 memory controller, unit 211/231 generate seed value) and a first pseudo-random binary sequence (PRBS) generator configured to generate a first PRBS based on the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where unit 213 generate first PRBS); and a memory device including a second PRBS generator configured to receive the seed value from the memory controller and generate a second PRBS based on the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where unit 100/101 memory device, unit 233 generate second PRBS),
an evaluator system including at least one of a first evaluator configured to evaluate the first PRBS and the second PRBS, the first evaluator being included in the memory controller, or a second evaluator configured to evaluate the first PRBS and the second PRBS, the second evaluator being included in the memory device (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where unit 130 evaluate PRBS), and
the memory controller further configured to perform a read test using the first evaluator, based on the memory controller including the first evaluator, or the memory device further configured to perform a write test using the second evaluator, based on the memory controller including the second evaluator (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where read / writes execute through unit 130 based on controller, each PB1…PBm include sensing circuitry to evaluate data).
Even though Hong teaches page buffer unit 130 which includes multiple page buffer PB1….PBm but silent exclusively about evaluator system. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Hong where each page buffer includes sensing circuitry to valuate incoming data which would be called evaluator in order to improve reliability of data and to improve operating speed of memory system (see paragraph 0164).
Regarding dependent claim 2, Hong further teaches the memory system according to claim 1, wherein a type of linear feedback shift register (LFSR) of the first PRBS generator and a type of LFSR of the second PRBS generator are a same as each other, and the first PRBS generator and the second PRBS generator are configured to generate the same PRBS based on the same seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0142).
Regarding dependent claim 3, Hong further teaches the memory system according to claim 1, wherein the memory device further includes a mode register configured to store at least one of LFSR type information or maximum length information supported by the second PRBS generator, and the memory device is configured to transmit at least one of the LFSR type information or the maximum length information supported by the second PRBS generator to the memory controller in response to a request from the memory controller (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0130).
Regarding dependent claim 4, Hong further teaches the memory system according to claim 3, wherein the memory controller is configured to generate at least one of specific LFSR type information or specific length information based on at least one of the LFSR type information or the maximum length information supported by the second PRBS generator, and the memory controller is configured to transmit at least one of the generated specific LFSR type information or specific length information to the memory device (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0134).
Regarding dependent claim 5, Hong further teaches the memory system according to claim 4, wherein the seed generator is configured to generate the seed value based on the specific length information, the first PRBS generator is configured to generates the first PRBS based on the specific LFSR type information and the seed value, and the second PRBS generator is configured to generates the second PRBS based on the specific LFSR type information and the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135).
Regarding dependent claim 6, Hong further teaches the memory system according to claim 4, wherein the first PRBS generator is configured to generate the first PRBS based on the specific LFSR type information and the seed value, and the second PRBS generator is configured to generate the second PRBS based on the specific LFSR type information, the specific length information, and the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0150).
Regarding dependent claim 7, Hong further teaches the memory system according to claim 1, wherein the memory controller is configured to transmit connection coefficients associated with the first and second PRBS generators to the memory device, the first PRBS generator is configured to generate the first PRBS based on the connection coefficients and the seed value, and the second PRBS generator is configured to generate the second PRBS based on the connection coefficients and the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101).
Regarding dependent claim 8, Hong further teaches the memory system according to claim 1, wherein the memory device is configured to transmit the generated second PRBS to the memory controller, and the first evaluator is configured to perform the read test on a plurality of data lines based on the first PRBS and the second PRBS (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135).
Regarding dependent claim 9, Hong further teaches the memory system according to claim 8, wherein the memory device is configured to: transmit the second PRBS to the memory controller through a first data line of the plurality of data lines; and transmit the second PRBS to the memory controller through a second data line of the plurality of data lines evaluator (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, DQ data lines), and the memory controller is configured to: determine whether the first data line passes or fails the read test based on the first PRBS and the second PRBS received through the first data line with the first evaluator; and determine whether the second data line passes or fails the read test based on the first PRBS and the second PRBS received through the second data line with the first evaluator (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0152).
Regarding dependent claim 10, Hong further teaches the memory system according to claim 8, wherein the first PRBS includes a first PRBS 1-1 and a first PRBS 1-2, the first PRBS 1-1 and the first PRBS 1-2 are different from each other, the second PRBS includes a second PRBS 2-1 and a second PRBS 2-2, the second PRBS 2-1 and the second PRBS 2-2 are different from each other, the memory device is configured to: transmit the second PRBS 2-1 to the memory controller through a first data line of the plurality of data lines; and transmit the second PRBS 2-2 to the memory controller through a second data line of the plurality of data lines evaluator (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, DQ data lines), and the memory controller: determine whether the first data line passes or fails the read test based on the first PRBS 1-1 and the second PRBS 2-1 received through the first data line with the first evaluator; and determines whether the second data line passes or fails the read test based on the first PRBS 1-2 and the second PRBS 2-2 received through the second data line with the first evaluator (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0151).
Regarding dependent claim 11, Hong further teaches the memory system according to claim 8, wherein the first evaluator includes a plurality of first sub evaluators associated with the plurality of data lines, and whether the plurality of data lines pass or fail the read test is determined based on an evaluation result of the plurality of first sub evaluators (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0130).
Regarding dependent claim 12, Hong further teaches the memory system according to claim 1, wherein the memory controller is configured to transmits the generated first PRBS to the memory device, and the second evaluator is configured to perform the write test on a plurality of data lines by performing an evaluation of the first PRBS and the second PRBS (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0125).
Regarding dependent claim 13, Hong further teaches the memory system according to claim 12, wherein the memory device further includes a mode register, and the memory device is configured to store a write test result for the plurality of data lines in the mode register (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0121).
Regarding dependent claim 14, Hong further teaches the memory system according to claim 13, wherein the memory controller is configured to receive the write test result stored in the mode register from the memory device (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-01305).
Regarding dependent claim 15, Hong further teaches the memory system according to claim 12, wherein the memory controller is configured to: transmit the first PRBS to the memory device through a first data line of the plurality of data lines, and transmit the first PRBS to the memory device through a second data line of the plurality of data lines, and the memory device is configured to: determine whether the first data line passes or fails the write test based on the second PRBS and the first PRBS received through the first data line with the second evaluator; and determine whether the second data line passes or fails the write test based on the second PRBS and the first PRBS received through the second data line with the second evaluator (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0143).
Regarding dependent claim 16, Hong further teaches the memory system according to claim 12, wherein the first PRBS includes a first PRBS 1-1 and a first PRBS 1-2, the first PRBS 1-1 and the first PRBS 1-2 are different from each other, the second PRBS includes a second PRBS 2-1 and a second PRBS 2-2, the second PRBS 2-1 and the second PRBS 2-2 are different from each other, the memory controller is configured to: transmit the first PRBS 1-1 to the memory device through a first data line of the plurality of data lines; and transmit the first PRBS 1-2 to the memory device through a second data line of the plurality of data lines, and the memory device is configured to: determines whether the first data line passes or fails the write test based on the second PRBS 2-1 and the first PRBS 1-1 received through the first data line with the second evaluator; and determines whether the second data line passes or fails the write test based on the second PRBS 2-2 and the first PRBS 1-2 received through the second data line with the second evaluator (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0152).
Regarding dependent claim 17, Hong further teaches the memory system according to claim 12, wherein the second evaluator includes a plurality of second sub evaluators associated with the plurality of data lines, and whether the plurality of data lines pass or fail the write test is determined based on an evaluation result of the plurality of second sub evaluators (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101).
Regarding dependent claim 18, Hong further teaches the memory system according to claim 1, performing a Shmoo test by repeatedly performing at least one of the read test and the write test (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0131).
Regarding independent claim 19, BM et al. teach A memory device, comprising: a PRBS generator configured to receive a seed value from a memory controller and generate a first PRBS based on the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where 200/201 memory controller, unit 211/231 generate seed value, unit 213 generate first PRBS); an evaluator configured to perform an evaluation of the first PRBS and a second PRBS received from the memory controller (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where unit 130 evaluate PRBS); and a mode register configured to store a write test result generated for a plurality of data lines using the evaluator, the first PRBS and the second PRBS being a same PRBS generated based on the same seed value, and the mode register is configured to transmit the write test result to the memory controller (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where read / writes execute through unit 130 based on controller, each PB1…PBm include sensing circuitry to evaluate data and also include register to store write / read data).
Regarding independent claim 20, BM et al. teach A memory system test method, comprising: by a memory controller, generating a seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where 200/201 memory controller, unit 211/231 generate seed value); by the memory controller, transmitting the seed value to a memory device; by the memory controller, generating a first PRBS using the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where unit 213 generate first PRBS); by the memory device, generating a second PRBS using the seed value (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where unit 100/101 memory device, unit 233 generate second PRBS); and by the memory controller, performing the read test by performing an evaluation of the first PRBS and the second PRBS, or by the memory device, performing the write test by performing an evaluation of the first PRBS and the second PRBS (see 1-2, 8, 9-12, 17-20 and paragraph 0005-0007, 0041-0042, 0045-0062, 0101-0135, 0141-0154, where read / writes execute through unit 130 based on controller, each PB1…PBm include sensing circuitry to evaluate data).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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