Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This action is responsive to the Application filed on 11/6/2024. A filing date 11/6/2024 is acknowledged. The sought benefit of IN application 202341076555 (which was filed on 11/9/2023) is acknowledged. Claims 1-20 are pending in this application. Claims 1, 7, 15 are independent claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
3. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Raymond Chau et al (US Publication 20220171373 A1, hereinafter Chau), and in view of Ala Moradian et al (US Publication 20220334569 A1, hereinafter Moradian).
As for independent claim 1, Chau discloses: A method comprising: obtaining, by a processing device, input data indicative of a first set of process parameters (Abstract, The model is used to capture underlying relationships between scheduling parameter values and various wafer processing scenarios to make predictions);
providing the input data to a first process model (Abstract, The model is trained using data collected from preventive maintenance operations, recipe times, and wafer-less auto clean times as inputs); obtaining, from the first process model, first predictive output indicative of performance of a first process operation in accordance with the first set of process parameters (Abstract, The model is used to capture underlying relationships between scheduling parameter values and various wafer processing scenarios to make predictions; [0163], the self-exploration process uses the discrete event simulator 1202 to automate efforts to find the best possible way to operate a system (e.g., to find the best path in which to move a wafer through the tool) at optimum throughput performance); providing the first predictive output to a second process model ([0169], At 1306, the discrete event simulator 1202 outputs the set of next scheduled level operations to the model 1204. At 1308, the model 1204 selects the best next operation to schedule that will provide the best system performance; [0184], In a subsequent layer of the model, the outputs of the neural networks from the initial layer (i.e., the predictions for program execution times and transfer times) are input to a next layer including the scheduler level neural network);
… and performing a corrective action in view of the second predictive output ([0026], The instructions are configured to train the model to recommend the best operations as the plurality of operations in response to the tool progressing through the plurality of states when processing the semiconductor substrates in the plurality of processing chambers according to the recipe; [0088], the smart scheduler can optimize the scheduling parameter values by taking into account preventive maintenance that may have to be skipped or delayed to meet manufacturing deadlines).
Chau discloses providing predictive information to multiple manufacturing processes, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention, to recognize that the next process is different from the previous process, in addition, in an analogous art of optimizing semiconductor manufacturing using machine learning, Moradian discloses: obtaining, from the second process model, second predictive output indicative of performance of a second process operation, different than the first process operation or a repetition of the first process operation, in accordance with the first set of process parameters (Moradian: [0051], performing process step A followed by process step B may result in a first resource consumption while performing process step B followed by process step A may result in a second resource consumption different than the first resource consumption);
Chau and Moradian are analogous arts because they are in the same field of endeavor, optimizing semiconductor manufacturing using machine learning. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention, to modify the invention of Chau using the teachings of Moradian to include performing process step B which is different from performing process step A. It would provide Chau’s method with enhanced capabilities of predicting data for a sequence of process steps more effectively.
As for claim 2, Chau-Moradian discloses: wherein the input data further comprises one or more indications of a substrate, the first predictive output further indicates a predicted result of performance of the first process operation on the substrate, and the second predictive output further indicates a predicted result of performance of the second process operation on the substrate (Chau: [0006], The instructions are configured to train a model using the first data and data generated by the simulation to predict optimum scheduling parameters for processing the semiconductor substrates in the plurality of processing chambers according to the recipe. The instructions are configured to receive inputs from the tool regarding processing of one of the semiconductor substrates in the plurality of processing chambers according to the recipe. The instructions are configured to predict based on the inputs, using the model, optimum scheduling parameters for processing the one of the semiconductor substrates in the plurality of processing chambers according to the recipe).
As for claim 3, Chau-Moradian discloses: wherein the first process operation comprises a first one of a: deposition operation; etch operation; doping operation; annealing operation (Chau: [0004], Semiconductor manufacturers use one or more substrate processing tools to perform deposition, etching, cleaning, and/or other substrate treatments during fabrication of semiconductor wafers; lithography operation; or nitridation operation.
As for claim 4, Chau-Moradian discloses: wherein the second process operation comprises a second one of a deposition operation, etch operation, doping operation, annealing operation; lithography operation, or nitridation operation, different than the first (Chau: [0169], At 1306, the discrete event simulator 1202 outputs the set of next scheduled level operations to the model 1204. At 1308, the model 1204 selects the best next operation to schedule that will provide the best system performance; [0184], In a subsequent layer of the model, the outputs of the neural networks from the initial layer (i.e., the predictions for program execution times and transfer times) are input to a next layer including the scheduler level neural network).
As for claim 5, Chau-Moradian discloses: wherein the first process model is associated with a first process chamber, and wherein the second process model is associated with a second process chamber (Chau: [0006], a plurality of processing chambers configured to process the semiconductor substrates according to a recipe).
As for claim 6, Chau-Moradian discloses: wherein the corrective action (Moradian: [0064], the optimization tool 126 may determine modifications to a manufacturing process that may include performing a corrected action associated with a component of the machine equipment (e.g., machine equipment 104) comprises one of: updating a process recipe (Moradian: [0061], optimization tool 126, and resource consumption tool 130) to dynamically update a determined eco-efficiency when a manufacturing recipe is updated); scheduling maintenance (Moradian: [0077], The scheduling information may include data indicative of upcoming recipes, tool idle states, maintenance, and so on); updating the first process model (Chau: [0131], The model can be updated to adjust for tool performance drift); or providing an alert to a user.
As per claim 7, it recites features that are substantially same as those features claimed by claim 1, thus the rationales for rejecting claim 1 are incorporated herein.
As per claim 8, it recites features that are substantially same as those features claimed by claim 6, thus the rationales for rejecting claim 6 are incorporated herein.
As for claim 9, Chau-Moradian discloses: wherein the first data comprises a metrology measurement of a first feature of a substrate subsequent to performance of the first process operation (Chau: [0222], enable endpoint measurements).
As for claim 10, Chau-Moradian discloses: wherein the first data comprises sensor data of the substrate processing system (Chau: [0093], the processing chamber controllers 130 monitor sensors 135 such as temperature sensors, pressure sensors, position sensors, etc.).
As for claim 11, Chau-Moradian discloses: wherein the first process model comprises a trained machine learning model or a physics-based model (Chau: Abstract, a nested neural network based model is trained using machine learning).
As for claim 12, Chau-Moradian discloses: wherein the first process model comprises a digital twin model of a first process chamber of the substrate processing system (Moradian: [0053], The digital replica tool 124 generates a digital twin of the physical system architecture of the manufacturing system or a virtual inputted system).
As for claim 13, Chau-Moradian discloses: wherein the first process operation comprises one of a deposition operation, an etch operation, a doping operation, an annealing operation, a lithography operation, or a nitridation operation, and wherein the second process operation comprise a second one of these operations, different than the first (Chau: [0169], At 1306, the discrete event simulator 1202 outputs the set of next scheduled level operations to the model 1204. At 1308, the model 1204 selects the best next operation to schedule that will provide the best system performance; [0184], In a subsequent layer of the model, the outputs of the neural networks from the initial layer (i.e., the predictions for program execution times and transfer times) are input to a next layer including the scheduler level neural network).
As for claim 14, Chau-Moradian discloses: wherein the substrate processing system comprises a semiconductor wafer manufacturing system (Chau: [0004], Semiconductor manufacturers use one or more substrate processing tools to perform deposition, etching, cleaning, and/or other substrate treatments during fabrication of semiconductor wafer).
As per claim 15, it recites features that are substantially same as those features claimed by claim 1, thus the rationales for rejecting claim 1 are incorporated herein.
As per claim 16, it recites features that are substantially same as those features claimed by claim 6, thus the rationales for rejecting claim 6 are incorporated herein.
As per claim 17, it recites features that are substantially same as those features claimed by claim 13, thus the rationales for rejecting claim 13 are incorporated herein.
As per claim 18, it recites features that are substantially same as those features claimed by claims 3 and 4, thus the rationales for rejecting claims 3 and 4 are incorporated herein.
As per claim 19, it recites features that are substantially same as those features claimed by claim 11, thus the rationales for rejecting claim 11 are incorporated herein.
As per claim 20, it recites features that are substantially same as those features claimed by claim 5, thus the rationales for rejecting claim 5 are incorporated herein.
Examiner’s Note
Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Applicants are required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Sawlani (US Publication 20230049157) PERFORMANCE PREDICTORS FOR SEMICONDUCTOR-MANUFACTURING PROCESSES
Bhatia (US Publication 20150261215) PREDICTIVE MODELING OF A MANUFACTURING PROCESS USING A SET OF INVERTED MODELS
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hua Lu whose telephone number is 571-270-1410 and fax number is 571-270-2410. The examiner can normally be reached on Mon-Fri 9:00 am to 6:00 pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Scott Baderman can be reached on 571-272-3644. The fax phone number for the organization where this application or proceeding is assigned is 703-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Hua Lu/
Primary Examiner, Art Unit 2118
Prosecution Insights