DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Specification
The disclosure is objected to because of the following informalities: Paragraph [0001], line 2, -- now US Patent No. 12,164,320 issued on Dec. 10, 2024,-- should be inserted after “February 28, 2022,”. Appropriate correction is required.
The disclosure is objected to because of the following informalities: Paragraph [0002] should belong to paragraph [0001], and “[0002]” should be deleted. Appropriate correction is required.
Claim Objections
Claim 3 is objected to because of the following informalities: on line 1, “comprising” should be changed to --further comprising-- . Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are the clear essential structural connections between a switch and a first transistor in a pre-settling circuit, and between these elements and other elements in the pre-settling circuit, as disclosed in the base claim 18. For example, in order for providing these recited functions “turning on a switch in a pre-settling circuit to output a pre-settling voltage to an output node” and “detecting the feedback signal at a first transistor in the pre-settling circuit; outputting the pre-settling voltage to the output node in response to the feedback signal being below a threshold volage of the first transistor; and turning off the switch to discontinue the outputting of the pre-settling voltage to the output node in response to the feedback signal being above the threshold voltage of the first transistor.” the above essential structural connections are needed for supporting the recited functions. Furthermore, claims 19-21 are also rejected due to their dependencies on the base claim 18.
Claim 20 is indefinite because the limitation “a switch”, in line 1, lacks clear antecedent basis. It is unclear if the limitation is referring to previously recited a switch in line 2 of the base claim 18, or introducing a new switch. It appears they are the same, which is based on the disclosure. Appropriate correction and/or clarification is required.
Claim 21 is indefinite because the limitation “a first transistor”, in line 1, lacks clear antecedent basis. It is unclear if the limitation is referring to previously recited a first transistor in line 6 of the base claim 18, or introducing a new first transistor. It appears they are the same, which is based on the disclosure. Appropriate correction and/or clarification is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-7 and 9-12 of U.S. Patent No. 11,262,778. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/939,077
U.S. Patent No. 11,262,778
Claim 2: A reference voltage generator, comprising: an input terminal configured to receive an enable signal; an output terminal configured to provide an output voltage;
a load configured to provide a first feedback signal that is responsive to the enable signal and based on the output voltage (1); and
a pre-settling circuit configured to generate a pre-settling output voltage at the output terminal in response to the enable signal and to discontinue providing the pre settling output voltage at the output terminal based on the first feedback signal, wherein the pre-settling circuit includes a switch responsive to the enable signal and to the first feedback signal to selectively generate the pre-settling output voltage.
Claim 3: The reference voltage generator of claim 2, comprising a voltage generator circuit that is coupled to the output terminal and configured to generate a voltage generator output voltage at the output terminal in response to the enable signal (2).
Claim 4: The reference voltage generator of claim 3, wherein the voltage generator circuit includes an operational amplifier having an output coupled to the output terminal and a first input connected to the input terminal, a second input connected to receive a reference voltage, and a third input configured to receive a second feedback signal from the load, wherein the operational amplifier is configured to provide the voltage generator output voltage.
Claim 5: The reference voltage generator of claim 3, wherein the voltage generator output voltage settles over time to a first predetermined voltage level, and the pre-settling output voltage settles over time to a second predetermined voltage level, wherein the pre-settling circuit is configured so that the pre-settling output voltage settles to the second predetermined voltage level more rapidly than the voltage generator output voltage settles to the first predetermined voltage level.
Claim 6: The reference voltage generator of claim 2, wherein the switch is coupled to the output terminal and a current source.
Claim 7: The reference voltage generator of claim 6, wherein the switch is responsive to the enable signal and the first feedback signal to selectively couple the output terminal to the current source based on the first feedback signal and to generate the pre-settling output voltage of the pre settling circuit when the switch is in a turned-on state.
Claim 1: A reference voltage generator, comprising: an input terminal configured to receive an enable signal; an output terminal configured to provide an output voltage;
a voltage generator circuit coupled to the output terminal and arranged to generate a first output voltage at the output terminal; and
a pre-settling circuit coupled to the input terminal and the output terminal and arranged to generate a second output voltage at the output terminal; wherein the pre-settling circuit is configured to provide the second output voltage at the output terminal in response to the enable signal received at the input terminal, and following a first time period discontinue providing the second output voltage at the output terminal, such that the voltage generator circuit provides the first output voltage at the output terminal; and
wherein the pre-settling circuit is coupled to the voltage generator circuit to receive a feedback signal from the voltage generator circuit and configured to determine the first time period in response to the feedback signal from the voltage generator circuit (2).
Claim 3: The reference voltage generator of claim 1, wherein the voltage generator circuit includes a load coupled to the output terminal, and wherein the feedback signal includes a voltage level of the load (1).
Claim 4: The reference voltage generator of claim 1, wherein the voltage generator circuit comprises an operational amplifier having an output coupled to the output terminal and a first input connected to the input terminal, a second input connected to receive a reference voltage, and a third input configured to receive the feedback signal from the voltage generator circuit, and wherein the operational amplifier is arranged to generate the first output voltage.
Claim 2: The reference voltage generator of claim 1, wherein the first output voltage settles over time to a first predetermined voltage level, and the second output voltage settles over time to a second predetermined voltage level, wherein the pre-settling circuit is configured so that the second output voltage settles to the second predetermined voltage level more rapidly than the first output voltage settles to the first predetermined voltage level.
Claim 5: The reference voltage generator of claim 1, wherein the pre-settling circuit comprises a switch coupled to the voltage generator circuit and a current source, wherein the switch is responsive to the enable signal to selectively couple the voltage generator circuit to the current source based on the feedback signal to generate the second output voltage of the pre-settling circuit when the switch is in a turned on state.
Claims 8-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10, 9, 11, 12, 6 and 7 of U.S. Patent No. 11,262,778, respectively, because they are substantially identical.
Claims 14-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 13-15 of U.S. Patent No. 11,262,778. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/939,077
U.S. Patent No. 11,262,778
Claim 14: A circuit, comprising: an input terminal configured to receive an enable signal; an output terminal configured to provide an output voltage; a load configured to provide a feedback signal that is responsive to the enable signal and based on the output voltage; a voltage detector circuit configured to provide a switch enable signal that is based on the enable signal and the feedback signal; and a switch configured to provide a pre-settling output voltage at the output terminal based on the enable signal and the switch enable signal, wherein the switch includes: a first transistor having a first source/drain terminal coupled to the output terminal and a gate terminal configured to respond to the switch enable signal; a second transistor having a first source/drain terminal coupled to a power device and a gate terminal configured to respond to the switch enable signal; and a third transistor coupled in series between a second source/drain terminal of each of the first and second transistors and a current source and having a gate terminal configured to respond to the enable signal.
Claim 15: The circuit of claim 14, wherein the voltage detector circuit comprises: a PMOS transistor having a first source/drain terminal coupled to a power supply terminal, and a gate terminal coupled to the input terminal; a first NMOS transistor having a first source/drain terminal coupled to a second source/drain terminal of the PMOS transistor, and a gate terminal coupled to the input terminal; a second NMOS transistor having a first source/drain terminal coupled to a second source/drain terminal of the first NMOS transistor, and a second source/drain terminal coupled to a ground terminal, and a gate terminal coupled to receive the feedback signal; and a capacitor coupled between the first source/drain terminal of the first NMOS transistor and the ground terminal.
Claim 16: The circuit of claim 15, wherein the gate terminal of the first transistor and the gate terminal of the second transistor are coupled to the first source/drain terminal of the first NMOS transistor and the second source/drain terminal of the PMOS transistor via a plurality of inverters. Claim 17: The circuit of claim 16, wherein the plurality of inverters include a first inverter and a second inverter coupled in series between the first source/drain terminal of the first NMOS transistor and the gate terminals of the first transistor and the second transistor.
Claim 13: A circuit, comprising: an input terminal configured to receive an enable signal; a voltage detector circuit coupled to the input terminal and configured to receive a load feedback signal that is responsive to the enable signal; and a switch coupled to the voltage detector circuit and coupled between a voltage generator output and a current source, wherein the switch is responsive to the voltage detector circuit to selectively couple the voltage generator output to the current source based on the load feedback signal received by the voltage detector circuit, wherein the switch includes: first and second switch transistors, the first switch transistor having a first source/drain terminal coupled to the voltage generator output and a gate terminal coupled to the input terminal and configured to respond to the enable signal and the voltage detector circuit, the second switch transistor having a first source/drain terminal coupled to a power device a gate terminal coupled to the input terminal and configured to respond to the enable signal and the voltage detector circuit; and a third transistor coupled in series between a second source/drain terminal of each of the first and second switch transistors and the current source and having a gate terminal coupled to the input terminal.
Claim 14: The circuit of claim 13, wherein the voltage detector circuit comprises: a PMOS transistor having a first source/drain terminal coupled to a power supply terminal, and a gate terminal coupled to the input terminal; a first NMOS transistor having a first source/drain terminal coupled to a second source/drain terminal of the PMOS transistor, and a gate terminal coupled to the input terminal; a second NMOS transistor having a first source/drain terminal coupled to a second source/drain terminal of the first NMOS transistor, and a second source/drain terminal coupled to a ground terminal, and a gate terminal coupled to receive the load feedback signal; and a capacitor coupled between the second source/drain terminal of the first NMOS transistor and the ground terminal.
Claim 15: The circuit of claim 14, further comprising first and second inverters coupled between the second source/drain terminal of the first NMOS transistor and the gate terminals of the first and second switch transistors.
Claim 15: The circuit of claim 14, further comprising first and second inverters coupled between the second source/drain terminal of the first NMOS transistor and the gate terminals of the first and second switch transistors.
Claims 2-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-5 and 7-12 of U.S. Patent No. 12,164,320. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/939,077
U.S. Patent No. 12,164,320
Claim 2: A reference voltage generator, comprising: an input terminal configured to receive an enable signal; an output terminal configured to provide an output voltage; a load configured to provide a first feedback signal that is responsive to the enable signal and based on the output voltage; and
a pre-settling circuit configured to generate a pre-settling output voltage at the output terminal in response to the enable signal and to discontinue providing the pre settling output voltage at the output terminal based on the first feedback signal, wherein the pre-settling circuit includes a switch responsive to the enable signal and to the first feedback signal to selectively generate the pre-settling output voltage.
Claim 3: The reference voltage generator of claim 2, comprising a voltage generator circuit that is coupled to the output terminal and configured to generate a voltage generator output voltage at the output terminal in response to the enable signal.
Claim 4: The reference voltage generator of claim 3, wherein the voltage generator circuit includes an operational amplifier having an output coupled to the output terminal and a first input connected to the input terminal, a second input connected to receive a reference voltage, and a third input configured to receive a second feedback signal from the load, wherein the operational amplifier is configured to provide the voltage generator output voltage.
Claim 5: The reference voltage generator of claim 3, wherein the voltage generator output voltage settles over time to a first predetermined voltage level, and the pre-settling output voltage settles over time to a second predetermined voltage level, wherein the pre-settling circuit is configured so that the pre-settling output voltage settles to the second predetermined voltage level more rapidly than the voltage generator output voltage settles to the first predetermined voltage level.
Claim 6: The reference voltage generator of claim 2, wherein the switch is coupled to the output terminal and a current source (1).
Claim 7: The reference voltage generator of claim 6, wherein the switch is responsive to the enable signal and the first feedback signal to selectively couple the output terminal to the current source based on the first feedback signal and to generate the pre-settling output voltage of the pre settling circuit when the switch is in a turned-on state (2).
Claim 1: A reference voltage generator, comprising: an input terminal configured to receive an enable signal; an output terminal configured to provide an output voltage; a load configured to provide a first feedback signal that is responsive to the enable signal and based on the output voltage; and
a pre-settling circuit coupled to the input terminal, the output terminal, and the load and configured to generate a pre-settling output voltage at the output terminal in response to the enable signal received at the input terminal, and to discontinue providing the pre-settling output voltage at the output terminal following a first time period.
Claim 2: The reference voltage generator of claim 1, comprising a voltage generator circuit that is coupled to the output terminal and configured to generate a voltage generator output voltage at the output terminal in response to the enable signal.
Claim 3: The reference voltage generator of claim 2, wherein the voltage generator circuit includes an operational amplifier having an output coupled to the output terminal and a first input connected to the input terminal, a second input connected to receive a reference voltage, and a third input configured to receive a second feedback signal from the load, wherein the operational amplifier is configured to provide the voltage generator output voltage.
Claim 4: The reference voltage generator of claim 2, wherein the voltage generator output voltage settles over time to a first predetermined voltage level, and the pre-settling output voltage settles over time to a second predetermined voltage level, wherein the pre-settling circuit is configured so that the pre-settling output voltage settles to the second predetermined voltage level more rapidly than the voltage generator output voltage settles to the first predetermined voltage level.
Claim 5: The reference voltage generator of claim 1, wherein the pre-settling circuit comprises a switch coupled to the output terminal and a current source (1), wherein the switch is responsive to the enable signal to selectively couple the output terminal to the current source based on the first feedback signal and to generate the pre-settling output voltage of the pre-settling circuit when the switch is in a turned-on state (2).
Claims 8-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-12 of U.S. Patent No. 12,164,320, respectively, because they are substantially identical.
Claims 14-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 13-16 of U.S. Patent No. 12,164,320. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/939,077
U.S. Patent No. 12,164,320
Claim 14: A circuit, comprising: an input terminal configured to receive an enable signal; an output terminal configured to provide an output voltage; a load configured to provide a feedback signal that is responsive to the enable signal and based on the output voltage (1); a voltage detector circuit configured to provide a switch enable signal that is based on the enable signal and the feedback signal; and a switch configured to provide a pre-settling output voltage at the output terminal based on the enable signal and the switch enable signal (2), wherein the switch includes: a first transistor having a first source/drain terminal coupled to the output terminal and a gate terminal configured to respond to the switch enable signal; a second transistor having a first source/drain terminal coupled to a power device and a gate terminal configured to respond to the switch enable signal; and a third transistor coupled in series between a second source/drain terminal of each of the first and second transistors and a current source and having a gate terminal configured to respond to the enable signal (3).
Claim 13: A circuit, comprising: an input terminal configured to receive an enable signal; an output terminal configured to provide an output voltage; a voltage detector circuit coupled to the input terminal and configured to receive a load feedback signal that is responsive to the enable signal and based on the output voltage (1); and a switch coupled to the voltage detector circuit and a current source, wherein the switch is responsive to the voltage detector circuit to selectively couple the output terminal to the current source based on the load feedback signal received by the voltage detector circuit (2), wherein the switch includes: a first transistor having a first source/drain terminal coupled to the output terminal and a gate terminal configured to respond to the voltage detector circuit; a second transistor having a first source/drain terminal coupled to a power device and a gate terminal configured to respond to the voltage detector circuit; and a third transistor coupled in series between a second source/drain terminal of each of the first and second transistors and the current source and having a gate terminal coupled to the input terminal (3).
Claims 15-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14-16 of U.S. Patent No. 12,164,320, respectively, because they are substantially identical.
Claims 18 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 17 and 20 of U.S. Patent No. 12,164,320. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/939,077
U.S. Patent No. 12,164,320
Claim 18: A method, comprising: turning on a switch in a pre-settling circuit to output a pre-settling voltage to an output node (1);
generating a feedback signal, that is based at least in part on the pre-settling voltage, from a load coupled to the output node; detecting the feedback signal at a first transistor in the pre-settling circuit (2);
outputting the pre-settling voltage to the output node in response to the feedback signal being below a threshold volage of the first transistor (3); and
turning off the switch to discontinue the outputting of the pre-settling voltage to the output node in response to the feedback signal being above the threshold voltage of the first transistor (4).
Claim 21: The method of claim 18, wherein detecting the feedback signal at a first transistor in the pre-settling circuit includes receiving the feedback signal at a gate of the first transistor and comparing the feedback signal to the threshold voltage of the first transistor
Claim 17: A method, comprising: enabling a pre-settling circuit to output a pre-settling voltage to an output node (1);
comparing a feedback signal from a load coupled to the output node to a predetermined voltage level by the pre-settling circuit (2);
outputting the pre-settling voltage to the output node from the pre-settling circuit in response to the feedback signal from the load being below the predetermined voltage level (3); and discontinuing the outputting of the pre-settling voltage to the output node from the pre-settling circuit in response to the feedback signal from the load being above the predetermined voltage level (4).
Claim 20: The method of claim 17, wherein comparing the feedback signal from the load to the predetermined level comprises providing the feedback signal from the load to a gate of a transistor of the pre-settling circuit, and outputting the pre-settling voltage in response to the feedback signal being below a threshold voltage of the transistor.
Conclusion
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/HAI L NGUYEN/Primary Examiner, Art Unit 2839 April 6, 2026
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