Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-16, 18, 19, and 20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 09/30/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16, 18, 19, and 20 are rejected 35 U.S.C. 103 as being unpatentable over PAPPU et al. (USPGPUB No. 2023/0114271 A1) in view of Ansari et al. (USPGPUB No. 2024/0394216 A1) and further in view of SUBRAHMANYA et al. (USPGPUB No. 2022/0045945 A1, hereinafter referred to as SUBRAHMANYA).
Referring to claim 1, Pappu discloses a chiplet, comprising {“package assembly that includes multiple units of hardware logic chiplets”, see Fig. 24c, [0032]}:
an interconnect module {“interconnect structure 2473”, see Fig. 24C, [0352]} for connecting to another chiplet {“route electrical signals between the various [another] chiplet”, see Fig. 24C, [0352]};
a bus interface {“physical or bus logic including a USB controller 2525”, see Fig. 25, [0358]} for connecting to at least one functional module in the chiplet {“one or more application processor(s) 2505”, see Fig. 25, [0358], 2nd sentence};
and a save and forward module connected {save and forwarding “inferencing system on a chip for performing [and forwarding] inferencing using a trained model”, see Fig. 13, [0019], [0221], 1st sentence; another example of save and forward module “various caches 462A-462d… over a coherence bus 464” (see Fig. 4b, [0121]} to the interconnect module and the bus interface {“ function as an application processor to execute software applications that can make use of the inferencing compute” such as the application processors 2505 (see Fig. 25, [0223], [0358])}, wherein the save and forward module comprises:
a first port {port examples “data port 2156” (see Fig. 21, [0318]) or “data port 1814” (see Fig. 18a [0288])} that receives a transaction from one of the interconnect module or the bus interface {“ routers 2903 to route transaction traffic through the mainstream agents”, see Fig. 29, [0387]};
a data buffer {“Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data”, see Fig. 2a, [0059] last sentence} that temporarily stores at least a portion of the transaction {“send cache line transactions in bursts [/portions]”, see Fig. 28, [0381]};
Pappu does not appear to explicitly disclose wherein the first port is a slave port and a master port that transmits the transaction stored in the data buffer to the other one of the interconnect module or the bus interface, and the transaction is divided into predetermined units and transmitted, and while at least the portion of the transaction is stored in the data buffer, access to the slave port, by the at least one functional module, is allowed.
However, Ansari discloses wherein the first port is a slave port and a master port {“uses AES master port 854 (e.g., a 128-bit write-only master interface) to direct packets…. To AES-GCM circuitry 810” (see Fig. 8, [0139]} that transmits the transaction stored in the data buffer {“pushes [transmits] write transactions to an input [data] FIFO buffer of packet processor 804 through AES slave port 856”, see Fig. 8, [0140]} to the other one of the interconnect module or the bus interface {“NPI bus 750, [other types of interconnect] NPI switch 748, link 739, and LCI 738”, see Fig. 7, [0109]}, and the transaction is divided into predetermined units and transmitted {“remaining part of the [transaction] partitions 510 is divided into multiple packets”, see Fig. 5, [0090]}, and while at least the portion of the transaction is stored in the data buffer {“packet 600 is divided into a header 605 and a packet data 610 (Le., a payload”, see Fig. 6, [0092]}, access to the slave port, by the at least one functional module, is allowed {“delegated [allowed] to the CIM circuits once the packets are received by those circuits” (see Fig. 5, [0091]) that include functional modules/slave port “functional circuitry 706-1 includes fixed-function circuitry 730” ([0097], 1st sentence)}.
Pappu and Ansari are analogous because they are from the same field of endeavor, chiplets that manage transactions and classifiers.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Pappu and Ansari before him or her, to modify Pappu’s “package assembly that includes multiple units of hardware logic chiplets” (see Fig. 24c, [0032]) incorporating Ansari’s “integrated circuit device 700” (see Fig. 3, [0096]) and respective master port/”AES-GCM circuitry 810” (see Figs. 7 and 8).
The suggestion/motivation for doing so would have been to implement functional circuitry and distributed management circuitry that includes a plurality of configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over a packet-switched network-on-chip (NoC), (Ansari [0006]) as an alternative solution/circumvent problems associated with such complex heterogeneous IC devices, a traditional centralized configuration manager becomes a bottleneck during configuration and initialization (Ansari [0002] last two sentences paraphrased).
Therefore, it would have been obvious to combine Ansari with Pappu to obtain the invention as specified in the instant claim(s).
However, neither Pappu or Ansari does not appear to explicitly disclose a transaction counter that determines whether all of a plurality of bits of the transaction are received based on a burst length and a burst size of the transaction;
And wherein the transaction counter generates and transmits an error signal to an interrupt handler based at least in part on determining less than all of the plurality of bits of the transaction are received within a predetermined error time threshold..
However, SUBRA discloses a transaction counter {“MPU can have [transaction] performance counters to count MPU stalls” (see Fig. 8 [0093], last two sentences) as the MPU handle AXI transactions “may track which bytes have been written to (a.k.a. dirty bytes) and which remain unchanged. When the table entry is flushed back to the memory, the dirty byte vector may be provided to AXI as a write strobe… dirty bytes in the table need not be contiguous” (see Fig. 8, [0087])} that determines whether all of a plurality {determination upon inquiring “flow table 1901 and scheduling aged out network traffic flows [of a plurality of transactions]”, see Fig. 19 [0139]} of bits of the transaction are received {bits of the transaction “Flow table 1901 has been divided into [bits] M shards” (see Fig. 19, [0139], 2nd sentence) received via aggregation/encapsulation “[bits] blocks of the memory may be independently lockable and some of the shard boundaries may coincide with the boundaries between lockable memory blocks [for one or more transactions]” (see Fig. 19 [0139], 4th sentence)} based on a burst length {“AXI interface 802 may include … burst based transactions”, see Fig. 8 [0087]} and a burst size of the transaction {“support unaligned data transfers using [burst size] byte strobes”, see Fig. 8, [0087]};
And wherein the transaction counter generates and transmits an error signal {“to [generate and transmit] send error messages and operational information indicating success or failure”, see Figs. 2 and 3 [0055], last sentence} to an interrupt handler {“PDMA 1010” DMA engine known for handling interrupts including “interrupt assertion writes”, see Fig. [0110], 4th sentence} based at least in part on determining less than all {“This is beneficial to prevent memory to memory read latency from blocking packet processing commands” ([0110], last three sentences) said commands determined to lack byte boundary “issuing of multiple outstanding addresses with out of order responses” or stalling timeframe (see Fig. 8 [0087]} of the plurality of bits of the transaction are received {“Placing those operations on a serialization queue for that flow processor worker ensures that the operations are performed in order [for a given AXI transaction]”, see Fig. 21, [0145], 2nd sentence} within a predetermined error time threshold {“P4+ pipeline stages processing multiple operations at the same time), however, is desired in order to perform more operations over a [error time threshold] given time”, see Fig. 21 [0142], last four sentences}.
Pappu/Ansari and SUBRA are analogous because they are from the same field of endeavor, chiplets that manage transactions and classifiers.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Pappu/Ansari and SUBRA before him or her, to modify Pappu/Ansari’s system incorporating SUBRA’s “match processing unit 801” and AXI protocol as appropriate (see Fig. 8, [0086], [0087]).
The suggestion/motivation for doing so would have been to implement match-action pipelines is a part of a data plane that can process network traffic flows extremely quickly, but only after being configured to process those traffic flows find a flow entry for the network traffic flow (SUBRA [0043]) which in turn facilitates throughput and CPS can be increased when processing is not repeated in different parts of the network appliance, when unnecessary processing is avoided, and when processing is performed by the fastest subsystem that can perform the processing (SUBRA [0042], last sentence).
Therefore, it would have been obvious to combine SUBRA with Pappu/Ansari to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Ansari discloses wherein, in response to determining that entire transaction is stored in the data buffer {“ type of the transaction, including length and width of the transaction is defined by commands embedded within a packet” including whether the entire transaction can be transferred/transmitted, see Fig. 8, [0138], 2nd sentence}, the master port transmits the entire transaction {“DMA engines 816 may transfer or stream the readback data to memory”, see Fig. 8, [0141], last two sentences}.
As per claim 3, the rejection of claim 1 is incorporated and Pappu discloses wherein the transaction is a burst transaction transmitted with a burst transfer method {“to send cache line transactions in bursts.”, see Fig. 28, [0381]}, the burst transaction comprises a plurality of bits, and the predetermined unit is a bit unit {“bit-boundary block transfers”, see Fig. 16a, [0261]}.
As per claim 4, the rejection of claim 1 is incorporated and Ansari discloses wherein the chiplet is a receiver side chiplet {“transceivers, chiplets,”, see Fig. 7, [0101], 2nd sentence} that receives the transaction from the other chiplet {“provides [transactions] configuration parameters [and conversely from] an off-chip device 711 e.g., a chiplet”, see Fig. 7, [0101], last two sentences}, the slave port receives the transaction from the interconnect module {“pushes [transmits] write transactions to an input [data] FIFO buffer of packet processor 804 through AES slave port 856”, see Fig. 8, [0140]}, and the master port transmits the transaction to the bus interface {“uses AES master port 854 (e.g., a 128-bit write-only master interface) to direct packets…. To AES-GCM circuitry 810” (see Fig. 8, [0139]}.
As per claim 5, the rejection of claim 4 is incorporated and Pappu discloses wherein the bus interface is an Advanced extensible Interface (AXI) type interface {“converts IoSF to Advanced eXtensible Interface”, see Fig. 30, [0391]}.
As per claim 6, the rejection of claim 3 is incorporated and Pappu discloses, wherein the save and forward module further comprises:
a transaction decoder that receives the plurality of bits from the slave port {“graphics processing engines 431, 432a, may comprise… media processing engines (e.g., video encoders/decoders”, see Fig. 4b, [0123]}; and the transaction counter that receives information associated with each bit received from the transaction decoder {such engines 431 and 432 includes transaction counters “setup operands and access [counter/subtract/multiply/divide] computation results, without the overhead of tradition I/O DMA data copies”, see Fig. 4F, [0154]}.
As per claim 7, the rejection of claim 6 is incorporated and Pappu discloses wherein the transaction counter determines whether all of the plurality of bits are received {“A selection between GPU bias and host processor bias may be driven by a [transaction] bias tracker data structure.”, see Fig. 4F, [0155], 1st sentence}, and in response to determining that all of the plurality of bits are received {“The efficiency of operand setup [received]”, see Fig. 4F, [0154], last sentence}, causes the master port to transmit all of the plurality of bits stored in the data buffer {“the efficiency of results access, and the efficiency of GPU computation [of the plurality of bits] all play a role in determining the effectiveness of GPU offload”, see Fig. 4F, [0154] last sentence}.
As per claim 8, the rejection of claim 6 is incorporated and Pappu discloses wherein the transaction decoder determines {“agent 2805 is capable of sending cache line transactions, or [determining] can access any rows of interest, any columns of interest”, see Fig. 28, [0381], 1st sentence} that the transaction is a burst transaction {“interface 2801 to send cache line transactions in bursts”, see Fig. 28, [0381], last two sentences}, based on control information included in a first bit received from the slave port {control information “finite state machine (FSM) 2835, data and command multiple input signature registers (MISRs) 2850, and a simple task actor protocol (STAP) interface 2855.” (see Fig. 28, [0380], 2nd sentence}.
As per claim 9, the rejection of claim 8 is incorporated and Pappu discloses wherein, in response to determining that the transaction is the burst transaction {“agent 2805 is capable of sending cache line transactions, or [determining] can access any rows of interest, any columns of interest”, see Fig. 28, [0381], 1st sente}, the transaction decoder stores the bits received from the slave port in the data buffer {“transactions at the low power state agent 2805 can go through hashing in order to support virtual to physical address mapping” (see Fig. 28, [0381], 2nd sentence} including mapping to the data buffer “address mapping 2904 components (e.g., hashing tables etc.) to translate the SoC logic address to the local memory device physical address” (see Fig. 29, [0385]).
As per claim 10, the rejection of claim 8 is incorporated and Pappu discloses wherein the transaction counter generates the error signal {“all media pipeline states should be valid”, see Fig. 22, [0336]} based on the control information and a data size of the transaction {control information “issuing a media object command 2242” ([0336]) that includes a non-zero data size of the “specific media decode operations ([0334])}.
As per claim 11, the rejection of claim 10 is incorporated and Pappu discloses wherein the save and forward module further comprises the interrupt handler {save forward module “various caches 462a” (see Fig. 4b, [0121] 1st sentence) including interrupt handler “interrupt management services on behalf of” ([0123], 1st sentence}, and the interrupt handler receives the error signal from the transaction counter {“The interrupt management circuit 447 may process interrupt events 492 received from the graphics acceleration module 446 [transaction counter].”, see Fig. 4D, [0141]}, generates a first interrupt based on the first error signal {“Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit”, see Table 1 after [0142]}, and transmits the first interrupt to a host {interrupt events “workloads or interrupts can be used to identify or indicate availability of work to perform” ([0055]) including an error as claimed “Errors are then propagated back through the system [including to a host]” that initiated the training sequence (see Fig. 11, [0201]}.
As per claim 12, the rejection of claim 6 is incorporated and Pappu discloses wherein the save and forward module further comprises a transaction time table register {“which has a [tabular] structure similar to a CNN and is trained in a manner similar to a deep belief network”, see Fig. 10, [0198]} that manages a transaction time table associated with the transaction {“processing longer sequences of language [transactions]”, see Fig. 10, [0198]}.
As per claim 13, the rejection of claim 12 is incorporated and Pappu discloses wherein the transaction time table comprises at least one of a validity of the transaction, an ID of the transaction {“Process and Thread Identification”, see Table 2 after [0143]}, a transmission start time, a transmission end time, an error occurrence time {Examiner’s note: recitation of “or” term renders this claim a Markush claim, thus the reference need only disclose one group member in order to address the claim}, or an error flag {“ an error signal representing the difference between the output and the labeled output is calculated”, see Fig. 2a, [0171]}.
As per claim 14, the rejection of claim 12 is incorporated and Ansari discloses wherein the save and forward module further comprises a timer, and the transaction time table register records at least one of a transmission start time {“[time] synchronizing command is a type of command that stalls issuance of further commands until the synchronizing command is has completed” (see Fig. 11, [0191], 1st sentence) in table register “Class Codes Description” (see Figs. 10 and 11, Table 2 after [0187])}, a transmission end time, or an error occurrence time of the transaction in the transaction time table using the timer {Examiner’s note: recitation of “or” term renders this claim a Markush claim, thus the reference need only disclose one group member in order to address the claim}.
As per claim 15, the rejection of claim 12 is incorporated and Ansari discloses wherein the save and forward module further comprises a comparator {compares as claimed “provide a SHA digest and compares the SHA digest”, see Fig. 7, [0132] 1st sentence} that generates a second error signal associated with a transmission time of the transaction {“Condition Register 1010 user choice Condition register that logs possible error” in Table 7 after [0199], see Figs. 11 and 12}, and in response to determining that the predetermined error time threshold has been exceeded {“compare the readback data to configuration parameters”, see Figs. 8 and 9, [0153]} since a transmission start time of the transaction recorded in a time table of the transaction {“[time table] dynamic scheduling algorithm of relocatable configuration contexts”, see Fig. 2a, [0066]}, the comparator generates the second error signal {“debug packet controller for identifying errors that may occur during the configuration process”, see Fig. 4, [0074], last sentence}.
As per claim 16, the rejection of claim 15 is incorporated and Ansari discloses wherein the save and forward module further comprises an interrupt handler {“[an interrupt handler] may send an error message/interrupt to central management circuitry 702”, see Fig. 8, [0132]}, and the interrupt handler receives the second error signal from the comparator {“debug packet controller for identifying errors that may occur during the configuration process”, see Fig. 4, [0074], last sentence}, generates a second interrupt based on the second error signal {“may send an error message/interrupt to central management circuitry 702”, see Fig. 8, [0132]}, and transmits the second interrupt to a host {“communicates error/interrupt packets on the GCR to [host] central management circuitry 702”, see Fig. 8, [0126]}.
As per claim 18, the rejection of claim 1 is incorporated and Ansari discloses wherein the chiplet is a transmitter side chiplet {“transceivers, chiplets,”, see Fig. 7, [0101], 2nd sentence} that transmits the transaction to the other chiplet {“provides [transactions] configuration parameters to an off-chip device 711 e.g., a chiplet”, see Fig. 7, [0101], last two sentences}, the slave port receives the transaction from the bus interface {“pushes [transmits] write transactions to an input [data] FIFO buffer of packet processor 804 through AES slave port 856”, see Fig. 8, [0140]}, and the master port transmits the transaction to the interconnect module {“uses AES master port 854 (e.g., a 128-bit write-only master interface) to direct packets…. [and conversely from] AES-GCM circuitry 810” (see Fig. 8, [0139]}.
As per claim 19, the rejection of claim 3 is incorporated and Ansari discloses wherein the slave port transmits to the data buffer whenever the slave port receives a plurality of bits included in the transaction in units of bits {“configured to perform an integrity check on the portions packets”, see Fig. 3, [0069]}, the data buffer sequentially stores the received bits {“increments the address with each write operation until data engine 904 is programmed with a new base address”, see Fig. 9a and 9b, [0155], last sentence}, and before all of the plurality of bits are stored in the data buffer {“pushes resultant data to read FIFO buffer 906 of data engine 904 over link 824”, see Fig. 9a, [0155], 2nd sentence}, transmission of at least one bit stored in the buffer is not performed {“packet 600 is divided into a header 605 and a packet data 610 (Le., a payload”, see Fig. 6, [0092]}.
As per claim 20, the rejection of claim 1 is incorporated and Pappu discloses wherein a size of the data buffer is determined based {“all media pipeline states should be valid”, see Fig. 22, [0336]} on a data size of the transaction {control information “issuing a media object command 2242” ([0336]) that includes a non-zero data size of the “specific media decode operations ([0334])}.
Response to Arguments
Applicant’s arguments filed on 11/25/2025 have been considered but deemed moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative of the current state of the art regarding claim 1’s “chiplet”, “interconnect module”, or “transaction counter”: US 20250139040 A1,US 11487685 B2, US 20220245072 A1, US 20220045945 A1, US 20220045940 A1, US 20210288910 A1, US 10509751 B2, US 9804988 B1, AND US 9286258 B2.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.B./
Examiner
Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184