Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 12, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US Pat # 10915133).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Zhang et al. teach a low dropout (LDO) regulator, comprising: a transistor (see Fig.11, column 16 lines 64-67, column 17 lines 1-18 , transistor 1111); an amplifier (Fig.11, column 16 lines 64-67, column 17 lines 1-18 , unit 1101); and a clamping circuit (Fig.11, column 16 lines 64-67, column 17 lines 1-18 , Unit (1131+1135+RL)), wherein: an output of the LDO regulator is coupled to a first terminal of the transistor; an output of the clamping circuit is coupled to a gate terminal of the transistor; and an output of the amplifier is coupled to the gate terminal of the transistor (see Fig.11, column 16 lines 64-67, column 17 lines 1-18 where output of LDO regulator Vout coupled to first terminal of transistor 1111, output of clamp circuit coupled to gate of 1111 through RU resistor, output of amplifier 1101 coupled to gate of 1111).
Even though Zhang et al. teach compensation circuit but silent exclusively about clamping circuit. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Zhang et al. where circuitry (1131+RL+1135) are working to clamp the output and would be called clamping circuit in order to stabilize the output voltage and to improve power supply rejection ratio including phase margin (see column 19 lines 63-67, column 20 lines 1-3).
Regarding independent claim 12, Zhang et al. teach a memory device, comprising: a memory cell array; and a peripheral circuit coupled to the memory cell array and comprising an LDO regulator, and the LDO regulator comprises: a transistor (see Fig.2, 11, column 2 lines 29-63, column 16 lines 64-67, column 17 lines 1-18 , transistor 1111); an amplifier (Fig.11, column 16 lines 64-67, column 17 lines 1-18 , unit 1101); and a clamping circuit (Fig.11, column 16 lines 64-67, column 17 lines 1-18 , Unit (1131+1135+RL)), wherein: an output of the LDO regulator is coupled to a first terminal of the transistor; an output of the clamping circuit is coupled to a gate terminal of the transistor; and an output of the amplifier is coupled to the gate terminal of the transistor (see Fig.11, column 16 lines 64-67, column 17 lines 1-18 where output of LDO regulator Vout coupled to first terminal of transistor 1111, output of clamp circuit coupled to gate of 1111 through RU resistor, output of amplifier 1101 coupled to gate of 1111).
Even though Zhang et al. teach compensation circuit but silent exclusively about clamping circuit. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Zhang et al. where circuitry (1131+RL+1135) are working to clamp the output and would be called clamping circuit in order to stabilize the output voltage and to improve power supply rejection ratio including phase margin (see column 19 lines 63-67, column 20 lines 1-3).
Regarding independent claim 20, Zhang et al. teach a memory system, comprising: a memory device, comprising: a memory cell array; and a peripheral circuit coupled to the memory cell array and comprising an LDO regulator, and the LDO regulator comprises: a transistor (see Fig.2, 11, column 2 lines 29-63, column 16 lines 64-67, column 17 lines 1-18 , transistor 1111); an amplifier (Fig.11, column 16 lines 64-67, column 17 lines 1-18 , unit 1101); and a clamping circuit (Fig.11, column 16 lines 64-67, column 17 lines 1-18 , Unit (1131+1135+RL)), wherein: an output of the LDO regulator is coupled to a first terminal of the transistor; an output of the clamping circuit is coupled to a gate terminal of the transistor; and an output of the amplifier is coupled to the gate terminal of the transistor (see Fig.11, column 16 lines 64-67, column 17 lines 1-18 where output of LDO regulator Vout coupled to first terminal of transistor 1111, output of clamp circuit coupled to gate of 1111 through RU resistor, output of amplifier 1101 coupled to gate of 1111); and a controller coupled to the memory device and configured to send one or more signals to the memory device to initiate operations (see Fig.2, 11, column 2 lines 29-63, column 16 lines 64-67, column 17 lines 1-18 , controller 122).
Even though Zhang et al. teach compensation circuit but silent exclusively about clamping circuit. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Zhang et al. where circuitry (1131+RL+1135) are working to clamp the output and would be called clamping circuit in order to stabilize the output voltage and to improve power supply rejection ratio including phase margin (see column 19 lines 63-67, column 20 lines 1-3).
Allowable Subject Matter
Claims 2-11, 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: wherein the clamping circuit comprises a first field-effect transistor (FET) and a second FET, a gate terminal of the first FET is coupled to the gate terminal of the transistor, the gate terminal of the first FET is coupled to a first terminal of the second FET, and a first terminal of the first FET is coupled to a gate terminal of the second FET.
Claim 13 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: wherein the clamping circuit comprises a first field-effect transistor (FET) and a second FET, a gate terminal of the first FET is coupled to the gate terminal of the transistor, the gate terminal of the first FET is coupled to a first terminal of the second FET, and a first terminal of the first FET is coupled to a gate terminal of the second FET.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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