DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 01/16/2025, 10/22/2025, 01/28/2026, and 05/28/2026 is/are being considered by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,175,739. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following.
Regarding claim 1, claims 1+2 of U.S. Patent No. 12,175,739 teaches the same limitations as highlighted below:
Claim 1 of the present application
Claims 1+2 of U.S. Patent No. 12,175,739
A processor comprising:
two or more parallel circuits [1]
to perform two or more portions of a non-maximum suppression (NMS) algorithm in parallel to remove one or more redundant bounding boxes corresponding to one or more objects within one or more digital images [2].
A processor comprising:
one or more circuits [1] to perform one or more parallel comparisons to select one of a plurality of bounding boxes based, at least in part, on an intersection over union (IoU) of only a subset of the plurality of bounding boxes having centers within a maximum radius of pixels [2] from a bounding box within the subset.
The processor of claim 1, wherein the one or more circuits are
to perform two or more portions of a non-maximum suppression (NMS) algorithm in parallel and: initiate a plurality of suppression processes to remove one or more redundant bounding boxes corresponding to one or more objects; and define an area that covers a subset of a plurality of bounding boxes for each suppression process.
Regarding difference [2], claims 1+2 of U.S. Patent No. 12,175,739 reciting a pixel implies the processing is done within at least one digital image as recited in claim 1. Regarding difference [1], one of ordinary skill in the art before the effective filing date of the invention would have found it obvious as a matter of simple substitution to replace the one or more circuits of the claims 1+2 of U.S. Patent No. 12,175,739 with two or more parallel circuits as recited in claim 1 to yield the predictable results of successfully analyzing the digital image.
Regarding claim 17, claims 17+18 of U.S. Patent No. 12,175,739 teaches the same limitations as highlighted below:
Claim 17 of the present application
Claims 17+18 of U.S. Patent No. 12,175,739
A method comprising:
identifying a plurality of bounding boxes
corresponding to one or more objects within one or more digital images [2]; and
performing two or more portions of a non-maximum suppression (NMS) algorithm in parallel to remove one or more redundant bounding boxes from the plurality of bounding boxes.
A method comprising:
identifying a plurality of bounding boxes; and performing one or more parallel comparisons to one of the plurality of bounding boxes based, at least in part, on an intersection over union (IoU) of only a subset of the plurality of bounding boxes having centers within a maximum radius of pixels [2] from a bounding box within the subset.
The method of claim 17, further comprising
performing two or more portions of a non-maximum suppression (NMS) algorithm in parallel by at least: initiating a plurality of parallel suppression processes to remove one or more redundant bounding boxes corresponding to one or more objects; and defining an area that covers a subset of a plurality of bounding boxes for each suppression process.
Regarding difference [2], claims 17+18 of U.S. Patent No. 12,175,739 reciting a pixel implies the processing is done within at least one digital image as recited in claim 17. The rest of claim 17 is anticipated by the highlighted language of claims 17+18 of U.S. Patent No. 12,175,739.
Claims 7 and 23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,275,739 in view of Mao et al, U.S. Patent No. 11,481,862.
Regarding claim 7, the claims of U.S. Patent No. 12,275,739 teach all the limitations of claim 1, but does not expressively wherein the two or more parallel circuits are to use a neural network to detect the one or more objects within the one or more digital images, and wherein the NMS algorithm is performed as a layer of the neural network.
However, Mao in a similar invention in the same field of endeavor teaches a system comprising two circuits (see Mao column 5, “The apparatuses, systems and methods described herein may be implemented by one or more computer programs executed by one or more processors”) for processing an image using an NMS algorithm (see claim 1) as taught in Oro wherein
the two or more circuits are to use a neural network to detect the one or more objects within the image, and wherein the NMS algorithm is performed as a layer of the neural network (see claim 1).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of including the NMS algorithm as a layer of a neural network as taught in Mao with the system taught in the claims of U.S. Patent No. 12,275,739, the motivation being to condense the network into fewer processing elements.
Regarding claim 23, the claims of U.S. Patent No. 12,275,739 teach all the limitations of claim 17, but does not expressively teach detecting, using a neural network, the one or more objects within the one or more digital images, wherein performing the two or more portions of the NMS algorithm in parallel is performed in a layer of the neural network.
However, Mao in a similar invention in the same field of endeavor teaches a system comprising two circuits (see Mao column 5, “The apparatuses, systems and methods described herein may be implemented by one or more computer programs executed by one or more processors”) for processing an image using an NMS algorithm (see claim 1) as taught in Oro wherein
the two or more circuits are to use a neural network to detect the one or more objects within the image, and wherein the NMS algorithm is performed as a layer of the neural network (see claim 1).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of including the NMS algorithm as a layer of a neural network as taught in Mao with the system taught in the claims of U.S. Patent No. 12,275,739, the motivation being to condense the network into fewer processing elements.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,275,739 in view of Xin et al, WO 2020/043057 A1 (citations will be to U.S. Publication No. 2020/0401829 which is an official translation of the reference).
Regarding claim 9, claims 1+2 of U.S. Patent No. 12,175,739 recite the same limitations as highlighted below:
Claim 9 of the present application
Claims 1+2 of U.S. Patent No. 12,175,739
A system comprising:
two or more circuits [1]
to perform two or more portions of a non-maximum suppression (NMS) algorithm in parallel to remove one or more redundant bounding boxes corresponding to one or more objects within one or more digital images [1]; and
one or more memories to store parameters associated with the NMS algorithm [2].
A processor comprising:
one or more circuits [1] to perform one or more parallel comparisons to select one of a plurality of bounding boxes based, at least in part, on an intersection over union (IoU) of only a subset of the plurality of bounding boxes having centers within a maximum radius of pixels [2] from a bounding box within the subset.
The processor of claim 1, wherein the one or more circuits are
to perform two or more portions of a non-maximum suppression (NMS) algorithm in parallel and: initiate a plurality of suppression processes to remove one or more redundant bounding boxes corresponding to one or more objects; and define an area that covers a subset of a plurality of bounding boxes for each suppression process.
Regarding difference [2], claims 1+2 of U.S. Patent No. 12,175,739 reciting a pixel implies the processing is done within at least one digital image as recited in claim 1. Regarding difference [1], one of ordinary skill in the art before the effective filing date of the invention would have found it obvious as a matter of simple substitution to replace the one or more circuits of the claims 1+2 of U.S. Patent No. 12,175,739 with two or more parallel circuits as recited in claim 1 to yield the predictable results of successfully analyzing the digital image.
Regarding difference [3], Xin in a similar invention in the same field of endeavor teaches a system with a circuit (see Xin paragraph [0119] referring to an FPGA unit) configured to perform an algorithm (see paragraph [0119]) on an image (see Abstract) as taught in claims 1+2 of U.S. Patent No. 12,175,739 further comprising
one or more memories to store parameters associated with the NMS algorithm (see paragraph [0119]).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of storing an algorithm for image processing in a memory as taught in Xin with the system taught in claims 1+2 of U.S. Patent No. 12,175,739, the motivation being to allow quick access and repeated access to the algorithm by a processor.
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,175,739 in view of Xin et al, WO 2020/043057 A1 (citations will be to U.S. Publication No. 2020/0401829 which is an official translation of the reference) and Mao et al, U.S. Patent No. 11,481,862.
Regarding claim 11, the claims of U.S. Patent No. 12,175,739 in view of Xin teaches all the limitations of claim 9, but does not expressively wherein the two or more parallel circuits are to use a neural network to detect the one or more objects within the one or more digital images, and wherein the NMS algorithm is performed as a layer of the neural network.
However, Mao in a similar invention in the same field of endeavor teaches a system comprising two circuits (see Mao column 5, “The apparatuses, systems and methods described herein may be implemented by one or more computer programs executed by one or more processors”) for processing an image using an NMS algorithm (see claim 1) as taught in Oro wherein
the two or more circuits are to use a neural network to detect the one or more objects within the image, and wherein the NMS algorithm is performed as a layer of the neural network (see claim 1).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of including the NMS algorithm as a layer of a neural network as taught in Mao with the system taught in the claims of U.S. Patent No. 12,275,739 in view of Xin, the motivation being to condense the network into fewer processing elements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oro et al, “Work-efficient parallel non-maximum suppression for embedded GPU architectures” (published in 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pages 1026-1030, March 2016).
Regarding claim 1, Oro teaches a processor comprising:
two or more parallel circuits to perform two or more portions of a non-maximum suppression (NMS) algorithm in parallel (see Oro section 1, final paragraph wherein the circuits are the GPUs) to remove one or more redundant bounding boxes corresponding to one or more objects (see Figure 2 and section 3, first two paragraphs) within one or more digital images (see column 3, fourth paragraph referring to pixels in the image of Figure 2, which implies the image is digital).
Regarding claim 2, Oro teaches all the limitations of claim 1, and further teaches wherein the two or more parallel circuits, to perform the two or more portions of the NMS algorithm in parallel, are to:
initiate a plurality of suppression processes to remove the one or more redundant bounding boxes corresponding to the one or more objects (see Oro section 3, first and second paragraphs); and
define an area that covers a subset of a plurality of bounding boxes for each suppression process (see Oro section 3, third paragraph).
Regarding claim 17, Oro teaches a method comprising:
identifying a plurality of bounding boxes corresponding to one or more objects (see Oro Figure 2 and section 3, first two paragraphs) within one or more digital images (see column 3, fourth paragraph referring to pixels in the image of Figure 2, which implies the image is digital);
performing two or more portions of a non-maximum suppression (NMS) algorithm (see section 1, final paragraph) in parallel to remove one or more redundant bounding boxes from the plurality of bounding boxes (see Figure 2 and section 3, first two paragraphs).
Regarding claim 18, Oro teaches all the limitations of claim 17, and further teaches wherein performing the two or more portions of the NMS algorithm in parallel comprises:
initiating a plurality of parallel suppression processes to remove the one or more redundant bounding boxes corresponding to the one or more object (see Oro section 3, first and second paragraphs); and
defining an area that covers a subset of a plurality of bounding boxes for each suppression process (see Oro section 3, third paragraph).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Oro et al, “Work-efficient parallel non-maximum suppression for embedded GPU architectures” (published in 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pages 1026-1030, March 2016) in view of Xin et al, WO 2020/043057 A1 (citations will be to U.S. Publication No. 2020/0401829 which is an official translation of the reference).
Regarding claim 9, Oro teaches a system comprising:
two or more parallel circuits to perform two or more portions of a non-maximum suppression (NMS) algorithm in parallel (see Oro section 1, final paragraph wherein the circuits are the GPUs) to remove one or more redundant bounding boxes corresponding to one or more objects (see Figure 2 and section 3, first two paragraphs) within one or more digital images (see column 3, fourth paragraph referring to pixels in the image of Figure 2, which implies the image is digital).
Oro does not expressively teach one or more memories to store parameters associated with the NMS algorithm.
However, Xin in a similar invention in the same field of endeavor teaches a system with a circuit (see Xin paragraph [0119] referring to an FPGA unit) configured to perform an algorithm (see paragraph [0119]) on an image (see Abstract) as taught in Oro further comprising
one or more memories to store parameters associated with the NMS algorithm (see paragraph [0119]).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of storing an algorithm for image processing in a memory as taught in Xin with the system taught in Oro, the motivation being to allow quick access and repeated access to the algorithm by a processor.
Regarding claim 10, Oro in view of Xin teaches all the limitations of claim 9, and further teaches wherein the two or more parallel circuits, to perform the two or more portions of the NMS algorithm in parallel, are to:
initiate a plurality of suppression processes to remove the one or more redundant bounding boxes corresponding to the one or more objects (see Oro section 3, first and second paragraphs); and
define an area that covers a subset of a plurality of bounding boxes for each suppression process (see Oro section 3, third paragraph).
Claims 7 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Oro et al, “Work-efficient parallel non-maximum suppression for embedded GPU architectures” (published in 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pages 1026-1030, March 2016) in view of Mao et al, U.S. Patent No. 11,481,862.
Regarding claim 7, Oro teaches all the limitations of claim 1, and further teaches wherein the two or more parallel circuits are to use a neural network to detect the one or more objects within the one or more digital images (see Oro section 2, first paragraph).
Oro does not expressively teach wherein the NMS algorithm is performed as a layer of the neural network.
However, Mao in a similar invention in the same field of endeavor teaches a system for processing an image using a neural network and performing an NMS algorithm (see Mao claim 1) as taught in Oro wherein
the NMS algorithm is performed as a layer of the neural network (see claim 1).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of including the NMS algorithm as a layer of a neural network as taught in Mao with the system taught in Oro, the motivation being to condense the network into fewer processing elements.
Regarding claim 23, Oro teaches all the limitations of claim 17, and further teaches detecting, using a neural network, the one or more objects within the one or more digital images (see Oro section 2, first paragraph).
Oro does not expressively teach wherein performing the two or more portions of the NMS algorithm in parallel is
However, Mao in a similar invention in the same field of endeavor teaches a method for processing an image using a neural network and performing an NMS algorithm (see Mao claim 1) as taught in Oro wherein
the NMS algorithm is performed as a layer of the neural network (see claim 1).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of including the NMS algorithm as a layer of a neural network as taught in Mao with the system taught in Oro, the motivation being to condense the network into fewer processing elements.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Oro et al, “Work-efficient parallel non-maximum suppression for embedded GPU architectures” (published in 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pages 1026-1030, March 2016) in view of Xin et al, WO 2020/043057 A1 (citations will be to U.S. Publication No. 2020/0401829 which is an official translation of the reference) and Mao et al, U.S. Patent No. 11,481,862.
Regarding claim 11, Oro in view of Xin teaches all the limitations of claim 9, and further teaches wherein the two or more parallel circuits are to use a neural network to detect the one or more objects within the one or more digital images (see Oro section 2, first paragraph).
Oro in view of Xin does not expressively teach wherein the NMS algorithm is performed as a layer of the neural network.
However, Mao in a similar invention in the same field of endeavor teaches a system for processing an image using a neural network and performing an NMS algorithm (see Mao claim 1) as taught in Oro in view of Xin wherein
the NMS algorithm is performed as a layer of the neural network (see claim 1).
One of ordinary skill in the art before the effective filing date of the invention would have found it obvious to combine the teaching of including the NMS algorithm as a layer of a neural network as taught in Mao with the system taught in Oro in view of Xin, the motivation being to condense the network into fewer processing elements.
Allowable Subject Matter
Claims 3-6, 8, 12-16, 19-21, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3, 8, 12, 16, 19, and 24, each of the claims teach analyzing candidate points on bounding boxes based on confidence thresholds and nearby points. Oro teaches a wholly different method of removing redundant bounding boxes (see Oro section 3). Furthermore, prior art NMS algorithms pick out the bounding box with the highest confidence as the “true” bounding box and then removes the others based on intersection over union (see Oro section 2, 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY L KRETZER whose telephone number is (571)272-5639. The examiner can normally be reached M-F 10:00-7:00 PM Pacific Time.
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/CASEY L KRETZER/Primary Examiner, Art Unit 2635
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