DETAILED ACTION
The instant application having Application No. 18/941,090 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-25, 27, 31-35, 37, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5-7, 9, 11-12, 15-16, 18, and 20 of U.S. Patent No. 12,164,447. Although the claims at issue are not identical, they are not patentably distinct from each other because both the instant application and the corresponding patent document disclose determining the state of a memory socket (whether it is occupied or unoccupied) before sending a signal to the corresponding memory sockets.
Instant Application 18/941,090
Patent Number US 12,164,447
Claim 21
A data buffer integrated circuit (IC) comprising: first and second control interfaces to be coupled respectively to first and second memory- module sockets via respective first and second control-signal paths;
a programmable register to store configuration information that indicates whether (i) only one of the first and second memory-module sockets is populated with a memory module or (ii) both the first and second memory-module sockets are populated with respective memory modules;
and control circuitry to: enable only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module;
and enable both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths if the configuration information indicates that both the first and second memory- module sockets are populated with respective memory modules.
Claim 1
A data buffer integrated circuit (IC) comprising: a primary data interface to be coupled to a memory control component; first and second secondary data interfaces to be coupled to first and second memory-module sockets, respectively;
a programmable register to store configuration information that indicates whether only one of the first and second memory-module sockets is populated with a memory module or if both the first and second memory-module sockets are populated with respective memory modules;
and multiplexing circuitry to convey data, in accordance with the configuration information, between either (i) the primary data interface and both of the first and second secondary data interfaces or (ii) exclusively between the primary data interface and a single one of the first and second secondary data interfaces.
Claim 5
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the data buffer IC further comprising circuitry to (i) enable oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enable oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.
Claim 22
wherein the control circuitry to enable only one of the first and second control interfaces to respond to control signals comprises circuitry to either (i) enable the first control interface to receive the control signals from a first registered clock driver IC disposed on a first memory module within the first memory-module socket or (ii) enable the second control interface to receive the control signals from a second registered clock driver IC disposed on a second memory module within the second memory-module socket.
Claim 5
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the data buffer IC further comprising circuitry to (i) enable oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enable oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.
Claim 23
wherein the control circuitry to enable both the first and second control interfaces to respond to control signals comprises circuitry to (i) enable the first control interface to receive a first subset of the control signals from a first registered clock driver IC disposed on a first memory module of the respective memory modules and (ii) enable the second control interface to receive a second subset of the control signals from a second registered clock driver IC disposed on a second memory module of the respective memory modules, the first and second memory modules populating the first and second memory-module sockets, respectively.
Claim 5
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the data buffer IC further comprising circuitry to (i) enable oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enable oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.
Claim 24
a primary data interface to be coupled to a memory control component;
first and second secondary data interfaces to be coupled respectively to the first and second memory-module sockets;
first timing calibration circuitry to execute a first timing calibration operation with respect to the first secondary data interface in response to the first subset of the control signals received via the first control interface;
and second timing calibration circuitry to execute a second timing calibration operation with respect to the second secondary data interface in response to the second subset of the control signals received via the second control interface.
Claim 5
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the data buffer IC further comprising circuitry to (i) enable oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enable oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.
Claim 25
wherein the first timing calibration circuitry to execute a first timing calibration operation with respect to the first secondary data interface comprises circuitry to adjust at least one of a transmit clock phase that controls data transmission timing via the secondary data interface or a receive clock phase that controls data reception timing via the first secondary data interface.
Claim 6
wherein the primary data interface comprises a synchronous signaling interface timed by a primary-interface timing signal that oscillates at the first frequency.
Claim 27
wherein the control circuitry to enable only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths comprises circuitry to detect that only one of the first and second memory-module sockets is populated with a memory module.
Claim 3
wherein the configuration information comprises a multi-bit value capable of representing, via respective patterns of constituent bits, at least the following three circumstances with respect to population of the first and second memory-module sockets: (i) the first memory-module socket is populated with a memory module, and the second memory-module socket is unpopulated;
(ii) the second memory-module socket is populated with a memory module, and the first memory-module socket is unpopulated; and (iii) the first memory-module socket is populated with a memory module, and the second memory-module socket is also populated with a memory module.
Claim 31
A method of operation within a data buffer integrated circuit (IC) having (i) first and second control interfaces coupled respectively to first and second memory-module sockets via respective control-signal paths, and (ii) a programmable register, the method comprising: storing configuration information within the programmable register that indicates whether (i) only one of the first and second memory-module sockets is populated with a memory module or (ii) both the first and second memory-module sockets are populated with respective memory modules;
enabling only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths if the configuration information indicates that only one of the first and second memory- module sockets is populated with a memory module;
and enabling both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules.
Claim 11
A method of operation within a data buffer integrated circuit (IC) having (i) a primary interface coupled to a memory control component, and (ii) first and second secondary data interfaces to be coupled to first and second memory-module sockets, respectively, the method comprising: storing, within a programmable register, configuration information that indicates whether only one of the first and second memory-module sockets is populated with a memory module or if both the first and second memory-module sockets are populated with respective memory modules;
and conveying data, in accordance with the configuration information, between either (i) the primary data interface and both of the first and second secondary data interfaces or (ii) exclusively between the primary data interface and a single one of the first and second secondary data interfaces.
Claim 12
wherein storing the configuration information within the programmable register comprises storing a multi-bit value that indicates (i) whether or not the first memory-module socket is populated with a memory module, and (ii) whether or not the second memory-module socket is populated with a memory module.
Claim 32
upon enabling only one of the first and second control interfaces to respond to control signals, receiving the control signals via either (i) the first control interface from a first registered clock driver IC disposed on a first memory module within the first memory-module socket or (ii) the second control interface from a second registered clock driver IC disposed on a second memory module within the second memory-module socket.
Claim 15
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the method further comprising (i) enabling oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enabling oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.
Claim 33
upon enabling both the first and second control interfaces to respond to control signals, receiving a first subset of the control signals via the first control interface from a first registered clock driver IC disposed on a first memory module of the respective memory modules, and receiving a second subset of the control signals via the second control interface from a second registered clock driver IC disposed on a second memory module of the respective memory modules, the first and second memory modules populating the first and second memory-module sockets, respectively.
Claim 15
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the method further comprising (i) enabling oscillation of the one or more timing signal instances at a first frequency within at least one of the first and second secondary data interfaces if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module, and (ii) enabling oscillation of the one or more timing signal instances at a second frequency within both of the first and second secondary data interfaces if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules and that both of the respective memory modules are to be accessed per memory access transaction, the second frequency being not more than half the first frequency.
Claim 9
wherein the first control interface comprises one or more signaling contacts to receive the control signals from the first registered clock driver chip via one or more counterpart signaling contacts within the first memory-module socket, and wherein the data buffer IC further comprises a second control interface having one or more signaling contacts to receive control signals from a second registered clock driver chip via one or more counterpart signaling contacts within the second memory-module socket.
Claim 34
wherein the data buffer IC includes (i) a primary data interface coupled to a memory control component and (ii) first and second secondary data interfaces coupled respectively to the first and second memory-module sockets, the method further comprising: executing a first timing calibration operation with respect to the first secondary data interface in response to the first subset of the control signals received via the first control interface;
and executing a second timing calibration operation with respect to the second secondary data interface in response to the second subset of the control signals received via the second control interface.
Claim 16
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the method further comprising disabling distribution of the one or more timing signal instances within one of the first and second secondary data interfaces in response to configuration information, stored within the programmable register, that indicates that only one of the first and second memory-module sockets is populated with a memory module.
Claim 35
wherein executing the first timing calibration operation with respect to the first secondary data interface comprises adjusting at least one of a transmit clock phase that controls data transmission timing via the secondary data interface or a receive clock phase that controls data reception timing via the first secondary data interface.
Claim 18
wherein receiving the control signals from the first registered clock driver chip comprises receiving first control signals output from the first registered clock driver chip to the first control interface via one or more signaling contacts within the first memory-module socket, the method further comprising receiving second control signals output from a second registered clock driver chip to a second control interface of the data buffer IC via one or more signaling contacts within the second memory-module socket.
Claim 37
wherein enabling only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths comprises detecting that only one of the first and second memory-module sockets is populated with a memory module.
Claim 16
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the method further comprising disabling distribution of the one or more timing signal instances within one of the first and second secondary data interfaces in response to configuration information, stored within the programmable register, that indicates that only one of the first and second memory-module sockets is populated with a memory module.
Claim 40
A data buffer integrated circuit comprising: first and second control interfaces to be coupled respectively to first and second memory- module sockets via respective first and second control-signal paths;
means for storing configuration information that indicates whether (i) only one of the first and second memory-module sockets is populated with a memory module or (ii) both the first and second memory-module sockets are populated with respective memory modules;
and means for enabling (i) only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths if the configuration information indicates that only one of the first and second memory- module sockets is populated with a memory module
and (ii) both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules.
Claim 20
A data buffer integrated circuit (IC) comprising: a primary data interface to be coupled to a memory control component; first and second secondary data interfaces to be coupled to first and second memory-module sockets, respectively;
means for storing configuration information that indicates whether only one of the first and second memory-module sockets is populated with a memory module or if both the first and second memory-module sockets are populated with respective memory modules;
and means for conveying data, in accordance with the configuration information, between either (i) the primary data interface and both of the first and second secondary data interfaces or (ii) exclusively between the primary data interface and a single one of the first and second secondary data interfaces.
Claim 7
wherein each of the first and second secondary data interfaces comprises a respective synchronous signaling interface timed by one or more timing signal instances, the data buffer IC further comprising circuitry to disable distribution of the one or more timing signal instances within one of the first and second secondary data interfaces in response to configuration information, stored within the programmable register, that indicates that only one of the first and second memory-module sockets is populated with a memory module.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 21-40 are rejected under 35 U.S.C. 103(a) as being unpatentable over Lee (Patent Number US 6,530,001 B1) in view of Rajan et al. (WO 2017/023508 A1).
As per claim 21, Lee discloses “A data buffer integrated circuit (IC) comprising: first and second control interfaces to be coupled respectively to first and second memory- module sockets via respective first and second control-signal paths (data/CLK bus and the clock buffer 130 to the memory banks 120-124; FIG. 3-4).” Lee discloses “a programmable register to store configuration information that indicates whether (i) only one of the first and second memory-module sockets is populated with a memory module or (ii) both the first and second memory-module sockets are populated with respective memory modules (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).”
However, Lee does not disclose “and control circuitry to: enable only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module” or “and enable both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths if the configuration information indicates that both the first and second memory- module sockets are populated with respective memory modules.”
Rajan et al. discloses “and control circuitry to: enable only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074) if the configuration information indicates that only one of the first and second memory-module sockets is populated with a memory module (Lee discloses the occupied/unoccupied determination of the state of a socket in [Column 4, lines 15-44]).” Rajan et al. discloses “and enable both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths (while in a wide mode the address-buffer component 115 sends signals to both secondary control interfaces 120A and 120B to steer data to the respective sets of memory components 105; Paragraphs 0029-0030) if the configuration information indicates that both the first and second memory- module sockets are populated with respective memory modules (Lee discloses the occupied/unoccupied determination of the state of a socket in [Column 4, lines 15-44]).”
Lee and Rajan et al. are analogous art in that they in the field of multiple memory device systems.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Lee and Rajan et al. to address loads on channels handling multiple memory modules [Paragraph 0003].
As per claim 22, Rajan et al. discloses “The data buffer IC of claim 21 (as disclosed by Lee and Rajan et al. above) wherein the control circuitry to enable only one of the first and second control interfaces to respond to control signals comprises circuitry to either (i) enable the first control interface to receive the control signals from a first registered clock driver IC disposed on a first memory module within the first memory-module socket or (ii) enable the second control interface to receive the control signals from a second registered clock driver IC disposed on a second memory module within the second memory-module socket (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 23, Rajan et al. discloses “The data buffer IC of claim 21 (as disclosed by Lee and Rajan et al. above) wherein the control circuitry to enable both the first and second control interfaces to respond to control signals comprises circuitry to (i) enable the first control interface to receive a first subset of the control signals from a first registered clock driver IC disposed on a first memory module of the respective memory modules and (ii) enable the second control interface to receive a second subset of the control signals from a second registered clock driver IC disposed on a second memory module of the respective memory modules, the first and second memory modules populating the first and second memory-module sockets, respectively (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 24, Lee discloses “The data buffer IC of claim 23 (as disclosed by Lee and Rajan et al. above) further comprising: a primary data interface to be coupled to a memory control component (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).” Lee discloses “first and second secondary data interfaces to be coupled respectively to the first and second memory-module sockets (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).” Lee discloses “first timing calibration circuitry to execute a first timing calibration operation with respect to the first secondary data interface in response to the first subset of the control signals received via the first control interface (see clock generator and register 128 in relation to DIMM 120-124; FIG. 3).” Lee discloses “and second timing calibration circuitry to execute a second timing calibration operation with respect to the second secondary data interface in response to the second subset of the control signals received via the second control interface (see clock generator and register 128 in relation to DIMM 120-124; FIG. 3).”
As per claim 25, Lee discloses “The data buffer IC of claim 24 (as disclosed by Lee and Rajan et al. above) wherein the first timing calibration circuitry to execute a first timing calibration operation with respect to the first secondary data interface comprises circuitry to adjust at least one of a transmit clock phase that controls data transmission timing via the secondary data interface (where the frequency of the memory clock signals is adjusted; Column 3, lines 15-22) or a receive clock phase that controls data reception timing via the first secondary data interface (connections to any one of the DIMM 120-124 through the clock generator 126 and the clock buffer 130 along with a connection to the Host to PCI Bridge Controller 108; FIG. 3).”
As per claim 26, Rajan et al. discloses “The data buffer IC of claim 21 (as disclosed by Lee and Rajan et al. above) wherein the control circuitry to enable only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths comprises circuitry to enable reception, via only one of the first and second control interfaces, of one or more signals indicating that a corresponding one of the first and second memory-module sockets is populated with a memory module (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 27, Lee discloses “The data buffer IC of claim 21 (as disclosed by Lee and Rajan et al. above) wherein the control circuitry to enable only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths comprises circuitry to detect that only one of the first and second memory-module sockets is populated with a memory module (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).”
As per claim 28, Rajan et al. discloses “The data buffer IC of claim 21 (as disclosed by Lee and Rajan et al. above) wherein the control circuitry to enable both the first and second control interfaces to respond to control signals comprises circuitry to: enable only a default one of the first and second control interfaces to respond to the control signals (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).” Rajan et al. discloses “receive, after enabling the default one of the first and second control interfaces, one or more configuration signals via the default one of the first and second control interfaces indicating that the other of the first and second control interfaces is to be enabled (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).” Rajan et al. discloses “and enable the other of the first and second control interfaces in response to the configuration signals (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 29, Lee discloses “The data buffer IC of claim 21 (as disclosed by Lee and Rajan et al. above) wherein the configuration information comprises a multi-bit value capable of representing, via respective patterns of constituent bits, at least the following three memory configurations:(i) the first memory-module socket is populated with a memory module and the second memory-module socket is unpopulated (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).” Lee discloses “(ii) the second memory-module socket is populated with a memory module and the first memory-module socket is unpopulated (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).” Lee discloses “and(iii) the first memory-module socket is populated with a memory module and the second memory-module socket is also populated with a memory module (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).”
As per claim 30, Rajan et al. discloses “The data buffer IC of claim 21 (as disclosed by Lee and Rajan et al. above) wherein, if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules, the configuration information additionally indicates whether (i) a single one of the respective memory modules is to be accessed exclusively per memory access transaction (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074) or (ii) both of the respective memory modules are to be accessed per memory access transaction (while in a wide mode the address-buffer component 115 sends signals to both secondary control interfaces 120A and 120B to steer data to the respective sets of memory components 105; Paragraphs 0029-0030).”
As per claim 31, Lee discloses “A method of operation within a data buffer integrated circuit (IC) having (i) first and second control interfaces coupled respectively to first and second memory-module sockets via respective control-signal paths, and (ii) a programmable register, the method comprising: storing configuration information within the programmable register that indicates whether (i) only one of the first and second memory-module sockets is populated with a memory module or (ii) both the first and second memory-module sockets are populated with respective memory modules (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).”
However, Lee does not disclose “enabling only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths if the configuration information indicates that only one of the first and second memory- module sockets is populated with a memory module” or “and enabling both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules.”
Rajan et al. discloses “enabling only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074) if the configuration information indicates that only one of the first and second memory- module sockets is populated with a memory module (Lee discloses the occupied/unoccupied determination of the state of a socket in [Column 4, lines 15-44]).” Rajan et al. discloses “and enabling both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths (while in a wide mode the address-buffer component 115 sends signals to both secondary control interfaces 120A and 120B to steer data to the respective sets of memory components 105; Paragraphs 0029-0030) if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules (Lee discloses the occupied/unoccupied determination of the state of a socket in [Column 4, lines 15-44]).”
Lee and Rajan et al. are analogous art in that they in the field of multiple memory device systems.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Lee and Rajan et al. to address loads on channels handling multiple memory modules [Paragraph 0003].
As per claim 32, Rajan et al. discloses “The method of claim 31 (as disclosed by Lee and Rajan et al. above) further comprising, upon enabling only one of the first and second control interfaces to respond to control signals, receiving the control signals via either (i) the first control interface from a first registered clock driver IC disposed on a first memory module within the first memory-module socket or (ii) the second control interface from a second registered clock driver IC disposed on a second memory module within the second memory-module socket (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 33, Rajan et al. discloses “The method of claim 31 (as disclosed by Lee and Rajan et al. above) further comprising, upon enabling both the first and second control interfaces to respond to control signals, receiving a first subset of the control signals via the first control interface from a first registered clock driver IC disposed on a first memory module of the respective memory modules, and receiving a second subset of the control signals via the second control interface from a second registered clock driver IC disposed on a second memory module of the respective memory modules, the first and second memory modules populating the first and second memory-module sockets, respectively (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 34, Lee discloses “The method of claim 33 (as disclosed by Lee and Rajan et al. above) wherein the data buffer IC includes (i) a primary data interface coupled to a memory control component and (ii) first and second secondary data interfaces coupled respectively to the first and second memory-module sockets note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44, the method further comprising: executing a first timing calibration operation with respect to the first secondary data interface in response to the first subset of the control signals received via the first control interface (see clock generator and register 128 in relation to DIMM 120-124; FIG. 3).” Lee discloses “and executing a second timing calibration operation with respect to the second secondary data interface in response to the second subset of the control signals received via the second control interface (see clock generator and register 128 in relation to DIMM 120-124; FIG. 3).”
As per claim 35, Lee discloses “The method of claim 34 (as disclosed by Lee and Rajan et al. above) wherein executing the first timing calibration operation with respect to the first secondary data interface comprises adjusting at least one of a transmit clock phase that controls data transmission timing via the secondary data interface (where the frequency of the memory clock signals is adjusted; Column 3, lines 15-22) or a receive clock phase that controls data reception timing via the first secondary data interface (connections to any one of the DIMM 120-124 through the clock generator 126 and the clock buffer 130 along with a connection to the Host to PCI Bridge Controller 108; FIG. 3).”
As per claim 36, Rajan et al. discloses “The method of claim 31 (as disclosed by Lee and Rajan et al. above) wherein enabling only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths comprises receiving, via only one of the first and second control interfaces, one or more signals indicating that a corresponding one of the first and second memory-module sockets is populated with a memory module (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 37, Rajan et al. discloses “The method of claim 31 (as disclosed by Lee and Rajan et al. above) wherein enabling only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths comprises detecting that only one of the first and second memory-module sockets is populated with a memory module (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).”
As per claim 38, Rajan et al. discloses “The method of claim 31 (as disclosed by Lee and Rajan et al. above) wherein enabling both the first and second control interfaces to respond to control signals comprises initially enabling only a default one of the first and second control interfaces to respond to control signals and then, after enabling the default one of the first and second control interfaces, (i) receiving one or more configuration signals via the default one of the first and second control interfaces indicating that the other of the first and second control interfaces is to be enabled and (ii) enabling the other of the first and second control interfaces in response to the configuration signals (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074).”
As per claim 39, Rajan et al. discloses “The method of claim 31 (as disclosed by Lee and Rajan et al. above) wherein, if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules, the configuration information additionally indicates whether (i) a single one of the respective memory modules is to be accessed exclusively per memory access transaction (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074) or (ii) both of the respective memory modules are to be accessed per memory access transaction (while in a wide mode the address-buffer component 115 sends signals to both secondary control interfaces 120A and 120B to steer data to the respective sets of memory components 105; Paragraphs 0029-0030).”
As per claim 40, Lee discloses “A data buffer integrated circuit comprising: first and second control interfaces to be coupled respectively to first and second memory- module sockets via respective first and second control-signal paths (data/CLK bus and the clock buffer 130 to the memory banks 120-124; FIG. 3-4).” Lee discloses “means for storing configuration information that indicates whether (i) only one of the first and second memory-module sockets is populated with a memory module or (ii) both the first and second memory-module sockets are populated with respective memory modules (note that there exists a plurality of memory sockets [Column 3, lines 40-45] where the system determines occupied/unoccupied conditions for each memory socket; Column 4, lines 15-44).”
However, Lee does not disclose “and means for enabling (i) only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths if the configuration information indicates that only one of the first and second memory- module sockets is populated with a memory module and (ii) both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules.”
Rajan et al. discloses “and means for enabling (i) only one of the first and second control interfaces to respond to control signals conveyed via a corresponding one of the first and second control-signal paths (while in the narrow mode, the address-buffer component 115 selects which of the individual secondary interfaces 120A or 120B is the target for sending data to the targeted DRAM dies of the DRAM components 105 and leaves the other secondary interface un-asserted; Paragraphs 0026 and 0074) if the configuration information indicates that only one of the first and second memory- module sockets is populated with a memory module (Lee discloses the occupied/unoccupied determination of the state of a socket in [Column 4, lines 15-44) and (ii) both the first and second control interfaces to respond to control signals conveyed respectively via the first and second control-signal paths (while in a wide mode the address-buffer component 115 sends signals to both secondary control interfaces 120A and 120B to steer data to the respective sets of memory components 105; Paragraphs 0029-0030) if the configuration information indicates that both the first and second memory-module sockets are populated with respective memory modules (Lee discloses the occupied/unoccupied determination of the state of a socket in [Column 4, lines 15-44]).”
Lee and Rajan et al. are analogous art in that they in the field of multiple memory device systems.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Lee and Rajan et al. to address loads on channels handling multiple memory modules [Paragraph 0003].
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated November 8, 2024, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
CLOSING COMMENTS
Conclusion
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/H.W.Y/Examiner, Art Unit 2181 January 9, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181