DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1) and Shirasaki (US 6,587,100 B1).
Claim 1, Kim (Fig. 1-4) discloses a driver (GIP; Fig. 1) including:
a plurality of stages (SL1-SLn/2 or SR1-SRn/2), at least one stage of the plurality of stages (Fig. 2) comprising:
an input circuit (M1 and M2; Fig. 3) which transfers an input signal (Gourt_Pre; Fig. 3) to a third node (Q; Fig. 3) in response to a clock signal (CLKA; Fig. 3);
an inverter circuit (M6 and M5; Fig. 3; INV1; Fig. 3) which inverts a voltage of the third node (Q; Fig. 4) and generate a voltage of a fourth node (QB; Fig. 3); and
wherein at least one of the inverter circuit (M6 and M5; Fig. 3; INV1; Fig. 3) includes different types of transistors (Paragraph [0051]; wherein discloses The first inverter INV1 includes a third NMOS M5 and a third PMOS M6).
Kim does not expressly disclose a first node control circuit which controls a voltage of a first node based on the voltage of the fourth node and a voltage of a second node;
a second node control circuit which controls the voltage of the second node based on the voltage of the third node and the voltage of the first node; and
wherein at least one of the first node control circuit and the second node control circuit includes different types of transistors.
Song (Fig. 1-23) discloses a first node control circuit (T213 and T211; Fig. 21) which controls a voltage of a first node (N211; Fig. 21) based on the voltage of the fourth node (IN(n); Fig. 21) and a voltage of a second node (Fig. 21; wherein figure shows a different node connected to the gate of transistor T211);
a second node control circuit (T214 and T212; Fig. 21) which controls the voltage of the second node (Fig. 21; wherein figure shows a different node connected between transistors T212 and T214) based on the voltage of the third node (INB(n); Fig. 21) and the voltage of the first node (N211; Fig. 21); and
wherein at least one of the first node control circuit (T213 and T211; Fig. 21) and the second node control circuit (T214 and T212; Fig. 21) includes different types of transistors (Paragraph [0162]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s driving circuit by applying a level shifter circuit, as taught by Song, so to use a driving circuit with a level shifter circuit for providing a display apparatus reducing a bezel width, forming a level shifter of a gate signal on a display panel or a flexible circuit substrate to overcome design constraints (i.e., the integral integrated circuit IIC cannot be located on the bezel area) in a structure having the reduced bezel width and generating the gate signal by a decoding method to reduce a power consumption (Paragraph [0006]).
Kim in view of Song does not expressly disclose an output circuit which generates an output signal based on the voltage of the first node and the voltage of the second node.
Shirasaki (Fig. 1-10(B)) discloses an output circuit (120 and 130; Fig. 1) which generates an output signal (OUT; Fig. 1) based on the voltage of the first node (N1; Fig. 1) and the voltage of the second node (N2; Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song’s driving circuit by applying switching circuits, as taught by Shirasaki, so to use a driving circuit with switching circuits for providing a driver circuit wherein pass-through current is not generated during the switching of the output voltage (Col. 2, Lines 2-5).
Claim 6, Shirasaki (Fig. 1-10(B)) discloses wherein the output circuit (120 and 130; Fig. 1) includes:
a first p-type metal-oxide-semiconductor transistor (121; Fig. 1; Col. 3, Lines 30-37; wherein discloses pMOS transistor 121) which outputs a high gate voltage (VU0; Fig. 1) as the output signal (OUT; Fig. 1) in response to the voltage of the second node (N1; Fig. 1); and
a second p-type metal-oxide-semiconductor transistor (131; Fig. 1; Col. 3, Lines 56-65; wherein discloses pMOS transistor 131) which outputs a first low gate voltage (GND; Fig. 1) as the output signal (OUT; Fig. 1) in response to the voltage of the first node (N2; Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song’s driving circuit by applying switching circuits, as taught by Shirasaki, so to use a driving circuit with switching circuits for providing a driver circuit wherein pass-through current is not generated during the switching of the output voltage (Col. 2, Lines 2-5).
Claim 7, Kim (Fig. 1-4) discloses wherein the input circuit (31; Fig. 3) includes:
a third p-type metal-oxide-semiconductor transistor (M2; Fig. 3: Paragraph [0041]; wherein discloses a PMOS transistor) which transfers the input signal (Gout_Pre; Fig. 3) to the third node (Q; Fig. 3) in response to the clock signal (CLKA; Fig. 3; wherein figure shows gate for transistor M2 connected to CLKA through an inverter circuit, therefore /CLKA (inverted clock)).
Claim 8, Kim (Fig. 1-4) discloses wherein the input circuit (31; Fig. 3) further includes:
a fourth n-type metal-oxide-semiconductor transistor (M1; Fig. 3) which transfers the input signal (Gout_Pre; Fig. 3) to the third node (Q; Fig. 3) in response to an inverted clock signal (CLKA; Fig. 3; wherein figure shows gate for transistor M1 connected to CLKA without being inverted, therefore CLKA being the inverted signal as compared to the signal received by gate for transistor M2).
Claim 9, Kim (Fig. 1-4) discloses wherein the inverter circuit (32; Fig. 3) includes:
a fourth p-type metal-oxide-semiconductor transistor (M6; Fig. 3; Paragraph [0041]; wherein discloses a PMOS transistor) which provides a high gate voltage (VGH; Fig. 3) to the fourth node (QB; Fig. 3) in response to the voltage of the third node (Q; Fig. 3); and
a first n-type metal-oxide-semiconductor transistor (M5; Fig 3) which provides a second low gate voltage (VGL; Fig. 3) to the fourth node (QB; Fig. 3) in response to the voltage of the third node (Q; Fig. 3).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1) and Shirasaki (US 6,587,100 B1) as applied to claim 1 above, and further in view of Maekawa (US 6,392,627 B1).
Claim 2, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the output signal has a first low gate voltage as a low voltage,
the fourth node has a second low gate voltage as a low voltage,
the first node has a third low gate voltage as a low voltage, and
at least two of the first, second and third low gate voltages have different voltage levels from each other.
Maekawa (Fig. 1-11) discloses wherein the output signal (Vout; Fig. 8 and 9) has a first low gate voltage as a low voltage (Vss1; Fig. 8 and 9),
the fourth node (Va; Fig. 8 and 9) has a second low gate voltage as a low voltage (Vss; Fig. 8 and 9),
the first node (Vc; Fig. 8 and 9) has a third low gate voltage as a low voltage (Vss1; Fig. 8 and 9), and
at least two of the first, second and third low gate voltages have different voltage levels from each other (Fig. 9; wherein figure shows Vout (1st) and Vc (3rd) having a low voltage of Vss1 and Va (2nd) having a low voltage of Vss).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying different low voltages, as taught by Maekawa, so to use a driving circuit with different low voltages for providing current flows through the level conversion circuit only during a certain duty period of an input pulse, the power consumption in the level conversion circuit is made small (Col. 9, Lines 49-55).
Claim 3, Maekawa (Fig. 1-11) discloses wherein the second low gate voltage (Vss; Fig. 8 and 9) is higher than (Col. 4, Lines 25-34; wherein discloses “a level conversion circuit 33 for shifting a low-voltage-side potential vss of output voltages of the CMOS inverters 31 and 32 to a potential vss1 that is lower than vss”) the first low gate voltage (Vss1; Fig. 8 and 9), and
the third low gate voltage (Vss1; Fig. 8; wherein figure shows transistor Qn15 provides a voltage of Vss1) is lower than or equal (Fig. 8; wherein figure shows them being equal) to the first low gate voltage (Vss1; Fig. 8; wherein figure shows transistors Qn13 and Qn14 both providing a voltage of Vss1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying different low voltages, as taught by Maekawa, so to use a driving circuit with different low voltages for providing current flows through the level conversion circuit only during a certain duty period of an input pulse, the power consumption in the level conversion circuit is made small (Col. 9, Lines 49-55).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1), Shirasaki (US 6,587,100 B1), and Maekawa (US 6,392,627 B1) as applied to claim 2 above, and further in view of Yu et al (US 2023/0097004 A1).
Claim 4, Kim in view of Song, Shirasaki, and Maekawa discloses the driver of claim 2.
Kim in view of Song, Shirasaki, and Maekawa does not expressly disclose wherein a low gate voltage of the clock signal is different from the first, second and third low gate voltages.
Yu (Fig. 1-15) discloses wherein a low gate voltage (VGL1; Fig. 5) of the clock signal (CLK; Fig. 5) is different from the first, second and third low gate voltages (VGL2 and VGL3; Fig. 7).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song, Shirasaki, and Maekawa’s driving circuit by applying a clock signal, as taught by Yu, so to use a driving circuit with a clock signal for providing a gate driving circuit capable of reducing a bezel area of a display panel and preventing a leakage current, and a display device including the same (Paragraph [0007]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1), and Shirasaki (US 6,587,100 B1) as applied to claim 1 above, and further in view of Maekawa (US 6,392,627 B1) and Yu et al (US 2023/0097004 A1).
Claim 5, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the input signal, the output signal, the first node, the second node, the third node and the fourth node have a same high gate voltage as a high voltage.
Maekawa (Fig. 1-11) discloses wherein the input signal (Vin; Fig. 8), the output signal (Vout; Fig. 8), the first node (Vc; Fig. 8), the second node (Fig. 8; node between Qp14 and Qn14; Fig. 8), the third node (Va; Fig. 8) and the fourth node (Vb; Fig. 8) have a same high gate voltage as a high voltage (Vdd; Fig. 8; wherein figure shows the same high voltage connected to entire circuit).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying different low voltages, as taught by Maekawa, so to use a driving circuit with different low voltages for providing current flows through the level conversion circuit only during a certain duty period of an input pulse, the power consumption in the level conversion circuit is made small (Col. 9, Lines 49-55).
Kim in view of Song, Shirasaki, and Maekawa does not expressly disclose wherein the clock signal have a same high gate voltage as a high voltage.
Yu (Fig. 1-15) discloses wherein the clock signal (CLK; Fig. 5) have a same high gate voltage as a high voltage (VGH; Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song, Shirasaki, and Maekawa’s driving circuit by applying a clock signal, as taught by Yu, so to use a driving circuit with a clock signal for providing a gate driving circuit capable of reducing a bezel area of a display panel and preventing a leakage current, and a display device including the same (Paragraph [0007]).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1) and Shirasaki (US 6,587,100 B1) as applied to claim 1 above, and further in view of Umezaki (US 2011/0285755 A1).
Claim 10, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the first node control circuit includes:
a fifth p-type metal-oxide-semiconductor transistor which provides a high gate voltage to the first node in response to the voltage of the fourth node; and
a second n-type metal-oxide-semiconductor transistor which provides a third low gate voltage to the first node in response to the voltage of the second node.
Umezaki (Fig. 7 and 8A) discloses wherein the first node control circuit (223 and 224; Fig. 8A) includes:
a fifth p-type metal-oxide-semiconductor transistor (223; Fig. 8A; Paragraph [0104]; wherein discloses a p-channel transistor) which provides a high gate voltage (211; Fig. 8A; VGH and 211; Fig. 7) to the first node (Fig. 8A; wherein figure shows a node between transistors 223 and 224) in response to the voltage of the fourth node (Fig. 8A; wherein figure shows transistor 223 connected to the output of inverter circuit); and
a second n-type metal-oxide-semiconductor transistor (224; Fig. 8A; Paragraph [0104]; wherein discloses a n-channel transistor) which provides a third low gate voltage (212; Fig. 8A; (VGL1 or VGL2) and 212; Fig. 7 and 8B) to the first node (Fig. 8A; wherein figure shows a node between transistors 223 and 224) in response to the voltage of the second node (Fig. 8A; wherein figure shows gate of transistor 224 connected to node between transistors 221 and 222).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying a level shifter circuit, as taught by Umezaki, so to use a driving circuit with a level shifter circuit for reducing a voltage applied to a transistor in an image retention period, to suppress deterioration of a transistor, to reduce the off-state current of a transistor, to increase the time during which an image can be maintained, and to provide a display device that can achieve any of these objects (Paragraph [0008]).
Claim 11, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the second node control circuit includes:
a sixth p-type metal-oxide-semiconductor transistor which provides a high gate voltage to the second node in response to the voltage of the third node; and
a third n-type metal-oxide-semiconductor transistor which provides a third low gate voltage to the second node in response to the voltage of the first node.
Umezaki (Fig. 7 and 8A) discloses wherein the second node control circuit (221 and 222; Fig. 8A) includes:
a sixth p-type metal-oxide-semiconductor transistor (221; Fig. 8A; Paragraph [0104]) which provides a high gate voltage (211; Fig. 8A; VGH and 221; Fig. 7) to the second node (Fig. 8A; wherein figure shows a node between transistors 221 and 222) in response to the voltage of the third node (Fig. 8A; wherein figure shows transistor 221 connected to the input of inverter circuit 225); and
a third n-type metal-oxide-semiconductor transistor (222; Fig. 8A; Paragraph [0104]) which provides a third low gate voltage (212; Fig. 8A; VGL1 or VGL2 and 212; Fig. 8B) to the second node (Fig. 8A; wherein figure shows a node between transistors 221 and 222) in response to the voltage of the first node (Fig. 8A; wherein figure shows gate of transistor 222 connected to node between transistors 223 and 224).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying a level shifter circuit, as taught by Umezaki, so to use a driving circuit with a level shifter circuit for reducing a voltage applied to a transistor in an image retention period, to suppress deterioration of a transistor, to reduce the off-state current of a transistor, to increase the time during which an image can be maintained, and to provide a display device that can achieve any of these objects (Paragraph [0008]).
Claims 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1) and Shirasaki (US 6,587,100 B1) as applied to claim 1 above, and further in view of Yang et al (US 2021/0012708 A1).
Claim 12, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the at least one stage further comprises:
a capacitor connected between the third node and a second low gate voltage line.
Yang (Fig, 1-25) discloses wherein the at least one stage (STA1-STA4; Fig. 5) further comprises:
a capacitor (C; Fig. 8) connected between the third node (N1; Fig. 8) and a second low gate voltage line (VLT; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying a capacitor, as taught by Yang, so to use a driving circuit with a capacitor for providing an emission signal driver for outputting an emission signal applied to a gate electrode of a light emitting control transistor of each pixel (Paragraph [0005]).
Claim 17, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the at least one stage further comprises:
a carry circuit which generates a carry signal based on the voltage of the fourth node, and
wherein the carry circuit includes:
a tenth p-type metal-oxide-semiconductor transistor which outputs a high gate voltage as the carry signal in response to the voltage of the fourth node; and
a fifth n-type metal-oxide-semiconductor transistor which outputs a second low gate voltage as the carry signal in response to the voltage of the fourth node.
Yang (Fig. 1-25) discloses wherein the at least one stage (ST1-ST4; Fig. 5) further comprises:
a carry circuit (INV3; Fig. 8) which generates a carry signal (COUT; Fig. 8) based on the voltage of the fourth node (N2; Fig. 8), and
wherein the carry circuit (INV3; Fig. 8) includes:
a tenth p-type metal-oxide-semiconductor transistor (T5; Fig. 8; Paragraph [0105]) which outputs a high gate voltage (VHT; Fig. 8) as the carry signal (COUT; Fig. 8) in response to the voltage of the fourth node (N2; Fig. 8); and
a fifth n-type metal-oxide-semiconductor transistor (T6; Fig. 8; Paragraph [0105]) which outputs a second low gate voltage (VLT; Fig. 8) as the carry signal (COUT; Fig. 8) in response to the voltage of the fourth node (N2; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying a carry signal, as taught by Yang, so to use a driving circuit with a carry signal for providing an emission signal driver for outputting an emission signal applied to a gate electrode of a light emitting control transistor of each pixel (Paragraph [0005]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1) and Shirasaki (US 6,587,100 B1) as applied to claim 1 above, and further in view of Toyoshima et al (US 2011/0157145 A1).
Claim 14, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the at least one stage further comprises:
a seventh p-type metal-oxide-semiconductor transistor including a gate which receives a third low gate voltage, and disposed at the first node to separate the first node into a fifth node and a sixth node; and
a capacitor connected between an output node at which the output signal is output and the sixth node.
Toyoshima (Fig. 1-43E) discloses wherein the at least one stage (10E; Fig. 12; 10; Fig. 28) further comprises:
a seventh p-type metal-oxide-semiconductor transistor (35; Fig. 12; Paragraph [0165]) including a gate which receives a third low gate voltage (PVSS1; Fig. 12), and disposed at the first node (Fig. 12; wherein figure shows a node between transistors 34 and 33) to separate the first node into a fifth node (B; Fig. 12) and a sixth node (C; Fig. 12); and
a capacitor (41; Fig. 12) connected between an output node (Out; Fig. 12) at which the output signal is output (Out; Fig. 12) and the sixth node (C; Fig. 12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying a bootstrap section, as taught by Toyoshima, so to use a driving circuit with a bootstrap section for providing a level shift circuit, a signal drive circuit, a display device, and an electronic device, each capable of achieving low-power consumption while achieving a proper or well-shaped internal waveform, a proper or well-shaped output waveform, or both (Paragraph [0009]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1) and Shirasaki (US 6,587,100 B1) as applied to claim 1 above, and further in view of Yu et al (US 2023/0097004 A1).
Claim 15, Kim in view of Song and Shirasaki discloses the driver of claim 1.
Kim in view of Song and Shirasaki does not expressly disclose wherein the first node control circuit includes a second n-type metal-oxide-semiconductor transistor which provides a third low gate voltage to the first node,
wherein the second node control circuit includes a third n-type metal-oxide-semiconductor transistor which provides the third low gate voltage to the second node, and
wherein each of the second and third n-type metal-oxide-semiconductor transistors includes a bottom gate which receives a fourth low gate voltage lower than the third low gate voltage.
Yu (Fig. 1-15) discloses wherein the first node control circuit (T7; Fig. 7) includes a second n-type metal-oxide-semiconductor transistor (T7; Fig. 7; Paragraph [0055]; wherein discloses a N-channel transistors) which provides a third low gate voltage (VGL2; Fig. 7) to the first node (31; Fig. 7),
wherein the second node control circuit (T3; Fig. 7) includes a third n-type metal-oxide-semiconductor transistor (T3; Fig. 7; Paragraph [0055]; wherein discloses a N-channel transistor) which provides the third low gate voltage (VGL2; Fig. 7) to the second node (n3; Fig. 7), and
wherein each of the second and third n-type metal-oxide-semiconductor transistors (T7 and T3; Fig. 5) includes a bottom gate which receives a fourth low gate voltage (VGL3; Fig. 7) lower than the third low gate voltage (VGL2; Fig. 7; Paragraph [0067]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song and Shirasaki’s driving circuit by applying a clock signal, as taught by Yu, so to use a driving circuit with a clock signal for providing a gate driving circuit capable of reducing a bezel area of a display panel and preventing a leakage current, and a display device including the same (Paragraph [0007]).
Claims 18 is are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Song et al (US 2022/0122511 A1), Shirasaki (US 6,587,100 B1), and Yang et al (US 2021/0012708 A1) as applied to claim 17 above, and further in view of Maekawa (US 6,392,627 B1) and Yu et al (US 2023/0097004 A1).
Claim 18, Kim in view of Song, Shirasaki, and Yang discloses the driver of claim 17.
Kim in view of Song, Shirasaki, and Yang does not expressly disclose wherein the second low gate voltage is higher than a first low gate voltage which is a low voltage of the output signal.
Maekawa (Fig. 1-11) discloses wherein the second low gate voltage (Vss; Fig. 8 and 9) is higher than a first low gate voltage (Vss1; Fig. 8 and 9) which is a low voltage of the output signal (Vout; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song, Shirasaki and Yang’s driving circuit by applying different low voltages, as taught by Maekawa, so to use a driving circuit with different low voltages for providing current flows through the level conversion circuit only during a certain duty period of an input pulse, the power consumption in the level conversion circuit is made small (Col. 9, Lines 49-55).
Kim in view of Song, Shirasaki, Yang, and Maekawa does not expressly disclose wherein a low gate voltage of the clock signal is higher than the first low gate voltage and lower than the second low gate voltage.
Yu (Fig. 1-15) discloses wherein a low gate voltage (VGL2; Fig. 9) of the clock signal (CLK_CAR; Fig. 9) is higher than the first low gate voltage (VGL3; Fig. 9) and lower than the second low gate voltage (VGL1; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Song, Shirasaki, Yang, and Maekawa’s driving circuit by applying a clock signal, as taught by Yu, so to use a driving circuit with a clock signal for providing a gate driving circuit capable of reducing a bezel area of a display panel and preventing a leakage current, and a display device including the same (Paragraph [0007]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0148392 A1) in view of Shirasaki (US 6,587,100 B1), Umezaki (US 2011/0285755 A1), and Yang et al (US 2021/0012708 A1).
Claim 19, Kim (Fig. 1-4) discloses a driver (GIP; Fig. 1) including a plurality of stages (SL1-SLn/2 or SR1-SRn/2; Fig. 2), at least one stage of the plurality of stages (SL1-SLn/2 or SR1-SRn/2; Fig. 2) comprising:
a third p-type metal-oxide-semiconductor transistor (M2; Fig. 3) including a gate that receives a clock signal (/CLKA; Fig. 3; wherein figure shows receiving an inverted clock signal), a first terminal that receives an input signal (Gout_Pre; Fig. 3), and a second terminal connected to a third node (Q; Fig. 3);
a fourth p-type metal-oxide-semiconductor transistor (M6; Fig. 3) including a gate connected to the third node (Q; Fig. 3), a first terminal connected to the high gate voltage line (VGH; Fig. 3), and a second terminal connected to a fourth node (QB; Fig. 3);
a first n-type metal-oxide-semiconductor (M5; Fig. 3) transistor including a gate connected to the third node (Q; Fig. 3), a first terminal connected to the fourth node (QB; Fig. 3), and a second terminal connected to a second low gate voltage line (VGL; Fig. 3).
Kim does not expressly disclose a first p-type metal-oxide-semiconductor transistor including a gate connected to a second node, a first terminal connected to a high gate voltage line, and a second terminal connected to an output node;
a second p-type metal-oxide-semiconductor transistor including a gate connected to a first node, a first terminal connected to the output node, and a second terminal connected to a first low gate voltage line.
Shirasaki (Fig. 1-10(B)) discloses a first p-type metal-oxide-semiconductor transistor (121; Fig. 1; Col. 3, Lines 30-37; wherein discloses pMOS transistor 121) including a gate connected to a second node (N1; Fig. 1), a first terminal connected to a high gate voltage line (VU0; Fig. 1), and a second terminal connected to an output node (OUT; Fig. 1);
a second p-type metal-oxide-semiconductor transistor (131; Fig. 1; Col. 3, Lines 56-65; wherein discloses pMOS transistor 131) including a gate connected to a first node (N2; Fig. 1), a first terminal connected to the output node (OUT; Fig. 1), and a second terminal connected to a first low gate voltage line (GND; Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s driving circuit by applying switching circuits, as taught by Shirasaki, so to use a driving circuit with switching circuits for providing a driver circuit wherein pass-through current is not generated during the switching of the output voltage (Col. 2, Lines 2-5).
Kim in view of Shirasaki does not expressly disclose a fifth p-type metal-oxide-semiconductor transistor including a gate connected to the fourth node, a first terminal connected to the high gate voltage line, and a second terminal connected to the first node;
a second n-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the first node, and a second terminal connected to a third low gate voltage line;
a sixth p-type metal-oxide-semiconductor transistor including a gate connected to the third node, a first terminal connected to the high gate voltage line, and a second terminal connected to the second node;
a third n-type metal-oxide-semiconductor transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third low gate voltage line.
Umezaki (Fig. 7 and 8A) discloses a fifth p-type metal-oxide-semiconductor transistor (223; Fig. 8A; Paragraph [0104]; wherein discloses a p-channel transistor) including a gate connected to the fourth node (Fig. 8A; wherein figure shows transistor 223 connected to the output of inverter circuit), a first terminal connected to the high gate voltage line (211; Fig. 8A; VGH and 211; Fig. 7), and a second terminal connected to the first node (Fig. 8A; wherein figure shows a node between transistors 223 and 224);
a second n-type metal-oxide-semiconductor transistor (224; Fig. 8A; Paragraph [0104]; wherein discloses a n-channel transistor) including a gate connected to the second node (Fig. 8A; wherein figure shows gate of transistor 224 connected to node between transistors 221 and 222), a first terminal connected to the first node (Fig. 8A; wherein figure shows a node between transistors 223 and 224), and a second terminal connected to a third low gate voltage line (212; Fig. 8A; (VGL1 or VGL2) and 212; Fig. 7 and 8B);
a sixth p-type metal-oxide-semiconductor transistor (221; Fig. 8A; Paragraph [0104]) including a gate connected to the third node (Fig. 8A; wherein figure shows transistor 221 connected to the input of inverter circuit 225), a first terminal connected to the high gate voltage line (211; Fig. 8A; VGH and 221; Fig. 7), and a second terminal connected to the second node (Fig. 8A; wherein figure shows a node between transistors 221 and 222);
a third n-type metal-oxide-semiconductor transistor (222; Fig. 8A; Paragraph [0104]) including a gate connected to the first node (Fig. 8A; wherein figure shows gate of transistor 222 connected to node between transistors 223 and 224), a first terminal connected to the second node (Fig. 8A; wherein figure shows a node between transistors 221 and 222), and a second terminal connected to the third low gate voltage line (212; Fig. 8A; VGL1 or VGL2 and 212; Fig. 8B).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Shirasaki’s driving circuit by applying a level shifter circuit, as taught by Umezaki, so to use a driving circuit with a level shifter circuit for reducing a voltage applied to a transistor in an image retention period, to suppress deterioration of a transistor, to reduce the off-state current of a transistor, to increase the time during which an image can be maintained, and to provide a display device that can achieve any of these objects (Paragraph [0008]).
Kim in view of Shirasaki and Umezaki does not expressly disclose a capacitor connected between the third node and the second low gate voltage line.
Yang (Fig, 1-25) discloses a capacitor (C; Fig. 8) connected between the third node (N1; Fig. 8) and a second low gate voltage line (VLT; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Shirasaki and Umezaki’s driving circuit by applying a capacitor, as taught by Yang, so to use a driving circuit with a capacitor for providing an emission signal driver for outputting an emission signal applied to a gate electrode of a light emitting control transistor of each pixel (Paragraph [0005]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2021/0012708 A1) in view of Kim (US 2017/0148392 A1), Song et al (US 2022/0122511 A1), and Shirasaki (US 6,587,100 B1).
Claim 20, Yang (Fig. 1-25) discloses a display device (10; Fig. 1) comprising:
a display panel (100; Fig. 3) including a plurality of pixels (SP; Fig. 3);
a data driver (220; Fig. 3) which provides data signals (DL; Fig. 3) to the plurality of pixels (SP; Fig. 3);
a gate driver (410; Fig. 3) which provides gate signals (SL; Fig. 3) to the plurality of pixels (SP; Fig. 3);
an emission driver (420; Fig. 3) which provides emission signals (EL; Fig. 3) to the plurality of pixels (SP; Fig. 3); and
a controller (210; Fig. 3) which controls (DCS, SCS, and ECS; Fig. 3) the data driver (220; Fig. 3), the gate driver (410; Fig. 3) and the emission driver 420; Fig. 3), at least one of the gate driver and the emission driver (420; Fig. 5; STA; Fig. 6) including:
a plurality of stages (STA1-STA4; Fig. 5).
Yang does not expressly disclose at least one stage of the plurality of stages comprising:
an input circuit which transfers an input signal to a third node in response to a clock signal;
an inverter circuit which inverts a voltage of the third node and generates a voltage of a fourth node;
wherein at least one of the inverter circuit, the first node control circuit and the second node control circuit includes different types of transistors.
Kim (Fig. 1-4) discloses at least one stage of the plurality of stages (Fig. 3) comprising:
an input circuit (M1 and M2; Fig. 3) which transfers an input signal (Gourt_Pre; Fig. 3) to a third node (Q; Fig. 3) in response to a clock signal (CLKA; Fig. 3);
an inverter circuit (M6 and M5; Fig. 3; INV1; Fig. 3) which inverts a voltage of the third node (Q; Fig. 4) and generate a voltage of a fourth node (QB; Fig. 3); and
wherein at least one of the inverter circuit (M6 and M5; Fig. 3; INV1; Fig. 3) includes different types of transistors (Paragraph [0051]; wherein discloses The first inverter INV1 includes a third NMOS M5 and a third PMOS M6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang’s driving circuit by applying a scan driving circuit, as taught by Kim, so to use a driving circuit with a scan driving circuit for providing a display device with a narrow bezel (Paragraph [0014]).
Yang in view of Kim does not expressly disclose a first node control circuit which controls a voltage of a first node based on the voltage of the fourth node and a voltage of a second node;
a second node control circuit which controls the voltage of the second node based on the voltage of the third node and the voltage of the first node; and
wherein at least one of the first node control circuit and the second node control circuit includes different types of transistors.
Song (Fig. 1-23) discloses a first node control circuit (T213 and T211; Fig. 21) which controls a voltage of a first node (N211; Fig. 21) based on the voltage of the fourth node (IN(n); Fig. 21) and a voltage of a second node (Fig. 21; wherein figure shows a different node connected to the gate of transistor T211);
a second node control circuit (T214 and T212; Fig. 21) which controls the voltage of the second node (Fig. 21; wherein figure shows a different node connected between transistors T212 and T214) based on the voltage of the third node (INB(n); Fig. 21) and the voltage of the first node (N211; Fig. 21); and
wherein at least one of the first node control circuit (T213 and T211; Fig. 21) and the second node control circuit (T214 and T212; Fig. 21) includes different types of transistors (Paragraph [0162]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Kim’s driving circuit by applying a level shifter circuit, as taught by Song, so to use a driving circuit with a level shifter circuit for providing a display apparatus reducing a bezel width, forming a level shifter of a gate signal on a display panel or a flexible circuit substrate to overcome design constraints (i.e., the integral integrated circuit IIC cannot be located on the bezel area) in a structure having the reduced bezel width and generating the gate signal by a decoding method to reduce a power consumption (Paragraph [0006]).
Yang in view of Kim and Song does not expressly disclose an output circuit which generates an output signal based on the voltage of the first node and the voltage of the second node.
Shirasaki (Fig. 1-10(B)) discloses an output circuit (120 and 130; Fig. 1) which generates an output signal (OUT; Fig. 1) based on the voltage of the first node (N1; Fig. 1) and the voltage of the second node (N2; Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Kim and Song’s driving circuit by applying switching circuits, as taught by Shirasaki, so to use a driving circuit with switching circuits for providing a driver circuit wherein pass-through current is not generated during the switching of the output voltage (Col. 2, Lines 2-5).
Allowable Subject Matter
Claims 13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 13, the claim is direct to Applicant’s figure 13 which shows the embodiment in which the capacitor CFQ’ is connected between nodes FQ and Q1. The Examiner believes the cited prior art references do not teach the claimed limitations.
With respect to claim 16, the claims are direct to Applicant’s figure 12, which shows the additionally claimed limitation with respect to the transistors PT8, PT9, and capacitors CC1 and CC2. The Examiner believes the cited prior art references do not teach the claimed limitations.
Conclusion
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/Adam J Snyder/Primary Examiner, Art Unit 2623 02/02/2026