DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 8 November 2024. In view of this communication, claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6 and 17-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Grober (US 10531577 B1), hereinafter referred to as Grober.
Regarding claim 1, Grober teaches a circuit board comprising:
an insulating structure (102) having a through hole (108) (Fig. 1 and column 17, lines 30-35 and 50-55: through hole 108 formed through insulating structure 102) passing through an upper surface (104) and a lower surface (106) opposite to the upper surface (104) (Fig. 1 and column 18, lines 5-10: main surfaces 104, 106); and
a through electrode (153) including a through portion disposed in the through hole (108) of the insulating structure (102) and a protruding portion disposed on the through portion and protruding on the upper surface of the insulating structure (102) (Fig. 1 and column 19, line 60 through column 20, line 10: first plating layer 153 formed on the sidewall 112 of through hole 108 and on the upper surface 104 of the insulating layer structure 102), and
wherein a side surface of the protruding portion has a step (Fig. 1 and column 20, lines 1-15: the plating layer 153 has a step formed at the corner of sidewall 112 and upper surface 104).
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Regarding claim 2, Grober teaches the circuit board of claim 1, wherein the protruding portion includes a first metal layer (153) disposed on the insulating structure (102); and a second metal layer (110) disposed on the first metal layer (153) (Fig. 3 and column 20, lines 50-60: bridge structure 110 disposed in the through hole 108 and covering the first metal layer 153 on the sides and upper and lower surfaces of first metal layer 153).
Regarding claim 3, Grober teaches the circuit board of claim 2, wherein a side edge of the first metal layer (153) and a side edge of the second metal layer (110) have the step (Fig. 3 and column 20, lines 50-60: bridge structure 110 disposed on first metal layer 153 such that it also has a step corresponding to the corner formed at sidewall 112 and upper surface 104 of the insulating layer 102).
Regarding claim 4, Grober teaches the circuit board of claim 2, wherein the insulating structure (102) includes an outer surface connecting the upper surface (104) and the lower surface (106), and wherein the side edge of the first metal layer (153) is closer to the outer surface than is the side edge of the second metal layer (110) (it is inherent that the board of Grober has an outer surface, so the side surface of the first metal layer 153 would inherently be closer to that outer surface than the side surface of bridge 110 could be).
Regarding claim 5, Grober teaches the circuit board of claim 2, wherein the protruding portion includes an additional metal layer (148) disposed on the second metal layer (110), and wherein a side edge of the additional metal layer (148) and the side edge of the first metal layer (153) have a step (Fig. 3 and column 21, lines 10-15: bulk structure 148 disposed on bridge 110 such that it also has a step corresponding to the corner formed at sidewall 112 and upper surface 104 of the insulating layer 102).
Regarding claim 6, Grober teaches the circuit board of claim 5, wherein the side edge of the second metal layer (110) and the side edge of the additional metal layer (148) are located on a same plane (Fig. 3 and column 23, lines 25-40: the side edges of layers 110 and 148 are vertically aligned).
Regarding claim 17, Grober teaches a circuit board comprising: circuit board (100) comprising: an insulating structure (102); and an upper wiring part (153) disposed on an upper surface (104) of the insulating structure (102) (Fig. 1 and column 19, line 60 through column 20, line 10: first plating layer 153 formed on the sidewall 112 of through hole 108 and on the upper surface 104 of the insulating layer structure 102), wherein a side surface of the upper wiring part (153) has a step (Fig. 1 and column 20, lines 1-15: the plating layer 153 has a step formed at the corner of sidewall 112 and upper surface 104).
Regarding claim 18, Grober teaches the circuit board of claim 17, wherein the upper wiring part (153) includes a first metal layer (153) disposed on the insulating structure (102); and a second metal layer (110) disposed on the first metal layer (153), and wherein the step is a step between a side edge of the first metal layer (153) and a side edge of the second metal layer (110) ) (Fig. 3 and column 20, lines 50-60: bridge structure 110 disposed in the through hole 108 and covering the first metal layer 153 on the sides and upper and lower surfaces of first metal layer 153.
Regarding claim 19, Grober teaches the circuit board of claim 18, comprising: a through electrode (110) passing through the upper surface (104) and the lower surface (106) of the insulating structure (102) and connected to the upper wiring part (110, 153), and wherein the side edge of the first metal layer (153) is spaced farther from the through electrode (110) along a horizontal direction than the side edge of the second metal layer (110) (Fig. 3: the side edge of the upper portion of metal layer 153 is farther from the center of the bridge 110 than the side surface of the bridge 110).
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kajihara (US 20140338965 A1), hereinafter referred to as Kajihara.
Regarding claim 1, Kajihara teaches a circuit board comprising:
an insulating structure (1) having a through hole (4) passing through an upper surface (F) and a lower surface (S) opposite to the upper surface (F) (paragraph 15: penetrating hole 4 in insulating layer 1); and
a through electrode (5) including a through portion (5) disposed in the through hole (4) of the insulating structure (1) and a protruding portion (2) disposed on the through portion (5) and protruding on the upper surface (F) of the insulating structure (1) (paragraph 15: first conductive layer 2 formed on first surface F of the insulating substrate 1 and connected to through-hole conductor 5, which is formed in penetrating hole 4), and
wherein a side surface of the protruding portion (2) has a step (Fig. 2 and paragraph 15: the first conductive layer 2 and the through-hole conductor 5 form a step at the intersection of the sidewall 4 and first surface F).
Regarding claim 2, Kajihara teaches the circuit board of claim 1, wherein the protruding portion (2) includes a first metal layer (9) disposed on the insulating structure (1); and a second metal layer (9) disposed on the first metal layer (9) (paragraph 18: 14 layers of electrolytic plated film 9 are formed on the wall of the through hole 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7-9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grober in view of Lee et al. (US 20200163228 A1), hereinafter referred to as Lee et al.
Regarding claim 7, Grober teaches the circuit board of claim 2, but does not teach that the insulating structure includes a first insulating layer; and a second insulating layer disposed on the first insulating layer, and wherein the through portion integrally passes through from a lower surface of the first insulating layer to an upper surface of the second insulating layer.
Lee et al. does teach that the insulating structure may include a first insulating layer (110); and a second insulating layer (120) disposed on the first insulating layer (110), and wherein the through portion integrally passes through from a lower surface of the first insulating layer (110) to an upper surface of the second insulating layer (120) (Lee et al. Fig. 4 and paragraphs 85-86: the through electrode 700 extends, via the pads 600 and 800, from an upper surface of the second insulating layer 120 to a lower surface of the first insulating layer 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating structure of Grober with a first and second insulating layer, such that the through portion passes from a lower surface of the first to an upper surface of the second, as taught by Lee et al. because it has been held to be within the general skill of a worker in the art to make singular part as plural parts as a matter of obvious engineering choice. Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. Of Int. 1969).
Regarding claim 8, Grober teaches the circuit board of claim 7, wherein the through portion includes a third metal layer (153) extending from the first metal layer (153) and disposed on an inner wall (112) of the through hole (108) (Figs. 3-4 and column 23, lines 1-20: the portion of first metal layer 153 beneath line 190 corresponds to the third metal layer); and a fourth metal layer (110) extending from the second metal layer (110) and disposed on the third metal layer (153) (Figs. 3-4 and column 23, lines 1-20: the portion of bridge 110 beneath line 190 corresponds to the fourth metal layer).
Regarding claim 9, Grober teaches the circuit board of claim 8, wherein the first metal layer (153) and the third metal layer (153) are formed integrally, and the second metal layer (110) and the fourth metal layer (110) are formed integrally (Fig. 3, column 19, lines 60-65, and column 20, lines 50-60: plating layers 110 and 153 are formed integrally from the upper surface 104 to the lower surface 106 of the insulating layer 102).
Regarding claim 20, Grober teaches the circuit board of claim 19, but does not teach that the insulating structure includes a plurality of insulating layers stacked along a vertical direction, and wherein the through electrode integrally passes through the plurality of insulating layers.
Lee et al. does teach that the insulating structure includes a plurality of insulating layers (110, 120) stacked along a vertical direction, and wherein the through electrode integrally passes through the plurality of insulating layers (110, 120) (Lee et al. Fig. 4 and paragraphs 85-86: the through electrode 700 extends, via the pads 600 and 800, from an upper surface of the second insulating layer 120 to a lower surface of the first insulating layer 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating structure of Grober with a a plurality of insulating layers, such that the through passes integrally through them, as taught by Lee et al. because it has been held to be within the general skill of a worker in the art to make singular part as plural parts as a matter of obvious engineering choice. Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. Of Int. 1969).
Claim(s) 7-8 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajihara in view of Lee et al.
Regarding claim 7, Kajihara teaches the circuit board of claim 2, but does not teach that the insulating structure includes a first insulating layer; and a second insulating layer disposed on the first insulating layer, and wherein the through portion integrally passes through from a lower surface of the first insulating layer to an upper surface of the second insulating layer.
Lee et al. does teach that the insulating structure may include a first insulating layer (110); and a second insulating layer (120) disposed on the first insulating layer (110), and wherein the through portion integrally passes through from a lower surface of the first insulating layer (110) to an upper surface of the second insulating layer (120) (Lee et al. Fig. 4 and paragraphs 85-86: the through electrode 700 extends, via the pads 600 and 800, from an upper surface of the second insulating layer 120 to a lower surface of the first insulating layer 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating structure of Kajihara with a first and second insulating layer, such that the through portion passes from a lower surface of the first to an upper surface of the second, as taught by Lee et al. because it has been held to be within the general skill of a worker in the art to make singular part as plural parts as a matter of obvious engineering choice. Nerwin v. Erlichman, 168 USPQ 177, 179 (PTO Bd. Of Int. 1969).
Regarding claim 8, Kajihara teaches the circuit board of claim 7, wherein the through portion includes a third metal layer (9) extending from the first metal layer (9) and disposed on an inner wall of the through hole (4); and a fourth metal layer (9) extending from the second metal layer (9) and disposed on the third metal layer (9) (the third and fourth metal layers are taken as the portions of electrolytic plated film 9 beneath the midpoint of the through hole 4, which coincides with stress line B shown in Figs. 3-4 of Kajihara).
Regarding claim 10, Kajihara teaches the circuit board of claim 8, wherein the third metal layer (9) includes a concave surface in contact with the fourth metal layer (9), and wherein the fourth metal (9) layer includes a convex surface in contact with the concave surface of the third metal layer (9) (the expanded view shown in Fig. 4 of Kajihara and described in paragraph 22 shows the abutting convex and concave surfaces between each electrolytic plating layer 9).
Regarding claim 11, Kajihara teaches the circuit board of claim 10, wherein a lowermost end of the concave surface or a lowermost end of the convex surface is positioned lower than an interface between the first insulating layer and the second insulating layer (referring to Fig. 4 and paragraph 22 of Kajihara, the lowermost points of the interfaces between electrolytic plating layers 9 are beneath the midpoint of the insulating layer 1 of Kajihara, placing them well below the point that Lee et al. teaches that the insulating layers would be split).
Regarding claim 12, Kajihara teaches the circuit board of claim 7, wherein the through portion (5) further includes a fifth metal layer (11) disposed on the fourth metal layer (9), wherein the fourth metal layer (9) includes a concave surface in contact with the fifth metal layer (11), and wherein the fifth metal layer (11) includes a convex surface in contact with the concave surface of the fourth metal layer (9) (Fig. 2 and paragraph 16: filled electrolytic plating layer 12 is formed on an electrolytic plating layer 9, resulting in a concave surface on layer 9 and a corresponding convex surface on layer 12).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grober in view of Lee et al., in further view of Oh et al. (US 20150351219 A1), hereinafter referred to as Oh et al.
Regarding claim 13, Grober in view of Lee et al. teaches the circuit board of claim 7, but does not teach a first via electrode passing through at least a portion of the first insulating layer along a vertical direction; and a second via electrode passing through at least a portion of the second insulating layer along the vertical direction, and wherein a width of the through portion of the through electrode in a horizontal direction is greater than a width of the first via electrode or the second via electrode in the horizontal direction.
Oh et al. teaches a first via electrode (105) passing through at least a portion of the first insulating layer along a vertical direction; and a second via electrode (105) passing through at least a portion of the second insulating layer along the vertical direction, and wherein a width of the through portion of the through electrode (103) in a horizontal direction is greater than a width of the first via electrode (105) or the second via electrode (105) in the horizontal direction (Oh et al. Fig. 1 and paragraph 49: the diameters of vias 103 are larger than the diameters of vias 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a first and second via electrode as taught by Oh et al. such that the width of the through portion of Grober is greater than the width of the via electrodes of Oh et al. because forming a large through electrode enables it to serve a heat radiation function in addition to transmitting signals (Oh et al. paragraph 49).
Regarding claim 14, Grober in view of Oh et al. teaches the circuit board of claim 13, wherein the first via electrode (105) and the second via electrode (105) overlap along the vertical direction (Oh et al. Figs. 1 and 9-11).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grober in view of Lee et al. and Oh et al., in further view of Oh et al. (US 20140174793 A1), hereinafter referred to as Oh et al. (2014).
Regarding claim 15, Grober in view of Lee et al. and Oh et al. teaches the circuit board of claim 13, but does not teach that the through portion of the through electrode, the first via electrode, and the second via electrode each has a slope whose width in the horizontal direction gradually decreases toward the lower surface of the insulating structure.
Oh et al. (2014) does teach that the through portion of the through electrode, the first via electrode, and the second via electrode each has a slope whose width in the horizontal direction gradually decreases toward the lower surface of the insulating structure (Oh et al. (2014) Fig. 1 and paragraphs 19 and 45: the diameters of the vias may narrow from an upper portion to a lower portion thereof).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the through electrode, first via electrode, and second via electrode of Grober in view of Lee et al. and Oh et al. to have a slope gradually decreasing toward a lower surface of the insulating structure as taught by Oh et al. (2014) because a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1976).
Regarding claim 16, Grober in view of Lee et al. and Oh et al., in further view of Oh et al. (2014) teaches the circuit board of claim 15, wherein the slope of the first via electrode and the slope of the second via electrode overlap along the horizontal direction with the slope of the through portion (in the via electrode structure taught by Grober in view of Lee et al. and Oh et al. as modified by Oh et al. (2014), above, the sloped portions of the via electrodes and through portions overlap with one another).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jeong et al. (US 20260068048 A1)
Chang et al. (US 12557666 B2)
Ko et al. (US 20230354520 A1)
Tanaka et al. (US 20230123522 A1)
Mun et al. (US 20220030713 A1)
Tanaka (US 20200168541 A1)
Kajihara et al. (US 20150034378 A1)
Hara et al. (US 20140097013 A1)
Kawai et al. (US 20110120762 A1)
Brunner et al. (US 20110011746 A1)
Balents et al. (US 6033764 A)
Chang et al. (US 5266446 A)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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