Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 15 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 365(c) is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/08/2024 and 05/19/2025 were received. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract of the disclosure is objected to because:
The abstract is a single sentence that appear to be a recitation of claim 1. The abstract of the disclosure fails to be in a narrative form.
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “that can be divided”. Specifically, whether the first check matrix, or the highest code rate limit the scope of “divided”.
Regarding claim 1, the limitation “the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “conceivable”.
Regarding claim 1, the limitation “some blocks are replaced” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “some blocks”.
Regarding claim 1, the limitation “with other blocks of submatrices having 1s shifted by a specified fixed value” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear if the “other blocks” related to the first row, or alternately the at least one second row disclosed.
Regarding claim 2, the limitation “the at least one second row that is a single second row” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “that is” in relation to a single second row.
Regarding claim 3, the limitation “the at least one second row that is at least two second rows” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “that is” in relation to at least two second rows.
Claim 3 recites the limitation "the fixed value". There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 6, the limitation “shifting that shifts back blocks of submatrices shifted by the fixed value” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear how the submatrices are shifted.
Regarding claim 6, the limitation “perform same operation as a row operation processing performed for the first check matrix even when a check matrix with a different code rate is used” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same operation” as disclosed.
Regarding claim 7, the limitation “to perform same operation as a column operation processing performed for the second check matrix with the code rate that is lowest even when a check matrix with a different code rate is used” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same operation” as disclosed.
Regarding claim 8, the limitation “a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “that can be divided”. Specifically, whether the first check matrix, or the highest code rate limit the scope of “divided”.
Regarding claim 8, the limitation “the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “conceivable”.
Regarding claim 8, the limitation “some blocks are replaced” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “some blocks”.
Regarding claim 9, the limitation “a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “that can be divided”. Specifically, whether the first check matrix, or the highest code rate limit the scope of “divided”.
Regarding claim 9, the limitation “the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “conceivable”.
Regarding claim 9, the limitation “some blocks are replaced” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “some blocks”.
Regarding claim 10, the limitation “the at least one second row that is a single second row” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “that is” in relation to a single second row.
Regarding claim 11, the limitation “the at least one second row that is at least two second rows” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “that is” in relation to at least two second rows.
Claim 11 recites the limitation "the fixed value". There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 14, the limitation “shifting that shifts back blocks of submatrices shifted by the fixed value” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear how the submatrices are shifted.
Regarding claim 14, the limitation “perform same operation as a row operation processing performed for the first check matrix even when a check matrix with a different code rate is used” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same operation” as disclosed.
Regarding claim 15, the limitation “to perform same operation as a column operation processing performed for the second check matrix with the code rate that is lowest even when a check matrix with a different code rate is used” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same operation” as disclosed.
Any claim not addressed above is rejected due to its dependency on a rejected claim
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 – 15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Independent claim 1 is directed to a mathematical relationship or algorithm that have been identified as abstract by numerous courts.
In analyzing claim 1 of the instant application, the limitations “a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices, the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication, where P is a positive integer” and “generate, using a unit row of the first check matrix that includes the submatrices in column directions, a first row where some blocks are replaced with zero matrices and at least one second row where specified blocks are replaced with zero matrices, with other blocks of submatrices having 1s shifted by a specified fixed value, to generate a second check matrix with a lower code rate than the first check matrix” are directed to a mathematical algorithm, thus, abstract.
The additional elements recited in the claims such as a “a memory to store” and “generation circuitry to generate” are merely generic computer elements performing generic computer functions, and merely storing data is routine and well known in the art (TLI Communications LLC v. AV Automotive LLC), thus, the claimed invention does not amount to significantly more than the abstract idea.
Claims 2 – 7 recite no additional limitation that would amount to significantly more than the abstract idea defined in independent claim 1.
Claim 2
mathematical algorithm
Claim 3
mathematical algorithm
Claim 4
mathematical algorithm
Claim 5
mathematical algorithm
Claim 6
mathematical algorithm
Claim 7
mathematical algorithm
Independent claim 8 is directed to a mathematical relationship or algorithm that have been identified as abstract by numerous courts.
In analyzing claim 8 of the instant application, the limitations “a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices, the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication, where P is a positive integer” and “generate a first row where some blocks are replaced with zero matrices by use of a unit row of the first check matrix that includes the submatrices in column directions; and further generate at least one second row where specified blocks are replaced with zero matrices, with other blocks of submatrices having 1s shifted by a specified fixed value, by use of a unit row of the first check matrix that includes the submatrices in column directions, to generate a second check matrix with a lower code rate than the first check matrix” are directed to a mathematical algorithm, thus, abstract.
The additional elements recited in the claims such as a “control circuit to control a decoding device” and “memory to store”, are merely generic computer elements performing generic computer functions, and merely storing data is routine and well known in the art (TLI Communications LLC v. AV Automotive LLC), thus, the claimed invention does not amount to significantly more than the abstract idea.
Furthermore, limitations such as “the control circuit configured to cause the decoding device to” is merely intended use statements that do not define the decoding device to be anything more than well known, generic computer elements.
Independent claim 9 is directed to a mathematical relationship or algorithm that have been identified as abstract by numerous courts.
In analyzing claim 9 of the instant application, the limitations “a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices, the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication, where P is a positive integer” and “generating a first row where some blocks are replaced with zero matrices by use of a unit row of the first check matrix that includes the submatrices in column directions; and further generating at least one second row where specified blocks are replaced with zero matrices, with other blocks of submatrices having 1s shifted by a specified fixed value, by use of a unit row of the first check matrix that includes the submatrices in column directions, to generate a second check matrix with a lower code rate than the first check matrix” are directed to a mathematical algorithm, thus, abstract.
The additional elements recited in the claims such as a “a decoding device” and “a memory to store” are merely generic computer elements performing generic computer functions, and merely storing data is routine and well known in the art (TLI Communications LLC v. AV Automotive LLC), thus, the claimed invention does not amount to significantly more than the abstract idea.
Claims 10 -15 recite no additional limitation that would amount to significantly more than the abstract idea defined in independent claim 9.
Claim 10
mathematical algorithm
Claim 11
mathematical algorithm
Claim 12
mathematical algorithm
Claim 13
mathematical algorithm
Claim 14
mathematical algorithm
Claim 15
mathematical algorithm
Accordingly, for the reasons provided above, claims 1 – 15 are directed to an abstract idea, hence, not patent eligible under 35 USC 101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al., U.S. Publication 2020/0244290 (herein Sun).
Regarding claim 1, Sun discloses: A decoding device (figure 7, element 790) comprising: a memory to store a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices, the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication, where P is a positive integer (figure 4D, 7; paragraph 0068, 0078, 0085); and generation circuitry to generate (claim 14), using a unit row of the first check matrix that includes the submatrices in column directions, a first row where some blocks are replaced with zero matrices and at least one second row where specified blocks are replaced with zero matrices, with other blocks of submatrices having 1s shifted by a specified fixed value, to generate a second check matrix with a lower code rate than the first check matrix (figure 4A, element 410; 4B, element 445-1; 4C, element 455-2; 4D; 7, element 790; paragraph 0057, 0058, 0078).
Regarding claim 2, Sun discloses: when the generation circuitry generates the at least one second row that is a single second row, the generation circuitry replaces blocks not replaced with zero matrices in the first row with zero matrices as the specified blocks (figure 4A, element 410; 4B, element 445-1; 4C, element 455-2; 4D; 7, element 790; paragraph 0057, 0058, 0078).
Regarding claim 3, Sun discloses: when the generation circuitry generates the at least one second row that is at least two second rows, the generation circuitry replaces blocks that differ between the at least two second rows with zero matrices as the specified blocks, and makes the fixed value differ between the at least two second rows (claim 1; paragraph 0080).
Regarding claim 4, Sun discloses: the generation circuitry uses a plurality of unit rows of the first check matrix that each include the submatrices in column directions and generates the first row and the at least one second row for each of the unit rows (figure 4A, element 410; 4B, element 445-1; 4C, element 455-2; 4D; 7, element 790; paragraph 0057, 0058, 0078, 0097).
Regarding claim 5, Sun discloses: decoding circuitry to repeatedly perform a row operation processing and a column operation processing in decoding using one of the first check matrix and the second check matrix (paragraph 0051, 0052).
Regarding claim 6, Sun discloses: the decoding circuitry includes row operation circuitry to perform, in the row operation processing, masking on blocks of submatrices replaced with the zero matrices and shifting that shifts back blocks of submatrices shifted by the fixed value, to perform same operation as a row operation processing performed for the first check matrix even when a check matrix with a different code rate is used (paragraph 0056, 0062 – 0070).
Regarding claim 7, Sun discloses: the decoding circuitry includes column operation circuitry to perform, in the column operation processing, masking on blocks of submatrices replaced with the zero matrices, to perform same operation as a column operation processing performed for the second check matrix with the code rate that is lowest even when a check matrix with a different code rate is used (paragraph 0056, 0075 – 0080).
Regarding claim 8, Sun discloses: A control circuit to control a decoding device (figure 7, element 790), the decoding device comprising a memory to store a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices, the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication, where P is a positive integer (figure 4D, 7; paragraph 0068, 0078, 0085), wherein the control circuit configured to cause the decoding device (claim 14) to: generate a first row where some blocks are replaced with zero matrices by use of a unit row of the first check matrix that includes the submatrices in column directions; and further generate at least one second row where specified blocks are replaced with zero matrices, with other blocks of submatrices having 1s shifted by a specified fixed value, by use of a unit row of the first check matrix that includes the submatrices in column directions, to generate a second check matrix with a lower code rate than the first check matrix (figure 4A, element 410; 4B, element 445-1; 4C, element 455-2; 4D; 7, element 790; paragraph 0057, 0058, 0078).
Regarding claim 9, Sun discloses: A check matrix generation method for a decoding device (figure 7, element 790), the decoding device comprising a memory to store a first check matrix with a highest code rate that can be divided into blocks of P×P submatrices, the highest code rate being conceivable as a check matrix of a low-density parity-check code used in communication, where P is a positive integer (figure 4D, 7; paragraph 0068, 0078, 0085), wherein the check matrix generation method comprising: generating a first row where some blocks are replaced with zero matrices by use of a unit row of the first check matrix that includes the submatrices in column directions; and further generating at least one second row where specified blocks are replaced with zero matrices, with other blocks of submatrices having 1s shifted by a specified fixed value, by use of a unit row of the first check matrix that includes the submatrices in column directions, to generate a second check matrix with a lower code rate than the first check matrix (figure 4A, element 410; 4B, element 445-1; 4C, element 455-2; 4D; 7, element 790; paragraph 0057, 0058, 0078).
Regarding claim 10, Sun discloses: when the at least one second row that is a single second row is generated in the generating the at least one second row, blocks not replaced with zero matrices in the first row are replaced with zero matrices as the specified blocks (figure 4A, element 410; 4B, element 445-1; 4C, element 455-2; 4D; 7, element 790; paragraph 0057, 0058, 0078).
Regarding claim 11, Sun discloses: wherein when the at least one second row that is at least two second rows is generated in the generating the at least one second row, blocks that differ between the at least two second rows are replaced with zero matrices as the specified blocks, and the fixed value differs between the at least two second rows (claim 1; paragraph 0080).
Regarding claim 12, Sun discloses: wherein in the generating the first row, a plurality of unit rows of the first check matrix that each include the submatrices in column directions are used to generate the first row for each of the unit rows, and in the generating the at least one second row, a plurality of unit rows of the first check matrix that each include the submatrices in column directions are used to generate the at least one second row for each of the unit rows (figure 4A, element 410; 4B, element 445-1; 4C, element 455-2; 4D; 7, element 790; paragraph 0057, 0058, 0078, 0097).
Regarding claim 13, Sun discloses: repeatedly performing a row operation processing and a column operation processing in decoding using one of the first check matrix and the second check matrix (paragraph 0051, 0052).
Regarding claim 14, Sun discloses: wherein in the row operation processing of the repeatedly performing the row operation processing and the column operation processing, masking on blocks of submatrices replaced with the zero matrices and shifting that shifts back blocks of submatrices shifted by the fixed value are performed to perform same operation as a row operation processing performed for the first check matrix even when a check matrix with a different code rate is used (paragraph 0056, 0062 – 0070).
Regarding claim 15, Sun discloses: wherein in the column operation processing of the repeatedly performing the row operation processing and the column operation processing, masking on blocks of submatrices replaced with the zero matrices is performed to perform same operation as a column operation processing performed for the second check matrix with the code rate that is lowest even when a check matrix with a different code rate is used (paragraph 0056, 0075 – 0080).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jin; Jie et al. US 20210058095 A1
Montorsi; Guido et al. US 10868567 B2
JIN; Jie et al. US 20200343912 A1
SUGIHARA; Kenya et al. US 20150365105 A1
Yosoku; Naoya et al. US 20130139038 A1
Matsumoto; Wataru et al. US 20090164864 A1
Kuznetsov; et al. US 6757122 B1
generation circuitry to generate, using a unit row of the first check matrix that includes the submatrices in column directions, a first row where some blocks are replaced with zero matrices and at least one second row where specified blocks are replaced with zero matrices, with other blocks of submatrices having 1s shifted by a specified fixed value, to generate a second check matrix with a lower code rate than the first check matrix.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Daniel F. McMahon/Primary Examiner, Art Unit 2111