DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 2, 3, 6-13, 19-21, and 23 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Nakatsuka et al (US PGPUB 2005/0270083).
Regarding claim 2, Figure 19 of Nakatsuka discloses a switch comprising:
a plurality of series-coupled transistors [109-112]
wherein a first transistor of the plurality of series-coupled transistors has a first size [109; paragraph 178; Figure 13; paragraph 142]
a second transistor of the plurality of series-coupled transistors has a second size smaller from the first size [110; paragraph 178; Figure 13; paragraph 142]
Regarding claim 3, Figure 19 of Nakatsuka discloses wherein a third transistor of the plurality of series-coupled transistors has a third size, and wherein the second size is smaller than the first size and the third size [112; paragraph 178; paragraph 142].
Regarding claim 6, Figure 19 of Nakatsuka discloses wherein the first size of the first transistor comprises a first width of the first transistor, wherein the second size of the second transistor comprises a second width of the second transistor, and wherein the second width is smaller than the first width [paragraph 137; paragraph 142].
Regarding claim 7, Figure 19 of Nakatsuka discloses a first node associated with a first voltage; and a second node associated with a second voltage lower in magnitude than the first voltage, wherein the plurality of series-coupled transistors is coupled between the first node and the second node [401 and GROUND; paragraphs 174-177].
Regarding claim 8, Figure 19 of Nakatsuka discloses wherein the first node is configured to receive the first voltage, and wherein the first voltage is a radio frequency (RF) voltage [401; paragraphs 174-177].
Regarding claim 9, Figure 19 of Nakatsuka discloses wherein the plurality of series-coupled transistors is configured to selectively shunt the RF voltage to ground [Figure 19; paragraphs 174-177].
Regarding claim 10, Figure 19 of Nakatsuka discloses wherein the plurality of series-coupled transistors is configured to selectively shunt the RF voltage to ground by: shunting the RF voltage to ground when each transistor of the plurality of series-coupled transistors is closed; and not shunting the RF voltage to ground when each transistor of the plurality of series-coupled transistors is open [Figure 19; paragraphs 174-177].
Regarding claim 11, Figure 19 of Nakatsuka discloses wherein the second node is coupled to a reference voltage [GROUND].
Regarding claim 12, Figure 19 of Nakatsuka discloses wherein the reference voltage is ground [GROUND].
Regarding claim 13, Figure 19 of Nakatsuka discloses wherein the first transistor is coupled to the first node [401].
Regarding claim 19, Figure 19 of Nakatsuka discloses a method comprising:
receiving, at a first node of a switch, a radio frequency (RF) voltage [401; paragraphs 174-177]
selectively shunting, by a plurality of series-coupled transistors of the switch, the RF voltage to ground [603; paragraphs 174-177]
wherein the plurality of series-coupled transistors is coupled between the first node and a second node of the switch [401 and GROUND]
wherein the second node is coupled to ground [GROUND]
wherein a first transistor of the plurality of series-coupled transistors has a first size [109; paragraph 178; Figure 13; paragraph 142]
wherein a second transistor of the plurality of series-coupled transistors has a second size smaller from the first size [110; paragraph 178; Figure 13; paragraph 142]
Regarding claim 20, Figure 19 of Nakatsuka discloses wherein the selectively shunting comprises: shunting the RF voltage to ground when each transistor of the plurality of series-coupled transistors is closed; and not shunting the RF voltage to ground when each transistor of the plurality of series-coupled transistors is open. [Figure 19; paragraphs 174-177]
Regarding claim 21, Figure 19 of Nakatsuka discloses wherein the first size of the first transistor comprises a first width of the first transistor, wherein the second size of the second transistor comprises a second width of the second transistor, and wherein the second width is smaller than the first width [paragraph 137; paragraph 142].
Regarding claim 23, Figure 19 of Nakatsuka discloses wherein a third transistor of the plurality of series-coupled transistors has a third size, and wherein the second size is smaller than the first size and the third size [112; paragraph 178; paragraph 142].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 16-18 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Nakatsuka et al (US PGPUB 2005/0270083).
Regarding claim 5, Nakatsuka does not explicitly disclose wherein the first size of the first transistor comprises a first area of the first transistor, wherein the second size of the second transistor comprises a second area of the second transistor, and wherein the second area is smaller than the first area.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Nakatsuka by using different areas instead of different gate widths as a matter of simple design-choice, since it does not appear that using different areas provides any benefit over using different widths and it appears the invention would perform equally well with different widths.
Regarding claim 16, Nakatsuka does not explicitly disclose wherein a difference between a drain-source capacitance (Cds) associated with the first transistor and a Cds associated with the second transistor is at least 2%.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Nakatsuka by using the above range of drain-source capacitances as a matter of simple design-choice, since it has been held that where the general conditions of claim are disclosed in the prior art, finding the optimum or workable ranges involves only routine skill in the art.
Regarding claim 17, Nakatsuka does not explicitly disclose wherein the first size of the first transistor comprises a first die area of the first transistor, wherein the second size of the second transistor comprises a second die area of the second transistor, and wherein the second die area is smaller than the first die area.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Nakatsuka by using different areas instead of different gate widths as a matter of simple design-choice, since it does not appear that using different areas provides any benefit over using different widths and it appears the invention would perform equally well with different widths.
Regarding claim 18, Nakatsuka does not explicitly disclose an antenna switch circuit comprising the switch.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Nakatsuka by using the circuit in an antenna switch circuit as a matter of simple design-choice, since it was well-known in the art to use RF switches with antennas.
Allowable Subject Matter
Claims 4, 14, 15, 22, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TOMI SKIBINSKI/Primary Examiner, Art Unit 2842