3Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub # 2021/0327479) in view of Mazumder et al. (US Pub # 2024/0071436).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Kim teaches a command timing control circuit, comprising a decoding circuit and a shift circuit (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0134, 0146, 0179-0182, decoding circuit (100+200), Unit 300 includes shift circuit 310), wherein: the decoding circuit is configured to receive a frequency indication signal and a write preamble signal, perform decoding processing according to the frequency indication signal and the write preamble signal (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0134, 0146, 0179-0182, CLK signal is frequency signal, CA signal includes write preamble signal), and generate a control signal, the control signal indicating a first duration for shifting a read modify write command signal; and the shift circuit is configured to receive the control signal and the read modify write command signal, shift the read modify write command signal by the first duration according to the control signal, and generate a target command signal, such that a time interval between the target command signal and a write enable signal meets a preset timing condition (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0134, 0146, 0179-0182, Shift signal receive control signal clock CLK and read modify write signal RMW and generate IWT write command signal based on SFT4 signal and CLK by unit 340).
Even though Kim teaches decoder 100 generate read-modify write signal RMW but silent exclusively about generate a control signal, the control signal indicating a first duration for shifting a read modify write command signal.
Mazumder et al. teach decoder to generate a control signal, the control signal indicating a first duration for shifting a read modify write command signal (see Fig. 1 and paragraph 0028, generate state machine SM-52 generate read-modify write signal and command control signal 36).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Mazumder et al. to the teaching of Kim where decoder 100 of Kim would be replaced with decoder 32 of Majumdeet al. where decoder generate command control signal along with read-modify write signal for the shift circuitry 310 in order to properly control the timing operation of shift circuitry and to avoid memory failure (see Mazumder et al. , paragraph 0013).
Further reason to combine the teachings of Mazumder et al. and Kim is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards memory device which includes decoder to generate read-modify write command and control command.
Regarding claim 2, Kim further teaches, wherein the shift circuit comprises S stage shift sub-circuits, the control signal comprises S control sub-signals, and only one of the S control sub-signals is in an enabled state, wherein S is an integer greater than 1; an input terminal of a first shift sub-circuit of the S shift sub-circuits is configured to receive the read modify write command signal, a first output terminal of an i-th shift sub-circuit of the S shift sub-circuits is connected to an input terminal of an (i+1)-th shift sub-circuit of the S shift sub-circuits, and a control terminal of the i-th shift sub-circuit of the S shift sub-circuits is configured to receive an i-th control sub-signal of the S control sub-signals, wherein i is an integer greater than 0 and less than S; (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0131) and wherein: the shift circuit is configured to shift the read modify write command signal by the first duration through the first to a j-th shift sub-circuits of the S shift sub-circuits when a j-th control sub-signal of the S control sub-signals is in an enabled state, to obtain the target command signal, and output the target command signal through the j-th shift sub-circuit of the S shift sub-circuits, wherein j is an integer greater than 0 and smaller than S (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0134).
Regarding claim 3, Kim further teaches, wherein a clock terminal of each one of the S shift sub-circuits is configured to receive a clock signal, and each one of the S shift sub-circuits shifts a signal received at an input terminal based on the clock signal, wherein: when i is equal to 1, a first shift sub-circuit of the S shift sub-circuits shifts the read modify write command signal by two clock cycles or one of the two clock cycles; and when i is greater than 1, the first to an (i-1)-th shift sub-circuits of the S shift sub-circuits shift signals received at input terminals by the two clock cycles, and the i-th shift sub-circuit of the S shift sub-circuits shifts a signal received at an input terminal by the two clock cycles or one of the two clock cycles, wherein the clock cycle is a cycle of the clock signal (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0134, 0146, 0179-0182).
Regarding claim 4, Kim further teaches, wherein a second duration compensated for shifting the read modify write command signal is obtained through encoding according to a frequency value indicated by the frequency indication signal; and a third duration compensated for shifting the read modify write command signal is obtained through encoding according to the write preamble signal, wherein the second duration is equal to A times the clock cycle, the third duration is equal to B times the clock cycle, and the first duration is related to the second duration and the third duration; A and B are both greater than 0, and A is less than B (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0134, 0146, 0179-0182).
Regarding claim 5, Kim further teaches, wherein the write preamble signal comprises N write preambles, wherein N is an integer greater than 0; the frequency indication signal comprises at least one bit of operand, wherein the at least one bit of operand corresponds to M logic combinations, and each one of the M logic combinations corresponds to a frequency value, with M being an integer greater than 0; and the decoding circuit comprises a first decoding circuit, a second decoding circuit, and a third decoding circuit, wherein: the first decoding circuit is configured to receive the at least one bit of operand, perform first logic processing according to the at least one bit of operand, and generate M frequency code signals, with the M frequency code signals in a one-to-one correspondence with M of the frequency values (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089), and only one of the M frequency code signals being in an enabled state; the second decoding circuit is configured to receive the M frequency code signals and the N write preambles, perform AND logic processing on each one of the M frequency code signals and each one of the N write preambles, and generate M×N initial control sub-signals; and the third decoding circuit is configured to receive the M×N initial control sub-signals, perform OR logic processing on several of the M×N initial control sub-signals, respectively, and generate the S control sub-signals (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0130).
Regarding claim 6, Kim further teaches, wherein the i-th shift sub-circuit of the S shift sub-circuits comprises a first output circuit, a second output circuit, a control circuit, and a select circuit, wherein: the first output circuit is configured to shift the signal received at the input terminal by one clock cycle, and generate a first shift amount signal, wherein when i is equal to 1, an input terminal of the first output circuit receives the read modify write command signal, and when i is greater than 1, the input terminal of the first output circuit receives a signal output by the (i-1)-th shift sub-circuit of the S shift sub-circuits; the second output circuit is configured to receive the first shift amount signal, shift the first shift amount signal by one clock cycle, and generate a second shift amount signal; the control circuit is configured to receive the second shift amount signal and the control sub-signal, and control whether to output the second shift amount signal to the (i+1)-th shift sub-circuit of the S shift sub-circuits according to the control sub-signal (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0068) and the select circuit is configured to receive the first shift amount signal, the second shift amount signal, the control sub-signal, and a preset write preamble, and select to output the first shift amount signal or the second shift amount signal as the target command signal according to the preset write preamble when the control sub-signal is in an enabled state; the preset write preamble instructs the i-th shift sub-circuit of the S shift sub-circuits to shift the signal received at the input terminal by two clock cycles or one of the two clock cycles (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073, 0089, 0118-0130).
Regarding claim 9, Kim further teaches, further comprising a command processing circuit, wherein: the command processing circuit is configured to receive a write command signal, perform shift processing on the write command signal to obtain a shifted write command signal, and determine a first shifted write command signal during a column address strobe write latency period as the read modify write command signal (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0073).
Regarding claim 10, Kim further teaches a memory, comprising the command timing control circuit according to claim 1 (see Fig. 1-6, 10-14, 16, 22-24 and paragraph 0006-0007, 0039-0042).
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
an output terminal of the first NOT gate is connected to an input terminal of the first transmission circuit; and an output terminal of the first transmission circuit is connected to an input terminal of the second transmission circuit and is configured to output the first shift amount signal; an output terminal of the second transmission circuit is connected to an input terminal of the second NOT gate; and an output terminal of the second NOT gate is connected to a first input terminal of the first AND gate and is configured to output the second shift amount signal; a second input terminal of the first AND gate is configured to receive an inverted control sub-signal, and an output terminal of the first AND gate is used as a first output terminal of the shift sub-circuit; a first input terminal of the second AND gate is configured to receive the first shift amount signal, a second input terminal of the second AND gate is configured to receive the preset write preamble, and an output terminal of the second AND gate is connected to a first input terminal of the first OR gate; a first input terminal of the third AND gate is configured to receive the second shift amount signal, a second input terminal of the third AND gate is configured to receive an inverted preset write preamble, and an output terminal of the third AND gate is connected to a second input terminal of the first OR gate; an output terminal of the first OR gate is connected to a first input terminal of the fourth AND gate, a second input terminal of the fourth AND gate is configured to receive the control sub-signal, and an output terminal of the fourth AND gate is used as a second output terminal of the shift sub-circuit, wherein, the inverted preset write preamble is obtained by performing inverted processing on the preset write preamble, and the inverted control sub-signal is obtained by performing inverted processing on the control sub-signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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