CTNF 18/942,774 CTNF 88495 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1 – 10 are pending. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 08-34 AIA Claim (s) 1 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claim (s) 8 of U.S. Patent No. 16/010,969 in view of JP 2011059838 A . Although the claims at issue are not identical, they are not patentably distinct from each other because they encompass substantially similar subject matter . The following table is presented for the purpose of a comparison of the conflicting claims between the application and the patent. Application No. 18/942,774 U.S. Patent No.: 12,174,247 B2 Claim 1 Claim 8 A semiconductor device comprising: a core area in which transistors to be monitored are disposed; a non-core area; and a plurality of oscillators each configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level; a multiplexer configured to output a selected oscillation signal in response to a selection signal; and a counter configured to count a number of rises or a number of falls of the selected oscillation signal, wherein: the plurality of oscillators are disposed in the core area, the multiplexer and the counter are disposed in the non-core area, and the plurality of oscillators include different numbers of inverting logics coupled in series to each other . A semiconductor device comprising: a core area in which transistors to be monitored are disposed; a non-core area; a plurality of oscillators each configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level; a multiplexer configured to output a selected oscillation signal in response to a selection signal; and a counter configured to count a number of rises or a number of falls of the selected oscillation signal, wherein: the plurality of oscillators are disposed in the core area, and the multiplexer and the counter are disposed in the non-core area. But U.S. Patent No.: 12,174,247 B2 does not specifically teach the plurality of oscillators include different numbers of inverting logics coupled in series to each other. However, JP 2011059838 A suggests the plurality of oscillators include different numbers of inverting logics coupled in series to each other (page 1, paragraphs 4 and 5; plurality of inverters on the oscillator circuit are connected in series with each other). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify U.S. Patent No.: 12,174,247 B2 in view of JP 2011059838 A in order to provide a signal in phase or not in phase at each node as desired (JP 2011059838 A, page 2, paragraph 6) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 4 – 10 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding Claim 4 , the prior art of record does not teach claimed limitation: “a counter configured to count a number of rises or a number of falls of the selected oscillation signal; a determiner configured to output semiconductor process state information based on a count value output from the counter and a reference value, wherein: the plurality of oscillators are disposed in the core area” in combination with all other claimed limitations of claim 4 . Regarding Claims 5 – 7 , the claims are allowed as they further limit allowed claim 4. Regarding Claim 8 , the prior art of record does not teach claimed limitation: “a counter configured to count a number of rises or a number of falls of the selected oscillation signal; a determiner configured to output semiconductor process state information based on a count value output from the counter and a reference value, wherein: the plurality of oscillators are disposed in the core area” in combination with all other claimed limitations of claim 8 . Regarding Claims 9 – 10 , the claims are allowed as they further limit allowed claim 8. Comments The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claim(s) 1. Therefore, no prior art rejection for claim(s) 1 – 3 is presented in this action. However, Claim(s) 1 is/are rejected on the ground of nonstatutory double patenting. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Kim et al. (US 2022/0076778 A1) teach a semiconductor memory device comprising: a memory core including a memory cell array configured to store data, and a data input/output circuit connected to a data input/output pad; and a built-in self test (BIST) circuit connected to a test pad that is disposed separate from the data input/output pad, the BIST circuit configured to generate test pattern data including first parallel bits based on commands and addresses received from external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device (see claim 1). Choi et al. (US 2020/0371157 A1) suggest a wafer-level method of testing an integrated circuit (IC) device, comprising: applying a plurality of test operation signals to a wafer containing the IC device; generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals; and then testing at least a portion of the IC device in response to said generating the test enable signal (see claim 1). Chiu et al. (US 2019/0066815 A1) disclose a method for detecting minimal operation voltage of memory array, comprising: receiving a minimum testing voltage and a maximum testing voltage; dividing a range of voltage between the minimum testing voltage and the maximum testing voltage into a plurality of testing voltages; performing a memory array operation test on the memory array for each of the testing voltages, wherein the testing voltages are provided for operating the memory array; detecting an occurrence of failure in the memory array in a failure memory array operation test; and detecting at least one of the testing voltages utilized for operating the memory array during the detected failure memory array operation test (see claim 1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to GIOVANNI ASTACIO-OQUENDO whose telephone number is (571)270-5724. The examiner can normally be reached Monday - Friday, 8:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 6/13/2026 Application/Control Number: 18/942,774 Page 2 Art Unit: 2858 Application/Control Number: 18/942,774 Page 3 Art Unit: 2858 Application/Control Number: 18/942,774 Page 4 Art Unit: 2858 Application/Control Number: 18/942,774 Page 5 Art Unit: 2858 Application/Control Number: 18/942,774 Page 6 Art Unit: 2858
Prosecution Insights