Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub # 2022/0122678).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Kim teaches a memory device comprising: a memory cell array including a memory cell; a page buffer connected to the memory cell through a bit line (see Fig. 1-2, paragraph 0034-0091, memory array 110, unit 123 is page buffer), the page buffer configured to perform a sensing operation of sensing program data stored in the memory cell; and a bit line operation controller configured to control the page buffer to perform a page buffer under drive operation before the sensing operation (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, Unit 130 is controller), wherein the page buffer includes: a latch circuit configured to store the program data; a sense amplifier (amp) circuit configured to perform the sensing operation; and a page buffer control switch configured to connect the bit line to the sense amp circuit (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, Unit 128 is sense amp circuitry, PBSIGNALS is page buffer control signal, Unit 101 include page buffer control switch) wherein the page buffer under drive operation is an operation of applying a page buffer control signal having a target voltage level to the page buffer control switch, and wherein the target voltage level is determined based on a read voltage level of a read voltage applied to a word line connected to the memory cell in the sensing operation (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, row decoder 122 apply read voltage, Vpbs is page buffer target voltage).
Even though Kim teaches page buffer target voltage and read voltage but silent exclusively about wherein the target voltage level is determined based on a read voltage. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Kim where page buffer sensing signal PBSENSE reach to target voltage Vpbs when wordline voltage is applied at T2-T3 in order to improve performance by decreasing program operation time with decreased peak current (see paragraph 0006).
Regarding claim 2, Kim teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Kim further teahces, further comprising a page buffer control information storage configured to store setting information on the page buffer control signal (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250).
Regarding claim 3, Kim teaches all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Kim further teahces, wherein the setting information includes an offset voltage level of the page buffer control signal, which corresponds to the read voltage level (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222).
Regarding claim 4, Kim teaches all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Kim further teahces, wherein the target voltage level is determined based on a default voltage level and the offset voltage level of the page buffer control signal (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0221).
Regarding claim 5, Kim teaches all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Kim further teahces, wherein the setting information includes a probability that a memory cell connected to a bit line adjacent to the bit line will be read as a program cell according to the read voltage level (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0227).
Regarding claim 6, Kim teaches all claimed subject matter as applied in prior rejection of claim 5 on which this claim depends.
Kim further teahces, wherein a magnitude of the offset voltage level is in inverse proportion to the probability that the memory cell will be read as the program cell (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0218).
Regarding claim 7, Kim teaches all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Kim further teahces, wherein the setting information includes an under drive group to which the read voltage level belongs according to the offset voltage level (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213).
Regarding claim 8, Kim teaches all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Kim further teahces, wherein the bit line operation controller determines the target voltage level, based on the setting information, and controls the page buffer to perform the page buffer under drive operation while a word line under driver operation is performed on the word line (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0230).
Regarding claim 9, Kim teaches all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Kim further teahces, wherein the bit line operation controller terminates the page buffer under drive operation before a word line settling operation of setting a potential of the word line to the read voltage level is completed (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213).
Regarding claim 10, Kim teaches all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Kim further teahces, wherein the word line under drive operation is an operation of applying, to the word line, an under drive voltage having a level lower than the read voltage level before the sensing operation (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0218).
Regarding claim 11, Kim teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Kim further teahces, wherein the page buffer performs a next sensing operation when the read voltage level is changed after the sensing operation is performed (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250).
Regarding claim 12, Kim teaches all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Kim further teahces, wherein the page buffer disables the sense amp circuit according to a result of the sensing operation in the next sensing operation (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0232).
Regarding claim 13, Kim teaches all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Kim further teahces, wherein the page buffer applies a shielding voltage to the bit line according to a result of the sensing operation in the next sensing operation (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0245).
Regarding independent claim 14, Kim teaches a page buffer comprising: a page buffer control switch connected between a bit line connected to a memory cell and a common sensing node (see Fig. 1-2, paragraph 0034-0091, memory array 110, unit 123 is page buffer), the page buffer control switch configured to be controlled according to a page buffer control signal ; first and second switches connected in series between a power node and a sensing node; a third switch connected between the sensing node and the common sensing node, the third switch configured to be controlled according to a sense amplifier (amp) sensing signal; fourth and fifth switches connected in series between the sensing node and a ground node (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, Unit 128 is sense amp circuitry, PBSIGNALS is page buffer control signal, Unit 101 include page buffer control switch); and a latch circuit configured to store data sensed from the memory cell, wherein the first switch and the fifth switch are controlled according to the data stored in the latch circuit, wherein the second switch is controlled according to a sense amp precharge signal, wherein the fourth switch is controlled according to a sense amp discharge signal (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, Vpre is precharge signal, LATS is latch circuit), wherein the page buffer control signal having a target voltage level is applied to the page buffer control switch before a sensing operation on the memory cell, and wherein the target voltage level is determined according to a read voltage level of a read voltage applied to a word line connected to the memory cell in the sensing operation (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, row decoder 122 apply read voltage, Vpbs is page buffer target voltage).
Even though Kim teaches page buffer target voltage and read voltage but silent exclusively about wherein the target voltage level is determined based on a read voltage. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Kim where page buffer sensing signal PBSENSE reach to target voltage Vpbs when wordline voltage is applied at T2-T3 in order to improve performance by decreasing program operation time with decreased peak current (see paragraph 0006).
Regarding claim 15, Kim teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Kim further teahces, wherein the target voltage level is determined based on a default voltage level and an offset voltage level of the page buffer control signal, and wherein the offset voltage level is determined according to a probability that a memory cell connected to a bit line adjacent to the bit line will be read as a program cell according to the read voltage level (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250).
Regarding claim 16, Kim teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Kim further teahces, wherein the page buffer control signal maintains the target voltage level while an under drive voltage having a level lower than the read voltage level is applied to the word line, and is changed from the target voltage level to a default voltage level before a potential of the word line reaches the read voltage level (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222).
Regarding claim 17, Kim teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Kim further teahces, wherein a shielding voltage is applied to the bit line according to a result of the sensing operation in a next sensing operation in which the read voltage level is changed (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226).
Regarding claim 18, Kim teaches all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Kim further teahces, wherein the sense amp discharge signal is inactivated in the sensing operation, and is activated in the next sensing operation (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0243).
Regarding independent claim 19, Kim teaches a method of operating a memory device, the method comprising: performing a page buffer under drive operation before a sensing operation of sensing data stored in a memory cell (see Fig. 1-2, paragraph 0034-0091, memory array 110, unit 123 is page buffer); and performing the sensing operation by applying a read voltage to a word line connected to the memory cell, wherein the performing of the page buffer under drive operation includes: determining a target voltage level of a page buffer control signal, based on a read voltage level of the read voltage (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, row decoder 122 apply read voltage, Vpbs is page buffer target voltage); and applying the page buffer control signal having the target voltage level to a page buffer control switch connecting a bit line connected to the memory cell to a latch circuit storing the data (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266, Unit 128 is sense amp circuitry, PBSIGNALS is page buffer control signal, Unit 101 include page buffer control switch).
Even though Kim teaches page buffer target voltage and read voltage but silent exclusively about wherein the target voltage level is determined based on a read voltage. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Kim where page buffer sensing signal PBSENSE reach to target voltage Vpbs when wordline voltage is applied at T2-T3 in order to improve performance by decreasing program operation time with decreased peak current (see paragraph 0006).
Regarding claim 20, Kim teaches all claimed subject matter as applied in prior rejection of claim 19 on which this claim depends.
Kim further teahces, wherein, in the determining of the target voltage level, the target voltage level is determined based on a default voltage level and an offset voltage level of the page buffer control signal, and wherein the offset voltage level is determined according to a probability that a memory cell connected to a bit line adjacent to the bit line will be read as a program cell according to the read voltage level (see Fig. 1-15, paragraph 0034-0091, 0107-0140, 0144-0156, 0158-0167, 0172-0191, 0194-0210, 0213-0222, 0226-0250, 0253-0266).
Response to Arguments
Applicant's arguments filed 07/21/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 8 of remarks) that Kim fails to teach or suggest "the page buffer under drive operation is an operation of applying a page buffer control signal having a target voltage level to the page buffer control switch" and "the target voltage level is determined based on a read voltage level of a read voltage applied to a word line connected to the memory cell in the sensing operation" as set forth in claim 1. Examiner respectfully disagrees with this statement.
First, as per claim limitation, page buffer under drive operation is an operation of applying a page buffer control signal having a target voltage level to the page buffer control switch.
Second, the target voltage level is determined based on a read voltage level.
Third, Other limitation clearly indicate page buffer under drive operation is before sensing operation i.e. it can be during precharge operation.
In Fig. 2, 5, 9, 12-14 and paragraph 0071-0090, 0120-0131, 0227-0249 where Kim teaches that read voltage generated by the unit 121 applied to wordline of row decoder 122 and the sensing circuitry 126 received VPB signal from page buffer circuitry 123. The control logic unit 130 which includes page buffer controller 101 receives the output from unit 126 and generate page buffer control signal PBSIGNALS to page buffer which include page buffer sense signal PBSENSE signal (see specially paragraph 0170). At time T2-T3 (for Fig.5), PBSENSE signal reaches to Vpbs voltage as target reference voltage. Here, page buffer controller / control switch 101 generate and control the page buffer unit 123 using PBSENSE signal and determine target voltage Vpbs as the target voltage for sensing operation based on read voltage generated by unit 121. So, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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