DETAILED ACTION
This action is responsive to the following communications: the Application filed November 11, 2014, and the information disclosure statement (IDS) filed November 11, 2014, May 23, 2025 and December 23, 2025. This application is a DIV of 17/483,501.
Claims 1-21 are pending. Claims 1, 13 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 11, 2014, May 23, 2025 and December 23, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 recites “… generating the control word is performed. periodically …”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,165,698. Although the claims at issue are not identical, they are not patentably distinct from each other.
Although Instant Application is a DIV of Application No. 17/483,501, the amendment of the Instant Application contains the subject matter of the Application ‘973. See the following for more details, i.e., nonstatutory double patenting rejection may be appropriate in situations in which the invention presented in the divisional is not the same invention that was the subject of the restriction requirement (see MPEP 804.04).
Instant Application
US Patent 12,165,698
Comment
Claim 19. A method of operating a static random access memory (SRAM) device, comprising:
powering an array of SRAM cells between a first voltage and a second voltage in retention mode;
generating a reference voltage that is proportional to absolute temperature, wherein a magnitude curve of the reference voltage as a function of temperature is based upon a control word; and
maintaining the second voltage as being equal to the reference voltage;
generating the control word based upon information about the SRAM device;
wherein generating the reference voltage comprises:
generating a current proportional to absolute temperature having a magnitude curve based upon the control word; and
passing the current through a resistor coupled to ground to form the reference voltage across the resistor.
Claim 11. A static random access memory (SRAM) device,
comprising:
an array of SRAM cells powered between a first voltage
and a second voltage in retention mode;
a reference voltage generator configured to generate a reference voltage that is proportional to absolute temperature, wherein a magnitude curve of the reference
voltage as a function of temperature is based upon a
control word;
a circuit configured to set and maintain the second voltage
as being equal to the reference voltage; and
control circuitry configured to generate the control word
based upon information about the SRAM device;
wherein the reference voltage generator comprises:
a current generator configured to generate a current proportional to absolute temperature having a magnitude curve based upon the control word; and a resistor coupled between the current generator and ground, wherein the reference voltage is formed across the resistor.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8-9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nautiyal et al. (US 2006/0050590).
Regarding independent claim 1, Nautiyal et al. disclose a method of operating a static random access memory (SRAM) device in retention mode, the method comprising:
powering an array of SRAM cells (see e.g., FIG. 7, along with FIG. 1) between first (voltage at top bold line) and second (voltage at bottom bold line) voltages in retention mode (see FIG. 7, along with prior art FIG. 2, and accompanying disclosure, e.g., para. 0058);
detecting process variation information about the array of SRAM cells (e.g., para. 0051: … memory cells … changes due to temperature variation …), and generating a control word based thereupon (FIG. 7: WL, i.e., controlling (generating) word lines to determine desired reference voltage);
generating a reference voltage (FIG. 11: Vref) that is proportional to absolute temperature (FIGS. 12-14, and para. 0063: … virtual ground for the temperature dependent reference variation …) and having a magnitude curve that is set by the control word (FIG. 7: WL, i.e., the size of 84 (number of WL) determine desired reference voltage); and
maintaining the second voltage as being equal to the reference voltage (FIG. 11 and accompanying disclosure, e.g., para. 0063-0065, i.e., Virtual-gnd = g(Vref, T)).
Regarding claim 8, which depends from claim 1, Nautiya et al. disclose generating the reference voltage comprises: selecting one of a plurality of reference voltages each being proportional to absolute temperature and having different magnitude curves from one another based upon the control word (see e.g., para. 0056: … Vref1 and Vref2 …; along with FIGS. 6 and 8: WL); and passing the selected reference voltage for use as the reference voltage (e.g., FIG. 6, selecting M61 and M63; and FIG. 8: BLKCNTRL, and accompanying disclosure).
Regarding claim 9, as best as can be understood, which depends from claim 1, Nautiya et al. teach detecting process variation information and generating the control word is performed. periodically during operation of the SRAM device (see FIG. 12 and accompanying disclosure, e.g., para. 0066).
Regarding claim 11, which depends from claim 1, Nautiya et al. disclose further comprising: generating a second reference voltage that is proportional to absolute temperature and having a magnitude curve that is set by the control word; powering the array of SRAM cells between a third voltage and the second voltage; and maintaining the third voltage as being equal to the second reference voltage (see e.g., FIG. 11, Supply terminal, VDD and GND, and Virtual Supply M82 and M83, and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7, 10 and 12 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nautiyal et al. (US 2006/0050590).
Regarding claim 6, Nautiya et al. teach the limitations of claim 1.
Nautiya et al. are silent with respect to detecting process variation information comprises: operating a ring oscillator formed on a same die as the array of SRAM cells; detecting an oscillation frequency of the ring oscillator; and determining the process variation information based upon the oscillation frequency of the ring oscillator.
However, ring oscillator used to detect PVT variation in memory device (e.g., SRAM) is a well-known technology for a type of memory (e.g., SRAM) for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used PVT variation with ring-OSC because these conventional technology are well established in the art of the memory devices.
Regarding claim 7, Nautiya et al. teach the limitations of claim 1.
Nautiyal et al. further teach generating the reference voltage comprises: generating a current proportional to absolute temperature having a magnitude curve that is set by the control word (FIG. 11: Vref; FIGS. 12-14, and para. 0063: … virtual ground for the temperature dependent reference variation …; and FIG. 7: WL, i.e., the size of 84 (number of WL) determine desired reference voltage).
Nautiyal et al. are silent with respect to sourcing the current proportional to absolute temperature to a resistor so that the reference voltage will be formed thereacross.
However, the claimed limitation of reference voltage is a well-known technology for a type of SRAM memory for its purpose.
For support, of the above asserted facts, see for example, Marr et al. (US 6,529,421), e.g., FIG. 21A and accompanying disclosure, e.g., col 14, lines 48-64: … the current … stack of resistors …reference voltage ...
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Marr et al. to the teaching of Nautiyal et al. such that a memory, as taught by Nautiyal et al., to utilizes a temperature and a resistor to a reference voltage, as taught by Marr et al., for the purpose of utilizing passive elements for generating reference voltages.
Regarding claim 10, Nautiya et al. teach the limitations of claim 1.
Nautiyal et al. further teach detecting process variation information and generating the control word is performed (see e.g.., FIGS. 11-14 and accompanying disclosoure).
Nautiyal et al. are silent with respect to PVT information after a predetermined number of power-ups of the SRAM device.
However, the claimed limitation of detecting variation is a well-known technology for a type of SRAM memory for its purpose.
For support, of the above asserted facts, see for example, Kim et al. (US 2013/0042138), e.g., FIG. 3A and accompanying disclosure, e.g., para. 0043: … The memory unites … different amount of time to complete power-up … due to variations in manufacturing process ...
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Kim et al. to the teaching of Nautiyal et al. such that a memory, as taught by Nautiyal et al., to utilizes power-up with variations, as taught by Kim et al., for the purpose of utilizing the variations of the adjusted power-up in memory.
Regarding claim 12, Nautiya et al. teach the limitations of claim 1.
Nautiyal et al. are silent with respect detecting process variation information and generating the control word comprises: performing electronic wafer sorting on a die containing the array of SRAM cells to tune for process variation of the die while maintaining a margin to accommodate statistical variation on the die; and setting the control word based on the electronic wafer sorting.
However, the claimed limitation of wafter sorting and die variation is a well-known technology for a type of memory process for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used wafter sorting and die variation because these conventional technology are well established in the art of the memory devices.
Claims 19 and 21 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nautiyal et al. (US 2006/0050590) in view of Dreesen (US 9,792,979).
Regarding independent claim 19, Nautiyal et al. teach a method of operating a static random access memory (SRAM) device in retention mode, the method comprising:
powering an array of SRAM cells (see e.g., FIG. 7, along with FIG. 1) between first (voltage at top bold line) and second (voltage at bottom bold line) voltages in retention mode (see FIG. 7, along with prior art FIG. 2, and accompanying disclosure, e.g., para. 0058);
generating a reference voltage (FIG. 11: Vref) that is proportional to absolute temperature (FIGS. 12-14, and para. 0063: … virtual ground for the temperature dependent reference variation …), wherein a magnitude curve of the reference voltage as a function of temperature is based upon a control word (FIG. 7: WL, i.e., the size of 84 (number of WL) determine desired reference voltage); and
maintaining the second voltage as being equal to the reference voltage; generating the control word based upon information about the SRAM device (FIG. 11 and accompanying disclosure, e.g., para. 0063-0065, i.e., Virtual-gnd = g(Vref, T)).
wherein the reference voltage generator comprises:
a current generator configured to generate a current proportional to absolute temperature having a magnitude curve based upon the control word (see e.g., FIGS. 7 and 11-14, and accompanying disclosure).
Nautiyal et al. do not explicitly disclose passing the current through a resistor coupled to ground to form the reference voltage across the resistor.
However, measuring current through resistor in a reference voltage generator is a well-known technology for a type of voltage generator circuit for its purpose.
For support, of the above asserted facts, see for example, Dreesen, e.g., FIG. 8, voltage generator circuit 800 formed a resistor 804.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Dreesen, to the teaching of Nautiyal et al. such that a SRAM device, as taught by Nautiyal et al., utilizes voltage generator circuit formed a resistor, as taught by Dutta et al., for the purpose of adjusting reference voltage level proportional toa temperature (see Dreesen, col. 7, lines 32-36).
Regarding claim 21, Nautiyal et al. and Dreesen et al., as combined, teach the limitations of claim 19.
Nautiyal et al. further teach maintaining the second voltage as being equal to the reference voltage comprises using a low dropout amplifier to maintain the second voltage as being equal to the reference voltage (e.g., FIG. 11, and accompanying disclosure).
Allowable Subject Matter
Claims 2-5 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if overcoming nonstatutory double patenting as indicated above rejection and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-18 are rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUNG IL CHO/Primary Examiner, Art Unit 2825
Prosecution Insights