DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/11/2024 was considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “swing level detector” of claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Regarding claims 18-20, the limitations of “a controller means”, “a plurality of signal means”, and “electrical stress detection means” are being interpreted under 112(f).
Claim Rejections - 35 USC § 112
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 2-4 and 11-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 2 and 11, the claim recites “receiving an indication as to whether the comparison was correctly executed”. The pending application provides no guidance as to how a determination of “whether the comparison was correctly executed” is perform or what method steps are required to achieve such a determination. The limitations as claimed are recited in [0058], [0079], and [0087], however, no steps or guidance are provided in the disclosure as filed 11/11/2024 which reasonably conveys to one skilled in the relevant art how to determine whether a comparison was correctly executed or what metric would indicate that a correction is correctly executed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0287479 (Nam).
Regarding claim 1, Nam teaches a method for measuring electrical stress of a semiconductor package (voltage detector 230 monitors threshold voltages in various voltage transferring paths to determine if the voltage is outside the window of a normal word line voltage or if a defect occurs; see [0100]; see Background/Summary), comprising:
transmitting a test voltage to a swing level detector included within a semiconductor die in a stack of semiconductor dies and electrically coupled to a plurality of signal lines associated with the stack of semiconductor dies (voltage generator 220 outputs a voltage V1-Vi on lines WL1-WLm of a memory cell array 210 comprising stacks of memory cells and voltage detector 230 detects the voltage; see Figs. 1-4; see [0054], [0062], [0099]-[0105]);
causing the swing level detector to compare the test voltage to at least one of a first threshold voltage associated with an overshoot value and a second threshold voltage associated with an undershoot value on a particular signal line of the plurality of signal lines (the threshold voltages of the cells are detected by voltage detector 230 and determines whether the threshold voltages are within a predetermined window range; see [0132]); and
receiving a result of the comparison (the voltage level detector 230 generates a pass/fail signal representing whether the word line is defective according to the detection result and provides the P/F signal to the memory controller; see [0100]; see Fig. 2).
Regarding claim 5, Nam teaches wherein the particular signal line is a first signal line and the method further comprises: selecting a second signal line; and causing the swing level detector to compare the test voltage to at least one of the first threshold voltage associated with an overshoot value and the second threshold voltage associated with an undershoot value on the second signal line of the plurality of signal lines (the voltage level detector sequentially performs the voltage level detecting operation with respect to the plurality of word lines; see [0114]).
Regarding claim 6, Nam teaches further comprising setting the first threshold voltage associated with the overshoot value and the second threshold voltage associated with the undershoot value (the threshold voltages of the cells are determined to be within a predetermined window range, wherein one of ordinary skill in the art would reasonably understand includes setting an upper threshold voltage and a lower threshold voltage to establish the window range; see [0132]; Although not relied on for the pending rejection, US 2022/0252663 is provided for further support as an example of a window comparator to determine if a voltage V is within a window range VTH2 < V < VTH1, and indicates a fault if the voltage V is outside the window range. See [0033]; see Figs. 2 and 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of US 2022/0365128 (Carfore).
Regarding claim 2, Nam fails to teach further comprising receiving an indication as to whether the comparison was correctly executed.
Carfore teaches comprising receiving an indication as to whether the comparison was correctly executed (a verification test verifies if a test is functioning properly and if the system fails to indicate a transducer mismatch among the plurality of transducers 111, 112 in the transducer module 100, that indicates that the mismatch test is not functioning, which indicates a malfunction of the system 100; see [0035]-[0037] and [0064]-[0066], [0073], [0112]-[0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Carfore into Nam in order to gain the advantage of verifying the test function is operating properly to correctly determine an error or proper circuit.
Regarding claims 3-4, Nam and Carfore fail to explicitly teach further comprising storing the result of the comparison responsive to receiving the indication that the comparison was correctly executed; and further comprising causing the swing level detector to compare the test voltage to at least one of a first threshold voltage associated with an overshoot value and a second threshold voltage associated with an undershoot value on a particular signal line of the plurality of signal lines a second time responsive to receiving an indication the comparison was incorrectly executed, however, it would be a matter of common sense for one of ordinary skill in the art to store the result of a comparison if a test was verified to function properly or perform a retest if the test was verified to be performed improperly on incomplete without requiring any undue experimentation or providing any new or undue results.
Claim(s) 10, 14-15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of US 2019/0295669 (Yang).
Regarding claim 10, Nam teaches a semiconductor package (memory system 10; see Figs. 1-4), comprising:
a controller (voltage generator 220; see Figs. 1-2; see [0099]);
a stack of semiconductor dies (memory cell stacks; see Figs. 3-4; see [0054] and [0062]);
a plurality of signal lines communicatively coupling the controller to the stack of semiconductor dies (a plurality of word lines WL1-WLm connected between the voltage generator 220 and the memory array; see Fig. 2); and
electrical stress detection circuitry within the stack of semiconductor dies and communicatively coupled to the plurality of signal lines (voltage detector 230 monitors threshold voltages in various voltage transferring paths to determine if the voltage is outside the window of a normal word line voltage or if a defect occurs; see [0100]; see Background/Summary), wherein the controller is configured to:
transmit a test voltage to the electrical stress detection circuitry associated with at least one semiconductor die (voltage generator 220 outputs a voltage V1-Vi on lines WL1-WLm of a memory cell array 210 comprising stacks of memory cells; see Figs. 1-4; see [0054], [0062], [0099]-[0105]);
cause the electrical stress detection circuitry to compare the test voltage to at least one of a first threshold voltage associated with an overshoot value and a second threshold voltage associated with an undershoot value on a particular signal line of the plurality of signal lines (the threshold voltages of the cells are detected by voltage detector 230 and determines whether the threshold voltages are within a predetermined window range; see [0132]); and
receive a result of the comparison (the voltage level detector 230 generates a pass/fail signal representing whether the word line is defective according to the detection result and provides the P/F signal to the memory controller; see [0100]; see Fig. 2).
Nam fails to explicitly teach electrical stress detection circuitry within each semiconductor die.
Yang teaches electrical stress detection circuitry within each semiconductor die (each memory die 104 comprises memory cells 142 and sense blocks 146; see Fig. 2B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Yang into Nam in order to gain the advantage of memory comprising multiple stacked dies, wherein each die comprises measurement circuitry for monitoring the voltages on the word lines to verify the voltages are supplied at appropriate levels for each die.
Regarding claim 14, Nam further teaches wherein the particular signal line is a first signal line and the controller is further configured to: select a second signal line; and cause the electrical stress detection circuitry to compare the test voltage to at least one of the first threshold voltage associated with an overshoot value and the second threshold voltage associated with an undershoot value on the second signal line of the plurality of signal lines (the voltage level detector sequentially performs the voltage level detecting operation with respect to the plurality of word lines; see [0114]).
Regarding claim 15, Nam further teaches wherein the controller is further configured to set the first threshold voltage associated with the overshoot value and the second threshold voltage associated with the undershoot value (the threshold voltages of the cells are determined to be within a predetermined window range, wherein one of ordinary skill in the art would reasonably understand includes setting an upper threshold voltage and a lower threshold voltage to establish the window range; see [0132]; Although not relied on for the pending rejection, US 2022/0252663 is provided for further support as an example of a window comparator to determine if a voltage V is within a window range VTH2 < V < VTH1, and indicates a fault if the voltage V is outside the window range. See [0033]; see Figs. 2 and 6).
Regarding claim 18, Nam teaches a semiconductor package (memory system 10; see Figs. 1-4), comprising:
a controller means (voltage generator 220; see Figs. 1-2; see [0099]);
a stack of semiconductor dies (memory cell stacks; see Figs. 3-4; see [0054] and [0062]);
a plurality of signal means communicatively coupling the controller means to the stack of semiconductor dies (a plurality of word lines WL1-WLm connected between the voltage generator 220 and the memory array; see Fig. 2); and
electrical stress detection means associated with the stack of semiconductor dies and communicatively coupled to the plurality of signal means (voltage detector 230 monitors threshold voltages in various voltage transferring paths to determine if the voltage is outside the window of a normal word line voltage or if a defect occurs; see [0100]; see Background/Summary), the electrical stress detection means configured to:
receive a test voltage (voltage generator 220 outputs a voltage V1-Vi on lines WL1-WLm of a memory cell array 210 comprising stacks of memory cells, wherein the voltages V1-Vi are received by the voltage detector 230; see Figs. 1-4; see [0054], [0062], [0099]-[0105]);
compare the test voltage to at least one of a first threshold voltage associated with an overshoot value and a second threshold voltage associated with an undershoot value on a particular signal line of the plurality of signal means (the threshold voltages of the cells are detected by voltage detector 230 and determines whether the threshold voltages are within a predetermined window range; see [0132]); and
provide a result of the comparison to the controller means.
Nam fails to explicitly teach an electrical stress detection means associated with each semiconductor die (the voltage level detector 230 generates a pass/fail signal representing whether the word line is defective according to the detection result and provides the P/F signal to the memory controller; see [0100]; see Fig. 2).
Yang teaches electrical stress detection circuitry within each semiconductor die (each memory die 104 comprises memory cells 142 and sense blocks 146; see Fig. 2B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Yang into Nam in order to gain the advantage of memory comprising multiple stacked dies, wherein each die comprises measurement circuitry for monitoring the voltages on the word lines to verify the voltages are supplied at appropriate levels for each die.
Regarding claim 19, Nam further teaches wherein the electrical stress detection means selects another signal line of the plurality of signal means on which to compare the test voltage to the at least the one of the first threshold voltage associated with the overshoot value and the second threshold voltage associated with the undershoot value (the voltage level detector sequentially performs the voltage level detecting operation with respect to the plurality of word lines; see [0114]).
Regarding claim 20, Nam further teaches wherein the electrical stress detection means selects the another signal line of the plurality of signal means based, at least in part, on a signal received from the controller means (the voltage level detector sequentially performs the voltage level detecting operation with respect to the plurality of word lines, such that the next signal line would reasonably be detected based on completion of measuring a previous signal from the controller and/or a signal from a string selection line; see [0114]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of US 2017/0178750 (Kang).
Regarding claim 7, Nam fails to teach further comprising: selecting a particular semiconductor die from the stack of semiconductor dies; and performing the comparison on the particular signal line of the plurality of signal lines associated with the particular semiconductor die.
Kang teaches further comprising: selecting a particular semiconductor die from the stack of semiconductor dies; and performing the comparison on the particular signal line of the plurality of signal lines associated with the particular semiconductor die (selecting one of the memory devices, providing one or more signals through one or more corresponding memory lines, and testing one or more signals of the selected memory device; see [0010]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Kang into Nam in order to gain the advantage of testing a specific line of a specific die, if desired, which would not require any undue experimentation or provide any new or unexpected results.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of US 9,343,165 (Vaysman).
Regarding claim 8, Nam fails to teach further comprising toggling between comparing the test voltage to the first threshold voltage associated with the overshoot value and comparing the test voltage to the second threshold voltage associated with the undershoot value.
Vaysman teaches comprising toggling between comparing the test voltage to the first threshold voltage associated with the overshoot value and comparing the test voltage to the second threshold voltage associated with the undershoot value (“In alternative embodiments, any distortion in the VDD voltage level (e.g. overshoot, undershoot) can be measured and the drop in voltage level is merely an exemplary measurement for an undershoot distortion measurement.” It would be obvious to one of ordinary skill in the art to use a processor 506 of a memory controller 118 which manages operation of the flash memory to switch between detecting an overshoot or an undershoot based on which condition is desired to be detected without requiring any undue experimentation or providing any new or unexpected results.; see col. 7, lines 24-27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Vaysman into Nam in order to gain the advantage of comparing the voltage with a threshold for detecting an overshoot if it is desired to detect an overshoot condition or comparing the voltage with a threshold for detecting an undershoot condition if it is desired as it is well-understood in the art that word lines are susceptible to both overshoots and undershoots.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of US 2008/0191728 (Attalla).
Regarding claim 9, Attalla fails to teach further comprising restricting other operations from being transmitted to other semiconductor dies in the stack of semiconductor dies.
Ayyapureddi teaches further comprising restricting other operations from being transmitted to other semiconductor dies in the stack of semiconductor dies (external devices (e.g., memory controllers) communicating with a conventional downgraded memory device are often restricted to access only a subset of memory regions that are free of manufacture defects; see [0016]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Ayyapureddi into Nam in order to gain the advantage of restricting communication from a die from a stack of memory core dies when a defect on a die affects operability.
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of in view of US 2019/0295669 (Yang), and in further view of US 2022/0365128 (Carfore).
Regarding claims 11-13, Nam fails to teach the limitations of claims 11-13, however, the claims are rejected over Carfore in an equivalent manner as outlined above for claims 2-4, respectively.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of in view of US 2019/0295669 (Yang), and in further view of US 2017/0178750 (Kang).
Regarding claim 16, Nam fails to teach wherein the controller is further configured to: select a particular semiconductor die from the stack of semiconductor dies; and perform the comparison on the particular signal line of the plurality of signal lines associated with the particular semiconductor die, however, claim 16 is rejected over Kang in an equivalent manner as outlined above for claim 7.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0287479 (Nam) in view of in view of US 2019/0295669 (Yang), and in further view of US 2022/0365128 (Carfore).
Regarding claim 17, Nam fails to teach wherein the controller is further configured to switch between comparing the test voltage to the first threshold voltage associated with the overshoot value and comparing the test voltage to the second threshold voltage associated with the undershoot value, however, claim 17 is rejected over Kang in an equivalent manner as outlined above for claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 with numerous references which detect overshoot (overvoltage) of undershoot (undervoltage) conditions on lines of memory circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN LEE YENINAS whose telephone number is (571)270-0372. The examiner can normally be reached M - F 10 - 6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN L YENINAS/Primary Examiner, Art Unit 2858
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