Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed November 11, 2024.
Status of claims to be treated in this office action:
a. Independent: 1
b. Pending: 1-11
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
On p. 5, lines 16, 18, and 19, change “concept” to “concepts”.
On p. 8, lines 12 and 17, make the following change:
“selected word line from the selected memory block”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 20160124809 A1) in view of Forhan et al. (US Pub. 20080040646 A1; “Forhan”).
Regarding independent claim 1, Lee discloses a semiconductor device (Fig. 8: storage device 100; [0050]) comprising:
a memory cell array (memory cell array 110; [0091]) including a plurality of planes (Fig. 14: “plains” 1-4; [0122]: Referring to FIG. 14, a program operation is performed on normal data A, B, and C at plains Plain1 to Plain3 and a program operation is performed on parity data P at another plain Plain4; also see [0093]: Each of the memory blocks BLK1 to BLKz includes a plurality of strings…arranged on the substrate in a third direction perpendicular to a plane formed in the first direction and the second direction); and
a plurality of read and write circuits (Fig. 8: circuits within I/O circuit 140) corresponding to the plurality of planes ([0098]: The I/O circuit 140 includes a plurality of page buffers to store data to be programmed during a program operation or to store read data during a read operation…During a program operation, the data stored in the page buffers may be programmed into a page corresponding to a selected memory block through bitlines BLs. During a read operation, the data read from the page corresponding to the selected memory block may be stored in the page buffers through the bitlines BLs), respectively,
wherein any one of the read and write circuits generates recovery data ([0012]: the parity operation may be performed at a page buffer in the second nonvolatile memory device) based on data received from a controller through a channel ([0021]: the first, second, and third nonvolatile memories may be connected to the memory controller through a single channel).
Lee does not disclose:
data sequentially received
However, Forhan teaches:
data sequentially received ([0014]: if it is desirable for the number of buffers used to be minimized, then read requests must be serialized to ensure that each incoming data value is scaled by the appropriate constant)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Forhan to Lee wherein data is sequentially received in order to implement circuit design that increases parallelism, reduce the number of buffers, and increase performance (Forhan, [0016]).
Regarding claim 2, Lee and Forhan together disclose the limitations of claim 1. Forhan discloses sequential data transfer. Further, through Lee:
wherein any one of the read and write circuits ([0012]) receives first and second data through the channel, generates the recovery data by performing an exclusive-OR (XOR) operation on the first and second data, and programs the recovery data into a corresponding plane ([0122]: Referring to FIG. 14, a program operation is performed on normal data A, B, and C at plains Plain1 to Plain3 and a program operation is performed on parity data P at another plain Plain4. The parity data is a result value of an XOR operation on the data A, B, and C. Although not shown, the XOR operation may be performed in a page buffer).
Regarding claim 3, Lee and Forhan together disclose the limitations of claim 2. Further, through Lee:
wherein the read and write circuits ([0012]) comprise:
a main buffer connected to the corresponding plane through a plurality of bit lines ([0098]: Each of the page buffers may include a plurality of latches LAT1 to LATk (see FIG. 6)…During a read operation, the data read from the page corresponding to the selected memory block may be stored in the page buffers through the bitlines BLs);
a cache buffer connected to the main buffer (in reference to Fig. 6, per [0077]: some of the latches LAT1 to LATk (e.g., LAT1 and LATk) may be used for a read operation. For example, a read operation may be performed only using a sensing latch and a cache latch during an XOR operation); and
a data generator connected to the cache buffer ([0110]: The parity p may be generated and stored by a latch operation of a page buffer (see FIG. 6) connected to a bitline BL. When certain data need to be restored, data restoration may be performed based on the other data and a parity).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over
Lee (US Pub. 20160124809 A1) and Forhan (US Pub. 20080040646 A1) as applied to claim 3 above and further in view of Chai (US Pub. 20220328107 A1) and Bruce et al. (US Pub. 20210357119 A1; “Bruce”).
Regarding claim 4, Lee and Forhan together disclose the limitations of claim 3, and further through Lee:
wherein the main buffer comprises a plurality of main latches connected to the plurality of bit lines ([0098]), respectively,
the data generator ([0110])
Neither Lee nor Forhan disclose:
the cache buffer includes a plurality of cache latches connected to the plurality of main latches, respectively,
the data generator includes a plurality of XOR scramblers connected to the plurality of cache latches, respectively, and
each of the plurality of XOR scramblers selectively transmits bit data input from a corresponding input and output (input/output) line to a corresponding cache latch in response to a control signal of a first state.
However, Chai teaches:
the cache buffer (Fig. 19: RAM 210; [0194]: The RAM 210 is used as at least one of an operation memory of the processing unit 220, a cache memory between the semiconductor memory device 100 and the host Host, and a buffer memory between the semiconductor memory device 100 and the host Host) includes a plurality of cache latches connected to the plurality of main latches ([0176]: In step S340, the first target bit data of the sense out node is stored in each of the plurality of cache latches, by applying the first control signal to the plurality of cache latches. The “cache latch” shown in FIG. 17 may mean the third latch L3 shown in FIG. 16. Examiner concludes that the cache latches are part of the buffer and therefore connected to it), respectively,
a plurality of XOR scramblers connected to the plurality of cache latches ([0176]), respectively ([0163]: the second latch circuit LC2 may perform an XOR operation on the result of sensing operation by the second voltage V2 masked to the target state, and bit data stored in the third latch circuit LC3. And then the second latch circuit LC2 may store the result of the XOR operation. Examiner concludes that the plurality of second latches, which perform the XOR operation, are respectively connected to the plurality of third latches, which are cache latches), and
each of the plurality of XOR scramblers selectively transmits bit data input from a corresponding input and output (input/output) line to a corresponding cache latch in response to a control signal of a first state ([0168]: generating first target bit data from the first bit data by applying a control signal corresponding to the target state to the plurality of page buffers (S330), storing the first target bit data of the sense out node in each of the plurality of cache latches, by applying a first control signal to the plurality of cache latches).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chai to modified Lee wherein the cache buffer includes a plurality of cache latches connected to the plurality of main latches, respectively, there is a plurality of XOR scramblers connected to the plurality of cache latches, respectively, and each of the plurality of XOR scramblers selectively transmits bit data input from a corresponding input and output (input/output) line to a corresponding cache latch in response to a control signal of a first state in order to provide a memory device that can quickly detect the threshold voltage distribution for each state to speed up operation (Chai, [0030]).
Chai does not explicitly disclose:
a plurality of XOR scramblers
However, Bruce teaches:
a plurality of XOR scramblers (Fig. 1: XOR/Cipher engine module 110; [0080]; [0010]: The XOR/Cipher engine module embeds XOR engines to perform RAID parity computation to provide data redundancy)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Bruce to modified Lee wherein there are a plurality of XOR scramblers in order to provide a controller device that is secure, reliable, scalable, and capable of in-storage processing (Bruce, [0306]-[0307]).
Regarding claim 5, Lee, Forhan, Chai, and Bruce together disclose the limitations of claim 4. Bruce discloses a plurality of XOR scramblers, and further through Chai:
wherein each of the plurality of XOR scramblers performs an XOR operation on the bit data input from the corresponding input/output line and bit data stored in a corresponding cache latch in response to the control signal of a second state ([0168]: storing XOR operation data for the first target bit data and the second target bit data in each of the plurality of cache latches, by applying a second control signal to the plurality of cache latches (S380)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chai to modified Lee wherein each of the plurality of XOR scramblers performs an XOR operation on the bit data input from the corresponding input/output line and bit data stored in a corresponding cache latch in response to the control signal of a second state in order to provide a memory device that can quickly detect the threshold voltage distribution for each state to speed up operation (Chai, [0030]).
Regarding claim 6, Lee, Forhan, Chai, and Bruce together disclose the limitations of claim 5. Bruce discloses a plurality of XOR scramblers, and further through Chai:
wherein each of the plurality of XOR scramblers stores bit data generated as a result of the XOR operation in the corresponding cache latch ([0168]: storing XOR operation data for the first target bit data and the second target bit data in each of the plurality of cache latches…counting the number of bits of “1” stored in the plurality of cache latches (S390)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chai to modified Lee wherein each of the plurality of XOR scramblers stores bit data generated as a result of the XOR operation in the corresponding cache latch in order to provide a memory device that can quickly detect the threshold voltage distribution for each state to speed up operation (Chai, [0030]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over
Lee (US Pub. 20160124809 A1), Forhan (US Pub. 20080040646 A1), Chai (US Pub. 20220328107 A1) and Bruce (US Pub. 20210357119 A1) as applied to claim 6 above and further in view of Vasiliev (US Pat. 6574774 B1), Fredrickson et al. (US Pat. 5805799 A; “Fredrickson”), and Detwiler et al. (US Pub. 20220197646 A1; “Detwiler”).
Regarding claim 7, Lee, Forhan, Chai, and Bruce together disclose the limitations of claim 6. Bruce discloses a plurality of XOR scramblers.
Neither Lee, Forhan, Chai, nor Bruce discloses:
wherein each of the XOR scramblers comprises a multiplexer and an XOR gate,
a first input, a second input, and an output of the multiplexer are connected to the corresponding input/output line, an output of the XOR gate, and the corresponding cache latch, respectively, and
a first input and a second input of the XOR gate are connected to the corresponding input/output line and the corresponding cache latch, respectively.
However, Vasiliev teaches:
wherein XOR scramblers (Fig. 1 or Fig. 2: ECC encoder/decoder 106; col. 2, lines 26-27) comprises a multiplexer (multiplexer or switch 108; col. 2, line 28) and an XOR gate (exclusive-or (XOR) circuit 112; col. 2, line 40),
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Vasiliev to modified Lee wherein the XOR scrambler comprises a multiplexer and an XOR gate in order to distinguish uncorrectable errors from misidentification of block addresses (Vasiliev, col. 3, lines 55-63).
Also, through Fredrickson:
a first input, a second input, and an output of the multiplexer (Fig. 1: multiplexer 106; col. 5, lines 41-42) are connected to the corresponding input/output line (the first input of multiplexer 106 is connected to FIFO 102; col. 4, line 61: The FIFO 102 is used to buffer the incoming data words), an output of the XOR gate (the second input of multiplexer 106 is connected to adder circuit 103; col. 5, lines 16-18: adder circuit 103, which in practice may be implemented as a parallel array of 16 XOR gates), and the corresponding cache latch, respectively (the output of multiplexer 106 is connected to block buffer 108; col. 4, lines 63-66: block buffer 108 functions as a cache memory to temporarily store a transferred sequence of data sectors prior to the further transfer of the sectors to the sequencer 109), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fredrickson to modified Lee wherein a first input, a second input, and an output of the multiplexer are connected to the corresponding input/output line, an output of the XOR gate, and the corresponding cache latch, respectively, in order to incorporate logical block address information into the data integrity block to prevent misidentification of data blocks during block transfer (Fredrickson, col. 2, lines 49-52).
Also, through Detwiler:
a first input and a second input of the XOR gate (Fig. 6: XOR gate 650; [0056]) are connected to the corresponding input/output line (data valid input INVLD is connected to second status circuit 628, which is connected to XOR gate 650) and the corresponding cache latch (first status circuit 622; [0052]: The first status circuit 622 includes a first status storage circuit 626, also referred to as a first status latch 626), respectively.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Detwiler to modified Lee wherein a first input and a second input of the XOR gate are connected to the corresponding input/output line and the corresponding cache latch, respectively in order to reduce power consumption during high-frequency data transfer (Detwiler, [0005]).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over
Lee (US Pub. 20160124809 A1), Forhan (US Pub. 20080040646 A1), Chai (US Pub. 20220328107 A1), Bruce (US Pub. 20210357119 A1), Vasiliev (US Pat. 6574774 B1), Fredrickson (US Pat. 5805799 A), and Detwiler (US Pub. 20220197646 A1) as applied to claim 7 above and further in view of Hara et al. (US Pub. 20090319840 A1; “Hara”).
Regarding claim 8, Lee, Forhan, Chai, Bruce, Vasiliev, Fredrickson, and Detwiler together disclose the limitations of claim 7. Neither Lee, Forhan, Chai, Bruce, Vasiliev, Fredrickson, nor Detwiler discloses:
wherein the first input of the multiplexer is connected to the output of the multiplexer in response to the control signal of the first state.
However, Hara teaches:
wherein the first input of the multiplexer (Fig. 9: multiplexer 43; [0126]) is connected to the output of the multiplexer in response to the control signal of the first state ([0126]: In accordance with a control signal (ECCTEST) which is input from the main state machine 33, the multiplexer 43 effects switching between the output of the parity syndrome 42 and the output from the ECC buffer 24, and delivers the output, which is selected by switching, to the error position decoder 44. Examiner asserts that the first input of multiplexer 43 may be “the output of the parity syndrome 42”).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hara to modified Lee wherein the first input of the multiplexer is connected to the output of the multiplexer in response to the control signal of the first state in order to implement a memory device that can test itself to increase simultaneous measurements (Hara, [0034]).
Regarding claim 9, Lee, Forhan, Chai, Bruce, Vasiliev, Fredrickson, and Detwiler together disclose the limitations of claim 7. Neither Lee, Forhan, Chai, Bruce, Vasiliev, Fredrickson, nor Detwiler discloses:
wherein the second input of the multiplexer is connected to the output of the multiplexer in response to the control signal of the second state.
However, Hara teaches:
wherein the second input of the multiplexer is connected to the output of the multiplexer in response to the control signal of the second state ([0126]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hara to modified Lee wherein the second input of the multiplexer is connected to the output of the multiplexer in response to the control signal of the second state in order to implement a memory device that can test itself to increase simultaneous measurements (Hara, [0034]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over
Lee (US Pub. 20160124809 A1), Forhan (US Pub. 20080040646 A1), Chai (US Pub. 20220328107 A1), and Bruce (US Pub. 20210357119 A1) as applied to claim 4 above and further in view of Bonen (US Pub. 20180067852 A1).
Regarding claim 10, Lee, Forhan, Chai, and Bruce together disclose the limitations of claim 4. Bruce discloses a plurality of XOR scramblers. Neither Lee, Forhan, Chai, nor Bruce discloses:
wherein the control signal of the first state is applied to a first XOR scrambler corresponding to a first address included in a read command received from the controller, in response to the first address.
However, Bonen teaches:
wherein the control signal of the first state (in reference to Fig. 4B, per [0049]: control passes to operation 470 and the memory controller 122 determines whether the data unit retrieved in operation 452 is equal to the scramble code generated by the scramble code generator 515 in operation 422. If, at operation 470 the data equals the scrambler code then control passes to operation 472 and the memory controller 122 returns a data unit comprising the scramble code generated by the scramble code generator 515 in operation 422 in response to the read request. Examiner asserts that the first state could be “yes” to operation 470) is applied to a first XOR scrambler ([0042]: A third example of operations to implement a polarity based transfer function will be described with reference to FIGS. 4A and 4B and FIGS. 5A-5B. In the third example the transfer function incorporates a data scrambler…an XOR operator to form scrambled data from data and code 525) corresponding to a first address included in a read command received from the controller ([0048]: Referring to FIG. 4B, at operation 450 the controller 122 receives a read request for the data unit written in FIG. 4A), in response to the first address ([0048]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Bonen to modified Lee wherein the control signal of the first state is applied to a first XOR scrambler corresponding to a first address included in a read command received from the controller, in response to the first address in order to reduce power consumption by replacing logic zeroes with logic ones in write data units (Bonen, [0015]).
Regarding claim 11, Lee, Forhan, Chai, Bruce, and Bonen together disclose the limitations of claim 10. Further, through Bonen:
wherein the control signal of the second state is applied to a second XOR scrambler corresponding to a second address included in the read command received from the controller, in response to the second address ([0050]: By contrast, if at operation 470 the data is not equals the scrambler code then control passes to operation 480 and the memory controller 122 generates an unscrambled data unit and at operation 482 the controller 122 returns the data retrieved from memory in response to the read request).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Bonen to modified Lee wherein the control signal of the second state is applied to a second XOR scrambler corresponding to a second address included in the read command received from the controller, in response to the second address in order to reduce power consumption by replacing logic zeroes with logic ones in write data units (Bonen, [0015]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Lee (US Pub. 20140281174 A1): paras. [0014] and [0161] and Fig. 16 are relevant to claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
/HAN YANG/Primary Examiner, Art Unit 2824
5/28/2026
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