DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/10/2026, 04/27/2026 and 01/28/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 & 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Perreault et al. (US 20150084701 A1, of record, hereinafter Perreault).
Regarding claim 1:
Perreault discloses in Figs. 7, 9 & 11, a tracker circuit comprising:
a pre-regulator circuit (elements S2, S2, S1c and S2c, inductor L) configured to convert an input voltage into a regulated voltage using a power inductor (inductor L);
a switched-capacitor circuit (Fig. 9, switched-capacitor 14’) configured to generate a plurality of discrete voltages (Fig. 9, voltages V1-V4) based on the regulated voltage;
a power modulation circuit (Fig. 11, Output switching stage and switch sets as shown in Fig. 6) configured to select at least one voltage from the plurality of discrete voltages that is used to generate a first supply voltage (V1), the first supply voltage being output to a first output terminal (V1 terminal); and
one or more bypass paths (Fig. 6, path from switch set #1 to Vmod1 for example) configured to bypass at least the switched-capacitor circuit and the power modulation circuit, and provide a second supply voltage (VN) from the pre-regulator circuit to a second output terminal (VN terminal), the second supply voltage being output by the second output terminal.
Regarding claim 19:
Perreault discloses in Figs. 7, 9 & 11, a voltage supply method comprising: converting an input voltage (Vin) into a regulated voltage using a power inductor (inductor L of Fig. 9); generating (switch capacitor) a plurality of discrete voltages based on the regulated voltage; selecting (output switching stage of Fig. 7) at least one voltage from the plurality of discrete voltages based on an envelope signal of a radio frequency signal, the at least one voltage being supplied to a first amplifier (see paragraph 0040-0041, plurality of power amplifier); and skipping the generating of the plurality of discrete voltages and the selecting of the at least one voltage (Switch set #1 to #N), and supplying the input voltage or the regulated voltage to a second amplifier (paragraph 0043, the output switching state voltage V.sub.mod may be applied directly to a power amplifier).
Regarding claim 20:
Perreault discloses in Figs. 7, 9 & 1, wherein: when the input voltage (Vin) is higher than a predetermined voltage, the regulated voltage is supplied to the second amplifier (see paragraph 0040-0041, plurality of power amplifier); and when the input voltage is not higher than the predetermined voltage, the converting of the input voltage into the regulated voltage is skipped, and the input voltage is supplied to the second amplifier (paragraph 0043, the output switching state voltage Vmod may be applied directly to a power amplifier and additional linear regulation and/or amplification to provide continuous output voltage control or to control the transitions between levels. Linear regulation and also see paragraph 0033, higher voltages V.sub.2-V.sub.4 related ratiometrically as described previously, one can identify switch voltage blocking requirements).
Allowable Subject Matter
Claims 2-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2, 7-8 are allowable since the closest prior art does not disclose wherein the one or more bypass paths comprises a first bypass path that is configured to bypass the switched-capacitor circuit and the power modulation circuit, and to provide the second supply voltage that is generated on a path between the power inductor and the switched-capacitor circuit to the second output terminal.
Claims 3 & 4-6 are allowable since the closest prior art does not disclose wherein the one or more bypass paths comprises a second bypass path that is configured to bypass the power inductor, the switched-capacitor circuit, and the power modulation circuit, and to provide the second supply voltage that is generated on a path between a direct current power source and the power inductor to the second output terminal.
Claim 9 is allowable since the closest prior art does not disclose wherein: the one or more bypass paths further include a third bypass path configured to bypass the power inductor based on a switch along the third bypass path, and the third bypass path is configured to connect a first path between a direct current power source and the power inductor to a second path between the power inductor and the switched-capacitor circuit based on the switch.
Claims 10-18 are allowable.
The following is an examiner’s statement of reasons for allowance:
Independent claim 10 is allowable since the closest prior art of record (i.e. Perreault) is not explicit in teaching a first end of the first switch and a first end of the third switch are connected to the first electrode, a first end of the second switch and a first end of the fourth switch are connected to the second electrode, a first end of the fifth switch and a first end of the seventh switch are connected to the third electrode, a first end of the sixth switch and a first end of the eighth switch are connected to the fourth electrode, a second end of the first switch, a second end of the second switch, a second end of the fifth switch, and a second end of the sixth switch are connected to each other, a second end of the third switch is connected to a second end of the seventh switch, a second end of the fourth switch is connected to a second end of the eighth switch, wherein the power modulation circuit includes: a ninth switch connected between the first output terminal and the second end of the first switch, the second end of the second switch, the second end of the fifth switch, and the second end of the sixth switch, and a tenth switch connected between the first output terminal and the second end of the third switch and the second end of the seventh switch, wherein the pre-regulator circuit includes: an eleventh switch connected between the input terminal and a first end of a power inductor, and a twelfth switch connected between the first end of the power inductor and ground, wherein a second end of the power inductor is connected to the second end of the first switch, the second end of the second switch, the second end of the fifth switch, and the second end of the sixth switch.
Claims 11-18 are allowable because they depend on claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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