DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement filed 11/20/2024 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because listed foreign patents and non-patent literature were not provided with the disclosure. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
The information disclosure statement filed 11/20/2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The first sentence of the abstract should be omitted.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 21 and claim 29 of copending Application No. 18/331746 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 9 of U.S. Patent No.11894045 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and claim 11 of U.S. Patent No. 11675538 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and claim 17 of U.S. Patent No. 11276457 B2 in view La Fratta, US 20160064045 A1.
Claim 1 of the at-issue application is a broader recitation of claim 1 and claim 17 of US 11276457 B2, but does not appear to recite one or more arrays of memory cells.
La Fretta recites one or more arrays of memory cells (see La Fretta Para [0031]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by US 11894045 B2, may use particular number of arrays, as disclosed by La Fretta. The inventions are well known variants of devices which control signals to memory arrays, and the combination of known invention which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is La Fretta's attempt efficiently implement logical and/or arithmetic operations (see La Fretta Para [0027]).
Claim 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 11276457 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and claim 9 of U.S. Patent No. 11016706 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 11016706 B2 in view La Fratta, US 20160064045 A1.
Claim 1 of the at-issue application is a broader recitation of claim 16 of US 11276457 B2, but does not appear to recite one or more arrays of memory cells.
La Fretta recites one or more arrays of memory cells (see La Fretta Para [0031]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by US 11894045 B2, may use particular number of arrays, as disclosed by La Fretta. The inventions are well known variants of devices which control signals to memory arrays, and the combination of known invention which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is La Fretta's attempt efficiently implement logical and/or arithmetic operations (see La Fretta Para [0027]).
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10741239 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 10741239 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 12 of U.S. Patent No. 10346092 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 23 of U.S. Patent No. 10346092 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter is substantially the same, but broadened in scope.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 6 recite(s) the language (emphasis added) “the compute component based on a selected a logical operation that is associated with”, where there appears to be a typo which makes unclear the scope of the limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-9, 11-14, and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by La Fratta, US 20160064045 A1.
As to claim 1, La Fretta discloses a processor-in-memory capable device (see La Fretta Fig 1 and Para [0028]), comprising:
one or more arrays of memory cells (see La Fretta Fig 1 Ref 130); a compute component (see La Fretta Fig 3 Ref 241 and Para [0049]); and control circuitry (see La Fretta Fig 1 Refs 140 and 150 and Para [0049]) coupled with the one or more arrays of memory cells and the compute component and configured to cause the device to:
receive a command instruction set (see La Fretta Fig 4 Ref 441 and Paras [0037] and [0070]) to initiate performance of a plurality of compute operations (see La Fretta Fig 5 Ref 550 and Para [0042]); coordinate the performance of the plurality of compute operations; and decode the command instruction set (see La Fretta Para [0037]) into a plurality of microcode instructions that are executable by the compute component (see La Fretta Fig 4 Ref 489 and Para [0070]).
As to claim 2, La Fretta discloses the device of claim 1, wherein
the control circuitry is configured to cause the device to: decode the command instruction set into at least a subset of the plurality of microcode instructions (see La Fretta Fig 7) that are executable in parallel by the compute component (see La Fretta Para [0105]).
As to claim 5, La Fretta discloses the device of claim 1, wherein,
to coordinate the performance of the plurality of compute operations, the control circuitry is configured to cause the device to:
control continuity of one or more pass gates (see La Fretta Fig 5 Refs 518-1 and 518-2) coupled with the compute component based on a selected logical operation that is associated with at least one of the plurality of compute operations (see La Fretta Fig 5 Refs AND and ANDinv and Para [0077]).
As to claim 6, La Fretta discloses the device of claim 1, wherein,
to coordinate the performance of the plurality of compute operations, the control circuitry is configured to cause the device to: control continuity of one or more swap transistors (see La Fretta Fig 13 Ref 1342) coupled with the compute component based on a selected a logical operation that is associated with at least one of the plurality of compute operations (see La Fretta Fig 14 and Para [0176]).
As to claim 7, La Fretta discloses the device of claim 1, wherein
the control circuitry comprises: a row address strobe manager (see La Fretta Fig 4 Refs 494 and 478) configured to coordinate timing of a sequence of compute sub-operations (see La Fretta Para [0069]) performed using a row address strobe component coupled with the one or more arrays of memory cells (see La Fretta Fig 4 Ref 479).
As to claim 8, La Fretta discloses the device of claim 7, wherein
the control circuitry is separate from decoder circuitry (see La Fretta Fig 1 Ref 142) used to perform read and write operations on the one or more arrays of memory cells (see La Fretta Para [0036]).
As to claim 9, La Fretta discloses the device of claim 1, wherein
to receive the command instruction set, the control circuitry is configured to cause the device to: receive, via a sideband channel (see La Fretta Fig 1 Ref 154), the command instruction set, wherein
the command instruction set is different from commands for read and write operations on the one or more arrays of memory cells (see La Fretta Para [0037]-[0039]).
As to claim 11, La Fretta discloses the device of claim 1, wherein
the control circuitry is separate from registers (see La Fretta Fig 1 Ref 142 and Para [0036]) used to control read and write access requests for the one or more arrays of memory cells (see La Fretta Fig 1 Ref 142 and Para [0036]).
As to claim 12, La Fretta discloses the device of claim 1, wherein
the plurality of compute operations comprise at least a logical operation performed using the compute component (see La Fretta Para [0039]).
As to claim 13, La Fretta discloses the device of claim 1, wherein
the compute component is included in sensing circuitry coupled with the one or more arrays of memory cells (see La Fretta Para [0039]).
As to claim 14, La Fretta discloses a method by a processor-in-memory capable device (see La Fretta Fig 1 and Para [0028]), comprising:
receiving, by control circuitry of the device, a command instruction set (see La Fretta Fig 4 Ref 441 and Paras [0037] and [0070]) to initiate performance of a plurality of compute operations; coordinating the performance of the plurality of compute operations (see La Fretta Fig 5 Ref 550 and Para [0042]) by a compute component of the device (see La Fretta Fig 3 Ref 241 and Para [0049]); decoding the command instruction set into a plurality of microcode instructions; and executing (see La Fretta Para [0037]), by the compute component of the device, the plurality of microcode instructions based at least in part on decoding the command instruction set (see La Fretta Fig 4 Ref 489 and Para [0070]).
As to claim 16, La Fretta discloses the method of claim 14.
Claim 16 recites substantially the same limitations as claim 5.
All the limitations of claim 16 have already been disclosed by La Fretta in claim 5 above.
As to claim 17, La Fretta discloses the method of claim 14.
Claim 17 recites substantially the same limitations as claim 6.
All the limitations of claim 17 have already been disclosed by La Fretta in claim 6 above.
As to claim 18, La Fretta discloses the method of claim 14.
Claim 18 recites substantially the same limitations as claim 7.
All the limitations of claim 18 have already been disclosed by La Fretta in claim 7 above.
As to claim 19, La Fretta discloses the method of claim 14.
Claim 19 recites substantially the same limitations as claim 9.
All the limitations of claim 19 have already been disclosed by La Fretta in claim 9 above.
As to claim 20, La Fretta discloses the method of claim 14, wherein
the compute component is included in sensing circuitry coupled with one or more arrays of memory cells of the device (see La Fretta Para [0031]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over La Fratta, US 20160064045 A1, in view of Willcock, US 20170277440 A1.
As to claim 3, La Fretta discloses the device of claim 1, wherein,
to coordinate the performance of the plurality of compute operations, the control circuitry is configured to cause the device to: organize usage of a sense amplifier of the device for an access operation on the one or more arrays of memory cells and a compute operation of the plurality of compute operations (see La Fretta Fig 7).
La Fretta does not appear to explicitly disclose prevent simultaneous usage of a sense amplifier of the device for an access operation on the one or more arrays of memory cells and a compute operation of the plurality of compute operations.
Willcock discloses prevent simultaneous usage of a sense amplifier of the device for an access operation on the one or more arrays of memory cells and a compute operation of the plurality of compute operations (see Willcock Paras [0105] and [0106]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a device, as disclosed by La Fretta, may implement particular access operations, as disclosed by Willcock. The inventions are well known variants of in-memory processing and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Willcock’s attempt to save time and power (see Willcock Para [0005]).
As to claim 4, La Fretta discloses the device of claim 1, wherein,
to coordinate the performance of the plurality of compute operations, the control circuitry is configured to cause the device to:
prevent simultaneous usage of a sense amplifier of the device for two compute operations of the plurality of compute operations (see Willcock Paras [0105] and [0106]).
As to claim 15, La Fretta discloses the method of claim 14.
Claim 15 recites substantially the same limitations as claim 3.
All the limitations of claim 16 have already been disclosed by La Fretta and Willcock in claim 3 above.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over La Fratta, US 20160064045 A1, in view of Murphy, US 20170263306 A1.
As to claim 10, La Fretta discloses the device of claim 1, wherein,
the control circuitry comprises a controller configured to decode the command instruction set comprising controller instructions into the plurality of microcode instructions.
La Fretta does not appear to explicitly disclose a very large instruction word (VLIW) type controller.
Murphy discloses a very large instruction word (VLIW) type controller (see Murphy Para [0036]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a device, as disclosed by La Fretta, may implement particular instructions, as disclosed by Murphy. The inventions are well known variants of in-memory processing and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Murphy’s attempt to save time and power (see Murphy Para [0005]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Potash, US 20170083434 A1 discloses a command instruction set comprising a VLIW.
Boswell, US 20180321938 A1 discloses a processor-in-memory capable device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 06/04/2026
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