DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application discloses and claims only subject matter disclosed in prior Application No. 18/412,605, filed 11/11/24, and names the inventor or at least one joint inventor named in the prior application. Accordingly, this application may constitute a continuation or divisional.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15-20 of U.S. Patent No. 12,166,084 B2 (Vellianitis et al). Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter, claims 1-12, of the instant application, may be found in claims 15-20 of the patent.
Regarding claim 1, Vellianitis et al 084’ discloses a transistor, comprising: a semiconductor channel layer; a gate structure disposed over the semiconductor channel layer; an insulating layer disposed over the gate structure and the semiconductor channel layer; a source and a drain disposed over the semiconductor channel layer and in the insulating layer; and a binary oxide layer sandwiched between the semiconductor channel layer and the source and the drain, wherein at least one metal element contained in a metal oxide material of the binary oxide layer is the same as that contained in a material of the semiconductor channel layer (claims 15 and 16).
Regarding claim 2, Vellianitis et al 084’ discloses wherein the metal oxide material of the binary oxide layer includes gallium oxide, indium oxide, zinc oxide, titanium oxide, aluminum oxide, or a combination thereof, and the material of the semiconductor channel layer includes gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), zinc tin oxide (ZTO), or a combination thereof (claim 16).
Regarding claim 3, Vellianitis et al 084’ discloses wherein the binary oxide layer is in contact with the semiconductor channel layer and the source and the drain (claims 17 and 18).
Regarding claim 4, Vellianitis et al 084’ discloses wherein the binary oxide layer extends on a top surface of the semiconductor channel layer (claim 17).
Regarding claim 5, Vellianitis et al 084’ discloses wherein the binary oxide layer surrounds the source and the drain and contacts bottom surfaces and sidewalls of the source and the drain (claim 18).
Regarding claim 6, Vellianitis et al 084’ discloses wherein the binary oxide layer extends over and contacts three sides of the semiconductor channel layer, and the source and the drain cover the three sides of the semiconductor channel layer with the binary oxide layer located there-between (claim 19).
Regarding claim 7, Vellianitis et al 084’ discloses wherein the source and the drain are located at opposite sides of the gate structure, and the binary oxide layer extends from the source to the drain (claim 20).
Regarding claim 8, Vellianitis et al 084’ discloses a transistor, comprising: a semiconductor layer; a gate structure disposed over the semiconductor layer and covering at least three sides of the semiconductor layer; source and drain terminals disposed over the semiconductor layer and covering the at least three sides of the semiconductor layer; and a binary oxide layer disposed between the at least three sides of the semiconductor layer and the source and drain terminals, wherein at least one metal element contained in a metal oxide material of the binary oxide layer is the same as that contained in a material of the semiconductor layer (claims 15 and 16).
Regarding claim 9, Vellianitis et al 084’ discloses wherein the metal oxide material of the binary oxide layer includes gallium oxide, indium oxide, zinc oxide, titanium oxide, aluminum oxide, or a combination thereof, and the material of the semiconductor channel layer includes gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), zinc tin oxide (ZTO), or a combination thereof (claim 16).
Regarding claim 10, Vellianitis et al 084’ discloses wherein the binary oxide layer extends over the at least three sides of the semiconductor layer, and the binary oxide layer contacts the source and drain terminals without being in contact with the gate structure (claims 17-19).
Regarding claim 11, Vellianitis et al 084’ discloses wherein the binary oxide layer wraps and contacts bottom surfaces and sidewalls of the source and drain terminals and exposes top surfaces of the source and drain terminals (claim 18).
Regarding claim 12, Vellianitis et al 084’ discloses wherein binary oxide layer contacts the at least three sides of the semiconductor layer, and the source terminal, the gate structure and the drain terminal are located directly on the binary oxide layer (claims 17-19).
Claim 13 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 16 of U.S. Patent No. 12,166,084 B2 (Vellianitis et al) in view of Samachisa et al (US 2012/0147650 A1).
Regarding claim 13, Vellianitis et al 084’ discloses source and drain terminals (claim 15).
However, Vellianitis et al 084’ does not disclose wherein the source and drain terminals include metallic contacts.
Samachisa et al discloses wherein the source and drain terminals include metallic contacts (paragraph 0250).
It would have been obvious to modify Vellianitis et al 084’ with the teachings of Samachisa et al for the purpose of including the source and drain materials with metallic contacts in order to make electrical connections in CMOS devices.
Allowable Subject Matter
Claims 14-20 are allowed over the prior art of record.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest a method of manufacturing a transistor, comprising: wherein the semiconductor channel layer and the binary oxide layer are sequentially formed in a same deposition process, and at least one metal element contained in the metal oxide material of the binary oxide layer is the same as that contained in a material of the semiconductor channel layer; forming a gate structure over the semiconductor channel layer and the binary oxide layer; forming an insulating layer over the gate structure, the binary oxide layer and the semiconductor channel layer; and forming a source and a drain beside the gate structure, on the binary oxide layer and over the semiconductor channel layer, wherein the binary oxide layer is sandwiched between the semiconductor channel layer and the source and the drain as described in independent claim 14 and in the context of its recited process, along with its depending claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
mdh
October 6, 2026
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