Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Continuation filed on 11/12/2024.
Claims 1-20 are pending for this examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Examiner notes that in the IDS submitted 3/12/2025, the reference cited under the Foreign Patent Documents section of WO 20100142987 A1 was not considered as there was no corresponding copy of this reference found in the IFW for this application or in the parent case of this application.
Objections - Specification
The disclosure is objected to because of the following informalities:
In Paragraph 0004, line 1 of Applicant’s Specification, Examiner believes “course-grained” is a typo and should be amended to --coarse-grained--.
Appropriate correction is required.
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
The claims do not fall within at least one of the four categories of patent eligible subject matter because the “system”, “host computer” and the “optimization module” in claim 1 are defined in Applicant’s Specification Paragraph 0143, where it specifically indicates that terms such as “apparatus”, “circuit”, “circuitry”, “module”, “computer”, “logic”, “FPGA”, “unit”, and “system” can be taken as entirely hardware embodiment, entirely software embodiment, or an embodiment combining software and hardware aspects. As such, under the broadest reasonable interpretation in view of Applicant’s specification, claim 1 can be interpreted as a purely software embodiment without sufficient definite structure for the purposes of this examination, i.e. “a ‘system’ comprising a host ‘computer’ comprising an ‘optimization module’ configured to conduct a method” being equated to a system comprising host software comprising an optimization software configured to conduct a method. As such despite being an intended system claim, the system itself and the only elements being claimed in the system can be purely software embodiments to conduct a method, which would make claim 1 a software per se claim, which does not fall within the statutory categories of invention and thus is deemed as non-statutory subject matter. Likewise dependent claims 2-9 do not add additional elements to the system.
Obvious-Type Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of instant Application, respectively contains every element of claims 1-19 of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667), as listed below with the differences between the two underlined, and as such would be anticipated the claims of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667):
Claims
Instant Application
Claims
U.S. Patent No. 12,164,463 (parent application s/n 18/130,667)
Independent claim 1
A system in reconfigurable dataflow processors, the system comprising:
a host computer comprising an optimization module configured to conduct a method comprising:
receiving a user program for execution on a reconfigurable dataflow computing system, the reconfigurable dataflow computing system comprising a plurality of compute units and a plurality of memory units interconnected with a switching array;
converting the user program to an intermediate representation comprising a plurality of logical operations, executable via dataflow through one or more compute units of the plurality of compute units, one or more logical operations of the plurality of logical operations preceded by or followed by a buffer of one or more buffers, the buffer of the one or more buffers corresponding to one or more memory units of the plurality of memory units;
determining whether splitting a selected buffer yields a reduced cost; and
splitting the selected buffer in response to determining that splitting the selected buffer yields the reduced cost, to produce a first buffer and a second buffer.
Independent claim 1
A system in reconfigurable dataflow processors, the system comprising:
a host computer comprising an optimization module configured to conduct a method comprising:
receiving a user program for execution on a reconfigurable dataflow computing system, the reconfigurable dataflow computing system comprising a grid of compute units and a grid of memory units interconnected with a switching array, the user program comprising a plurality of tensor-based algebraic expressions;
converting the plurality of tensor-based algebraic expressions to an intermediate representation comprising one or more logical operations, executable via dataflow through one or more compute units of the grid of compute units, one or more logical operations preceded by or followed by a buffer, each buffer corresponding to one or more memory units within the grid of memory units;
determining whether splitting a selected buffer yields a reduced cost;
splitting the selected buffer in response to determining that splitting the selected buffer yields the reduced cost, to produce a first buffer and a second buffer; and
wherein dataflow through memory units corresponding to the first buffer and the second buffer is controlled by one or more memory units of the grid of memory units.
Analysis
It can be seen above that the instant application is a broader version of the already allowed claimed of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667), where there are minor differences in wording such as using “a plurality of” instead of “a grid of”, converting “the user program”, instead of converting “the plurality of tensor-based algebraic expression” where the user program comprises a plurality of tensor-based algebraic expressions, and U.S. Patent No. 12,164,463 even has an entire limitation not found in the instant application. As such, the broader claims of the instant application would be anticipated and read upon by the narrower claims of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667).
Independent claim 10
A method in a reconfigurable computing system, the method comprising:
receiving a user program for execution on a reconfigurable dataflow computing system, the reconfigurable dataflow computing system comprising a plurality of compute units and a plurality of memory units, the plurality of compute units and the plurality of memory units being interconnected;
converting the user program to an intermediate representation comprising a plurality of logical operations, executable via dataflow through one or more compute units of the plurality of compute units, one or more logical operations preceded by or followed by a buffer of one or more buffers, each buffer of the one or more buffers corresponding to one or more memory units of the plurality of memory units;
determining whether splitting a selected buffer yields a reduced cost; and
splitting the selected buffer in response to determining that splitting the selected buffer yields the reduced cost, to produce a first buffer and a second buffer.
Independent claim 10
A method in a reconfigurable computing system, the method comprising:
receiving a user program for execution on a reconfigurable dataflow computing system, the
reconfigurable dataflow computing system comprising a grid of compute units and a grid of memory units interconnected with a switching array, the user program comprising a
plurality of tensor-based algebraic expressions;
converting the plurality of tensor-based algebraic expressions to an intermediate
representation comprising one or more logical operations, executable via dataflow
through one or more compute units of the grid of compute units, one or more logical
operations preceded by or followed by a buffer, each buffer corresponding to one or more memory units within the grid of memory units;
determining whether splitting a selected buffer yields a reduced cost;
splitting the selected buffer in response to determining that splitting the selected buffer yields the reduced cost, to produce a first buffer and a second buffer; and
wherein dataflow through memory units corresponding to the first buffer and the second
buffer is controlled by one or more memory units of the grid of memory units.
Analysis
It can be seen above that the instant application is a broader version of the already allowed claimed of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667), where there are minor differences in wording such as using “a plurality of” instead of “a grid of”, converting “the user program”, instead of converting “the plurality of tensor-based algebraic expression” where the user program comprises a plurality of tensor-based algebraic expressions, and U.S. Patent No. 12,164,463 even has an entire limitation not found in the instant application. As such, the broader claims of the instant application would be anticipated and read upon by the narrower claims of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667).
Independent claim 19
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, wherein the program instructions are executable by a processor to cause the processor to conduct a method comprising:
receiving a user program for execution on a reconfigurable dataflow computing system, the reconfigurable dataflow computing system comprising a plurality of compute units and a plurality of memory units;
converting the user program to an intermediate representation comprising a plurality of logical operations, executable via one or more compute units of the plurality of compute units, one or more logical operations of the plurality of logical operations preceded by or followed by a buffer of one or more buffers, each buffer of the one or more buffers corresponding to one or more memory units of the plurality of memory units;
determining whether splitting a selected buffer yields a reduced cost;
splitting the selected buffer in response to determining that splitting the selected buffer yields the reduced cost, to produce a first buffer and a second buffer.
Independent claim 19
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, wherein the program instructions are executable by a processor to
cause the processor to conduct a method comprising:
receiving a user program for execution on a reconfigurable dataflow computing system, the reconfigurable dataflow computing system comprising a grid of compute units and a grid of memory units interconnected with a switching array, the user program comprising a plurality of tensor-based algebraic expressions;
converting the plurality of tensor-based algebraic expressions to an intermediate representation comprising one or more logical operations, executable via dataflow through one or more compute units of the grid of compute units, one or more logical operations preceded by or followed by a buffer, each buffer corresponding to one or more memory units within the grid of memory units;
determining whether splitting a selected buffer yields a reduced cost;
splitting the selected buffer in response to determining that splitting the selected buffer yields the reduced cost, to produce a first buffer and a second buffer; and
wherein dataflow through memory units corresponding to the first buffer and the second buffer is controlled by one or more memory units of the grid of memory units.
Analysis
It can be seen above that the instant application is a broader version of the already allowed claimed of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667), where there are minor differences in wording such as using “a plurality of” instead of “a grid of”, converting “the user program”, instead of converting “the plurality of tensor-based algebraic expression” where the user program comprises a plurality of tensor-based algebraic expressions, and U.S. Patent No. 12,164,463 even has an entire limitation not found in the instant application. It should be noted that the instant independent claim 19 talks about “…comprising a plurality of logical operations, executable via one or more compute units of the plurality of compute units…”, whereas independent claim 19 of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667) talks about “…comprising one or more logical operations, executable via dataflow through one or more compute units…” which is a shows that the instant application is broader here, but the logical operations executable via dataflow through the one or more compute units is claimed later in dependent claim 20 of the instant application. As such, the broader claims of the instant application would be anticipated and read upon by the narrower claims of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667).
Likewise, the dependent claims 2-9 and 11-18 of the instant application is a word for word duplicate of dependent claims 2-9 and 11-18 of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667), and claim 20 of the instant application is a limitation that is found in independent claim 19 of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667), but not found in independent claim 19 of the instant application, i.e. showing how instant independent claim 19 is broader than that of independent claim 19 of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667) and thus all of the dependent claims of the instant application would be anticipated by the claims of U.S. Patent No. 12,164,463 (parent application s/n 18/130,667) respectively.
Allowable Subject Matter
Claims 1-20 are deemed as allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art teaches systems and method for splitting a buffer/cache into multiple parts for the sake of performance or parallelism and systems and methods for allocating / splitting data into multiple groups, however, the prior art does not fairly teach or suggest, individually or in combination, a system and method for a reconfigurable dataflow processor system comprising a plurality of compute units and a plurality of memory units interconnected with a switching array that receives a user program, where the user program is converted to intermediate representations comprising one or more logical operations that are executed through the plurality of compute units where execution of operations is preceded by or followed by a buffer with each buffer corresponding to one or more memory units within the plurality of memory units, where a determination is made on whether splitting a selected buffer will yield a reduced cost, and if so, then splitting the selected buffer to produce a first buffer and second buffer as claimed. More specifically, Examiner finds that prior art such as Joshi ‘121 teaches a data processing engine (DPE) array with a grid of DPEs with each DPE having a core and a memory module where a buffer splitting variable can be used to indicated that a buffer is split, however Examiner finds that prior art does not specifically teach a reconfigurable array/processor having a plurality of compute units and a plurality of memory units that performs the conversion of a user program into intermediate representation and where a determination of a buffer associated with one of the memory units is done to determine if a split buffer will reduce costs and splitting the buffer into two buffers if it is determined that this split will yield reduced results as claimed where Examiner specifically cites Applicant’s Specification Paragraphs 0125-0126 where Applicants indicate that reduced cost may include resource-aware splitting that includes analysis via a buffer resource model and/or cost model where the reduced costs will enable reduced memory consumption, reduced latency, and improved runtime performance. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Joshi et al. (US 10,839,121) teaches a data processing engine (DPE) array with a grid of DPEs with each DPE having a core and a memory module where a buffer splitting variable can be used to indicated that a buffer is split.
Gurtovoy et al. (US 2023/0140640) teaches a system for splitting frames with a command buffer into frames with multiple smaller command buffers.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183