Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on May 22nd, 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of any patent granted on Application Number 18/945,120 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Amendment
The amendment filed May 22nd, 2026 has been entered. Claims 1 and 3-20 are pending in this application. Claim 2 has been canceled. Applicant amended independent claims 1, 13, and 19 to further define the first intermediate representation as comprising a transformed representation of the data, to identify the previously taught checksum as a first checksum, and to teach generating a second checksum based on a second intermediate representation produced by the second processing stage.
Applicant’s amendments to the claims have been fully considered, however after reconsidering the prior art, as well as performing an updated search, the rejection set forth in the previous Office action mailed February 23rd, 2026, has been modified accordingly.
Response to Arguments
Applicant's arguments filed May 22nd, 2026 have been fully considered but they are not persuasive.
Applicant’s submission of the terminal disclaimer in response to the nonstatutory double patenting rejection has been considered. The terminal disclaimer overcomes the previously asserted nonstatutory double patenting rejection.
Applicant’s arguments regarding the combination of Brinicombe et al. (US 2015/0301964), hereinafter Brinicombe, in view of Yang et al. (US 8,255,763), hereinafter Yang, have been fully considered but are not persuasive in view of the amended rejection. Applicant argues that the cited references fail to teach a first intermediate representation comprising a transformed representation of the data and generation of a second checksum based on a second intermediate representation produced by a second processing stage. The rejection has been modified to further rely on Pruthi (US 8,645,798), which teaches transformed intermediate or partial representations of data, including weighted sums and linear combinations of data, and generation of intermediate and compete checksum values.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-20 are rejected under 35 U.S.C. 103 as being unpatentable over Brinicombe et al. (US 2015/0301964), hereinafter Brinicombe, in view of Yang et al. (US 8,255,763), hereinafter Yang, and further in view of Pruthi (US 8,645,798).
Regarding claim 1, Brinicombe teaches a method comprising:
detecting, by a storage system, a write command that initiates a data storage operation, wherein the data storage operation includes processing data via a data storage path from intake of the data into the storage system to storing the data in a storage device of the storage system (Brinicombe, Fig. 3B teaches a write ingest pipeline that handles write operations, where data flows through an ingest pipeline prior to reaching storage),
verifying, by the storage system prior to the second processing stage producing a second intermediate representation of the data, the first checksum (Brinicombe, claim 9, “The data-plane architecture of claim 8, wherein the write pipeline moves the data from the write/ingest memory to the write/emit memory, and wherein during the write pipeline checksums are verified ad the data is encrypted”); and
directing, by the storage system and based on the verifying the first checksum, the second processing stage to produce the second intermediate representation of the data based on the first intermediate representation of the data (Brinicombe, para. [0082] teaches verifying data using stored checksums maintained in a checksum database, where the checksum database serves as an authoritative source for comparison).
Brinicombe fails to explicitly teach the data storage path comprising at least a first processing stage and a second processing stage, generating, by the storage system and based on a first intermediate representation of the data produced by the first processing stage, a first checksum, the first intermediate representation of the data comprising a transformed representation of the data, , and generating, by the storage system and based on the second intermediate representation of the data produced by the second processing stage, a second checksum.
However, Yang, in an analogous art, teaches the data storage path comprising at least a first processing stage (Yang, Fig. 1, interleaved code encoder 122) and a second processing stage (Yang, Fig. 1, embedded parity code encoder 124).
Brinicombe and Yang are both considered to be analogous to the claimed invention because both are in the same field of multi-stage memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brinicombe to incorporate the teachings of Yang by including the functionality of having staged processing and intermediate representations of data.
The suggestion/motivation for doing so would be to ensure that subsequent processing stages operate correctly on verified data.
The combination of Brinicombe in view of Yang, taken singly or combined, fail to teach generating, by the storage system and based on a first intermediate representation of the data produced by the first processing stage, a first checksum, the first intermediate representation of the data comprising a transformed representation of the data and generating, by the storage system and based on the second intermediate representation of the data produced by the second processing stage, a second checksum.
However, Pruthi, in an analogous art, teaches generating, by the storage system and based on a first intermediate representation of the data produced by the first processing stage, a first checksum (Pruthi, col. 8, lines 1-30 teach the limits of summation determining the partial sum that generates each intermediate checksum, and that each RAID controller computes an intermediate checksum, as shown in Equation 8), the first intermediate representation of the data comprising a transformed representation of the data (Pruthi, col. 7, lines 30-44 teach an intermediate sum calculator calculating intermediate, local, partial sums, into which checksum and data calculations are decomposed, and the intermediate sums may be weighted sums of symbols read from the storage devices; col. 10, lines 15-30 teach intermediate checksum/data/parity calculations being computed from a linear combination of data words using properties of a Galois field), and generating, by the storage system and based on the second intermediate representation of the data produced by the second processing stage, a second checksum (Pruthi, col. 10, lines 31-49 teach receiving second and third intermediate checksum that, when combined with the locally calculated first checksum, form a sufficient set to compute a complete checksum; col. 10, lines 49-54 t4each the resulting data and complete checksum symbols are stored/striped across the disk array).
Brinicombe, Yang, and Pruthi are considered to be analogous to the claimed invention because they are in the same field of multi-stage memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Brinicombe in view of Yang, further in view of Pruthi by including the functionality of having intermediate checksum calculations.
The suggestion/motivation for doing so would be to provide integrity information corresponding to transformed intermediate data, as well as reduce computational burden and latency while increasing scalability and throughput (Pruthi, col. 5, lines 1-8, “The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture”).
Regarding claim 3, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 1, wherein the transforming comprises at least one of compressing the data, merging the data, splitting the data, encrypting the data, or generating erasure codes for the data (Brinicombe, para. [0055], lines 7-9, “data processing steps can be limited to standard storage operations and systems [e.g. for RAID, compression, de-duplication, encryption, and the like]”).
Regarding claim 4, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 1, wherein the processing the data comprises a transmission of the data from a first component of the storage system to a second component of the storage system (Brinicombe, para. [0053], lines 10-11, “movement of data between pipeline steps can be automated by built-in micro-sequencers to save embedded CPU load”; para. [0075], lines 10-12, “These reverse references can be used to allow for physical data movement within the storage array”).
Regarding claim 5, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 1, wherein the verifying the first checksum comprises: generating an additional instance of the first checksum based on the first intermediate representation; and comparing the additional instance of the first checksum to the first checksum (Brinicombe, para. [0081], lines 1-8, “an additional smaller checksum can be computed [e.g. substantially simultaneously with hash message authentication code (HMAC or other cryptographic hash)]. This checksum can be held in memory. By holding the checksum in memory, the checksum can be available so every read computes the same checksum. A comparison can be performed in order to detect transient read errors for the storage devices”).
Regarding claim 6, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 5, further comprising: determining, based on the comparing, that the additional instance of the first checksum is different from the first checksum; and directing, based on the determining that the additional instance of the first checksum is different from the first checksum, the first processing stage to generate an additional instance of the first intermediate representation of the data (Brinicombe, para. [0081], lines 8-10, “A comparison can be performed in order to detect transient read errors for the storage devices. A failure can result in the data being re-read from the array and/or reconstruction of the data using parity on the redundant”).
Regarding claim 7, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 5, further comprising:
determining, based on the comparing, that the additional instance of the first checksum is different from the first checksum; and
applying, based on the determining that the additional instance of the first checksum is different from the first checksum, an error correcting algorithm to the first intermediate representation of the data (Brinicombe, para. [0081], lines 8-10, “A comparison can be performed in order to detect transient read errors for the storage devices. A failure can result in the data being re-read from the array and/or reconstruction of the data using parity on the redundant;” para. [0045], lines 37-43, “Example data encoding for redundancy implementations can include: mirroring [e.g. copying of data]: single parity [RAID-5], double parity [RAID-6] and triple parity encoding; generic M+N/(Cauchy)Reed-Solomon coding; and/or error correction codes such as Hamming codes, convolution codes, BCH codes, turbo codes, LDPC codes”).
Regarding claim 8, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 1, wherein the generating the first checksum is performed in conjunction with a generating of the first intermediate representation at the first processing stage (Brinicombe, para. [0055], lines 7-9, “data processing steps can be limited to standard storage operations and systems ( e.g. for RAID, compression, de-duplication, encryption, and the like);” para. [0080], lines 5-7, “a cryptographic hash (e.g. SHA-256) can be computed for every user data block for each write”; the reference teaches a hash/checksum being computer during write processing, as well as processing and checksum generating occurring together in the pipeline).
Regarding claim 9, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 1, wherein: the data storage path consists of a plurality of processing stages including the first processing stage and the second processing stage; and the method further comprises: generating at each processing stage of the plurality of stages, a respective checksum; and verifying, prior to proceeding to a subsequent processing stage, the respective checksum (Yang, Fig. 6B, block 662; the reference teaches multi-stage processing and verification before proceeding).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brinicombe to incorporate the teachings of Yang by including the functionality of multi-stage processing and verification before proceeding.
The suggestion/motivation for doing so would be to ensure reliability of the processing stage before proceeding in the operation.
Regarding claim 10, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 9, wherein the generating the respective checksum at each processing stage is performed in conjunction with processing the data at each processing stage (Yang, Fig. 6A teaches evaluating parity and reliability metrics before continuing the decoding process).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brinicombe to incorporate the teachings of Yang by including the functionality of generating checksum at each stage, along with processing data.
The suggestion/motivation for doing so would be to ensure reliability of the processing stage before proceeding in the operation.
Regarding claim 11, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 1, further comprising:
detecting a read command that initiates a data retrieval operation, wherein the data retrieval operation includes processing the data via a data retrieval path from the storage device to output of the data from the storage system (Brinicombe, Fig. 3B teaches a read pipeline that handles write operations, where data flows through an ingest pipeline prior to reaching storage), the data retrieval path comprising at least a third processing stage that corresponds to the second processing stage of the data storage path and a fourth processing stage that corresponds to the first processing stage of the data storage path (Yang, Fig. 4A teaches a multi-stage processing pipeline with sequential stages);
verifying, prior to the third processing stage producing an additional instance of the first intermediate representation of the data, the second checksum; directing, based on the verifying the second checksum, the third processing stage to produce the additional instance of the first intermediate representation of the data based on the second intermediate representation of the data; generating, based on the additional instance of the first intermediate representation of the data, an additional instance of the first checksum; verifying, prior to the fourth processing stage producing an additional instance of the data, the additional instance of the first checksum (Brinicombe, para. [0081], lines 7-10, “A comparison can be performed in order to detect transient read errors for the storage devices. A failure can result in the data being re-read from the array and/or reconstruction of the data using parity on the redundant”); and providing, based on the verifying the additional instance of the first checksum, the additional instance of the data as an output to the read command (Brinicombe, para. [0082], lines 1-4, “Multiple reads can be implemented to validate data. For example, when the system is running the checksum database can be used to allow the data for every read to be validated to catch transient and/or drive errors”; implies that validation occurs before data is provided to the requestor).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brinicombe to incorporate the teachings of Yang by including the functionality of having staged processing and intermediate representations of data.
The suggestion/motivation for doing so would be to ensure that subsequent processing stages operate correctly on verified data.
Regarding claim 12, the combination of Brinicombe in view of Yang, further in view of Pruthi teaches the method of claim 11, wherein: the first checksum is stored in the storage system in response to the write command; and the verifying the additional instance of the checksum comprises comparing the additional instance of the first checksum with the first checksum (Brinicombe, para. [0081], lines 1-8, “an additional smaller checksum can be computed [e.g. substantially simultaneously with hash message authentication code (HMAC or other cryptographic hash)]. This checksum can be held in memory. By holding the checksum in memory, the checksum can be available so every read computes the same checksum. A comparison can be performed in order to detect transient read errors for the storage devices”).
Claim 13 is a system with limitations similar to the method of claim 1, and is rejected under the same rationale.
Claim 14 is a system with limitations similar to the method of claim 3, and is rejected under the same rationale.
Claim 15 is a system with limitations similar to the method of claim 4, and is rejected under the same rationale.
Claim 16 is a system with limitations similar to the method of claim 8, and is rejected under the same rationale.
Claim 17 is a system with limitations similar to the method of claim 9, and is rejected under the same rationale.
Claim 18 is a system with limitations similar to the method of claim 11, and is rejected under the same rationale.
Claim 19 is a computer program product with limitations similar to the method of claim 1, and is rejected under the same rationale.
Claim 20 is a computer program product with limitations similar to the method of claim 11, and is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Froemke et al. (US 5,239,640) teaches a storage system with a write-staging area and multiple checksum operations.
Foley et al. (US 10,120,797) teaches computing checksums for data portions in a storage system, and using the checksums to determine whether data is valid.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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