DETAILED ACTION
This non-final office action is responsive to the following communications: application field on 11/12/2024.
Claims 1-17 are pending. Claims 1, 4 and 13 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
B) G) Per MPEP 2173.04, Breadth of a claim is not to be equated with indefiniteness, but “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”.
C) Per MPEP 2173.04, undue breadth of the claim may be addressed under different statutory provisions, depending on the reasons for concluding that the claim is too broad.
D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim. Other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See
MPEP § 2163.06.
E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103 and once a reference teaching product appearing to be substantially identical is made the basis of a rejection, and the examiner presents evidence or reasoning tending to show inherency, the burden of proof shifts to the applicant.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 11/12/2024 and 10/31/2025. All IDS has been considered.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 4-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 4 (line 9) recites “…read transistor connected to the capacitor through a gate…” which is unclear and vague in view of supporting Fig. 1A, Fig. 1B, para [0075]-para [0078]. The language is subject to multiple interpretations which can imply an additional intervening gate/ transistor/ component in-between read transistor and capacitor. In view of supporting Fig. 1A, Fig. 1B, the limitation should state that the gate of the read transistor is connected to the electrode of the capacitor connected to the one end of the second NMOS transistor.
Claim 13 (lines 3-4) recites “…read transistor connected to the second NMOS transistor through a gate…” which is unclear and vague in view of supporting Fig. 1A, Fig. 1B, para [0075]-para [0078]. See above.
Definiteness of claim language requires a determination of whether those skilled in the art would understand what is claimed when the claim is read in light of the specification.
The limitations are interpreted according to Fig. 1A, Fig. 1B, para [0075]-para [0078]. See art rejection.
All dependent claims inclusive of claims 4-17 are rejected under this category.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) (1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-11, and 13-17 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Gokmen et al. (US 2018/0053089 A1).
Regarding independent claim 1, Gokmen teaches a neuromorphic semiconductor device (para [0057]: cross-point array of RPU) comprising a resistive processing unit (Fig. 5: 100 RPU) used as a synaptic element (para [0003]) and included in one cell,
wherein the resistive processing unit (Fig. 5: 100 RPU) includes a first N-type metal oxide semiconductor (NMOS) transistor (Fig. 5: TR1) electrically connected to a first input terminal (V.sub.G1) (Fig. 5: UPDATE 1) and having one end connected to a voltage source including a power supply voltage (V.sub.DD) or a ground voltage (GND) (Fig. 5: VDD, GND), and
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a second NMOS transistor (Fig. 5: TR2) electrically connected to a second input terminal (V.sub.G2) (Fig. 5: UPDATE 2) and having one end (Fig. 5: Vw terminal) connected to a gate of a read transistor (Fig. 5: gate of TR3),
the first NMOS transistor (Fig. 5: TR1) and the second NMOS transistor (Fig. 5: TR2) being connected in series (see Fig. 5: TR1, TR2 connection) and the read transistor reading an amount of charge stored in the gate (Fig. 5 in context of para [0047]: charge stored in Cw and gate is read by TR3).
Regarding claim 2, Gokmen teaches the neuromorphic semiconductor device of claim 1, wherein when charging the gate of the read transistor (Fig. 5: TR3), the first NMOS transistor (Fig. 5: TR1) and the second NMOS transistor (Fig. 5: TR2) are set to an ON state (V.sub.G1=V.sub.G2>Vth), and then the voltage source is set to V.sub.DD (Fig. 5 in context of para [0045], para [0046]: charging with VDD applied and circuitry configuration teaches this function), and
when discharging the gate of the read transistor (Fig. 5: TR3), the first NMOS transistor (Fig. 5: TR1) and the second NMOS transistor (Fig. 5: TR2) are set to the ON state, and then the voltage source is set to the ground (GND) (Fig. 5 in context of para [0045], para [0046]: discharging with VSS applied and circuitry configuration teaches this function).
Regarding claim 3, Gokmen teaches the neuromorphic semiconductor device of claim 1, wherein when the gate of the read transistor does not require charging, at least one of the first NMOS transistor or the second NMOS transistor is set to an OFF state (V.sub.G1<Vth or V.sub.G2<Vth) (Fig. 5 configuration teaches this is done to isolate additional charge propagation from VDD), and
in order to read the amount of charge stored in the gate of the read transistor, the first NMOS transistor and the second NMOS transistor are set to an OFF state (V.sub.G1=V.sub.G2<Vth) (Fig. 5 configuration teaches this is done for reading the charge accumulated on Cw/ TR3 gate and to isolate additional charge propagation).
Regarding independent claim 4, Gokmen teaches a neuromorphic semiconductor device (para [0003], para [0057]: cross-point array of RPU) comprising a resistive processing unit (Fig. 5: 100 RPU) used as a synaptic element (para [0003]) and included in one cell,
wherein the resistive processing unit (Fig. 5: 100 RPU) includes
a first N-type metal oxide semiconductor (NMOS) transistor (Fig. 5: TR1) electrically connected to a first input terminal (V.sub.G1) (Fig. 5: UPDATE 1) and having one end connected to a voltage source including a power supply voltage (V.sub.DD) or a ground voltage (GND) (Fig. 5: VDD, GND),
a second NMOS transistor (Fig. 5: TR2) electrically connected to a second input terminal (V.sub.G2) (Fig. 5: UPDATE 2) and having one end (Fig. 5: Vw terminal) connected to a capacitor (Fig. 5: Cw), and
a read transistor (Fig. 5: TR3) connected to the capacitor (Fig. 5: Cw) through a gate (Fig. 5: gate of TR3) and
configured to read an amount of charge charged in the capacitor (Fig. 5 in context of para [0047]: charge stored in capacitor and gate is read by TR3),
the first NMOS transistor and the second NMOS transistor being connected in series (see Fig. 5: TR1, TR2 series connection).
Regarding claim 5, Gokmen teaches the neuromorphic semiconductor device of claim 4, wherein the first NMOS transistor and the second NMOS transistor include a thin film transistor (TFT), an organic semiconductor, hydrogenated amorphous silicon (a-Si: H), or a metal oxide semiconductor (MOS) (para [0049]: MOS)
Regarding claim 6, Gokmen teaches the neuromorphic semiconductor device of claim 4, wherein the voltage source connected to one end of the first NMOS transistor is electrically connected to a power supply voltage (V.sub.DD) or a ground voltage (GND) through a switch (para [0045] in context of Fig. 5: VDD, GRND: function requires a switch in Fig. 5 circuit).
Regarding claim 7, Gokmen teaches the neuromorphic semiconductor device of claim 4, wherein charging or discharging of the read transistor is controlled by selectively changing the power supply voltage (V.sub.DD) or the ground voltage (GND) (para [0045], para [0046]).
Regarding claim 8, Gokmen teaches the neuromorphic semiconductor device of claim 4, wherein the read transistor is configured to have the same NMOS form as the first NMOS transistor and the second NMOS transistor (Fig. 5 and para [0049]).
Regarding claim 9, Gokmen teaches the neuromorphic semiconductor device of claim 4, wherein the resistive processing unit (RPU) is arranged in an array form to perform selective update (see Fig. 10 array with rows and columns and selectable cells. See also Fig. 5), and
the gate electrodes of the first NMOS transistor (Fig. 5: TR1’s UPDATE 1 terminal which is same as See Fig. 10: nmos connected to N12 row terminal) are connected as a row line (Fig. 10: N12) and the gate electrodes of the second NMOS transistor (Fig. 5: TR2’s UPDATE 2 terminal which is same as See Fig. 10: nmos connected to N21 column terminal) are connected as a column line (Fig. 10: N21) to form an array (See Fig. 10 in context of para [0057]: RPU arranged in 2x2 array is formed).
Regarding claim 10, Gokmen teaches the neuromorphic semiconductor device of claim 4, wherein when charging the resistive processing unit, the voltage source is set to V.sub.DD, and the first NMOS transistor and the second NMOS transistor are controlled to be in an ON state (V.sub.G1=V.sub.G2>Vth), (para [0045]: charging)
when discharging the resistive processing unit, the voltage source is set to GND, and the first NMOS transistor and the second NMOS transistor are controlled to be in an OFF state (V.sub.G1=V.sub.G2<Vth) (para [0059] and subthreshold operation), and
when not charging the resistive processing unit, at least one of the first NMOS transistor or the second NMOS transistor is controlled to be in an OFF state (V.sub.G1<Vth or V.sub.G2<Vth) (limitation is treated as Fig. 5 device usage and the functionality is taught by device circuitry configuration).
Regarding claim 11, Gokmen teaches the neuromorphic semiconductor device of claim 4, wherein when reading the amount of charge charged in the capacitor, the first NMOS transistor and the second NMOS transistor are controlled to be in an OFF state (V.sub.G1=V.sub.G2<Vth) and the current is read through the read transistor (Fig. 5 in context of para [0004], para [0044], para [0059]: transistor operation and read function in “subthreshold” regime).
Regarding independent claim 13, Gokmen teaches an operating method of a neuromorphic semiconductor device (para [0003]) by an update operation using an array of resistive processing units (para [0003], para [0057]: cross-point array of RPU) including a first NMOS transistor (Fig. 5: TR1) and a second NMOS transistor (Fig. 5: TR2) connected in series and a read transistor (Fig. 5: TR3) connected to the second NMOS transistor (Fig. 5: TR2) through a gate (Fig. 5: gate of TR3),
the operation method comprising:
forming an array in which gate electrodes of the first NMOS transistor (Fig. 5: TR1’s UPDATE 1 terminal which is same as See Fig. 10: nmos connected to N12 row terminal) are connected as a row line (Fig. 10: N12) and gate electrodes of the second NMOS transistor are connected as a column line (Fig. 5: TR2’s UPDATE 2 terminal which is same as See Fig. 10: nmos connected to N21 column terminal. See Fig. 10 in context of para [0057]: RPU arranged in 2x2 array is formed);
applying a first voltage to the row line connected to the gate electrode of the first NMOS transistor (para [0045]: current applied to TR1 via UPDATE 1);
applying a second voltage to the column line connected to the gate electrode of the second NMOS transistor (para [0045]: current applied to TR2 via UPDATE 2); and
selecting an operable resistive processing unit (selection of RPU, see Fig. 5: 100) based on the first voltage and the second voltage applied to the row line and the column line (para [0045] in context of Fig. 5, Fig. 10), respectively, and
updating the selected resistive processing unit (para [0046]: updating the weight of training).
Regarding claim 14, Gokmen teaches the operation method of claim 13, wherein when the first voltage and the second voltage applied to the row line and the column line are higher than a threshold voltage (Vth) (para [0045]: UPDATE 1, UPDATE 2 voltages are used to turn on transistors TR1, TR2. See Fig. 5 and Fig. 10: N12 row, N21 column coupling),
an update operation of the corresponding resistive processing unit is performed (para [0003], para [0004], para [0045], para [0046]), and
when the first voltage and the second voltage applied to the row line and the column line are lower than the threshold voltage (Vth), the update operation of the corresponding resistive processing unit is not performed (see para [0045], para [0046).
Regarding claim 15, Gokmen teaches the operation method of claim 13, further comprising reading an amount of charge (para [0046]: weight of training and associated charge) charged in the gate through the read transistor (Fig. 5: TR3) in the resistive processing unit (para [0047]).
Regarding claim 16, Gokmen teaches the operation method of claim 13, wherein the resistive processing unit further includes a capacitor (Fig. 5: Cw) connected to one end (Fig. 5: Vw) of the second NMOS transistor (Fig. 5: TR2), and
the operation method further includes reading an amount of charge charged in the capacitor through the read transistor (para [0046], para [0047]).
Regarding claim 17, Gokmen teaches the operation method of claim 13, wherein a V.sub.DD voltage is applied to an input terminal to increase an amount of charge stored in the read transistor (Fig. 5 in context of para [0045], para [0046]: charging with VDD applied and circuitry configuration teaches this function), and a GND voltage is applied to decrease the amount of stored charge (Fig. 5 in context of para [0045], para [0046]: discharging with VSS applied and circuitry configuration teaches this function).
(Art rejection for not all claims re provided. See 112b rejection)
Prior Art Not Relied Upon
Kim (US 20210064974 A1): Fig. 1-Fig. 8 disclosure applicable for all claims. Kim teaches neuromorphic device includes a plurality of first control lines, a plurality of second control lines and a matrix of resistive processing unit cells. Each resistive processing unit cell is electrically connected with one of the first control lines and one of the second control lines. A given resistive processing unit cell includes a first resistive device and a second resistive device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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