DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 4, 10-13, 14-15 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (Patent 10790038), hereinafter as Jang.
Regarding claim 1, Jang teaches a memory, comprising: a compression circuit (Fig 7A, 531 and Fig 7B, 541), an input terminal of the compression circuit receiving read data transmitted through transmission paths of a plurality of data input/output pins (Fig 7A, IO2<0:7>), and the compression circuit being configured to separately compress the read data transmitted through the transmission paths of the data input/output pins (Fig 7A IO2<0:7>, and Fig 7B IO2<8:15>), to obtain a plurality of pieces of compressed data (Fig 7A and 7B, DATA_CMPR1/2); and
a data input/output selector (Fig 7A/B MUXB), a first input terminal of the data input/output selector being connected to an output terminal (Fig 7A/B input of MUXB connected to output of 531) of the compression circuit, and the data input/output selector receiving the plurality of pieces of compressed data (Fig 7A/B input of MUXB) and being configured to:
in a test mode (Fig 7A/B TM2), transmit the plurality of pieces of compressed data to a target data input/output pin, the target data input/output pin being any one of the plurality of data input/output pins (col 5, line 13-20, i.e. DQ4 could be any one of DQ0-7).
Regarding claim 5, Jang teaches a second input terminal of the data input/output selector receives read data transmitted through transmission paths of the target data input/output pin, and the data input/output selector is configured to transmit, to the target data input/output pin when the data input/output selector is in an operating mode, the read data transmitted through the transmission paths of the target data input/output pin (Fig 7A, TM1, select data either through 531 or bypassing 531).
Regarding claim 6, Jang teaches the data input/output selector comprises a plurality of first selectors (Fig 7A/B, 532 and 542), and each first selector corresponds to one transmission path of the target data input/output pin;
a first input terminal of each first selector receives compressed data corresponding to one data input/output pin, and a second input terminal of each first selector receives 1-bit data in the read data transmitted through the transmission paths of the target data input/output pin (Fig 7A/B); and
each first selector is configured to: in the test mode, transmit compressed data of a data input/output pin corresponding to the first selector to the target data input/output pin, and in the operating mode, transmit, to the target data input/output pin, 1-bit data in the read data transmitted through the transmission paths of the target data input/output pin (Fig 7A/B).
Regarding claim 7, Jang teaches a first buffer (Fig 7A, 533 PPLT), an input terminal thereof being connected to the data input/output selector, and the first buffer being configured to: store data output by the data input/output selector, and output, after a read command is received, the data output by the data input/output selector.
Regarding claim 8, Jang teaches a first parallel-to-serial conversion circuit (Fig 7A, 534 P2S), an input terminal thereof being connected to the first buffer, and the first parallel-to-serial conversion circuit receiving data output by the first buffer, performing parallel-to-serial conversion on the data output by the first buffer, and outputting data obtained through parallel-to-serial conversion to the target data input/output pin.
Regarding claim 9, Jang teaches in the test mode, the first parallel-to-serial conversion circuit is specifically configured to sort the plurality of pieces of compressed data in a sequence of the data input/output pins, to convert the plurality of pieces of compressed data into serial data (Fig 7A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang, in view of Yuan et al. (PGPUB 20110156742), hereinafter as Yuan.
Regarding claim 2, Jang teaches a device as in rejection of claim 1,
But not expressly compare compressed data with info of matching and mismatching.
Yuan teaches when read data transmitted through all transmission paths of any data input/output pin is the same, the plurality of pieces of compressed data are configured to indicate that the memory is normal if compressed data corresponding to each data input/output pin indicates that all bits of data in read data transmitted through transmission paths corresponding to the data input/output pin are the same; or the plurality of pieces of compressed data are configured to indicate that the memory is faulty if compressed data corresponding to each of some data input/output pins indicates that a part of data in read data transmitted through transmission paths corresponding to the data input/output pin is different ([0026]).
Since Yuan and Jang are both from the same field of semiconductor memory device, the purpose disclosed by Yuan would have been recognized in the pertinent art of Jang.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use compressed data to flag test data for the purpose of identify mismatching of test data.
Regarding claim 3, Jang teaches the compression circuit comprises a plurality of compression sub-circuits (Fig 7A/B, 531/541), and an input terminal of each compression sub-circuit receives read data transmitted through transmission paths of one data input/output pin (Fig 7A/B); and
each compression sub-circuit is configured to compress read data transmitted through transmission paths of a data input/output pin corresponding to the compression sub-circuit, to obtain corresponding compressed data (Fig 7A/B, DATA_COMPR1/2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
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