DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 4, 10-13, 14-15 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 16 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a compression circuit, an input terminal of the compression circuit receiving read data transmitted through transmission paths of a plurality of data input/output pins, and the compression circuit being configured to separately compress the read data transmitted through the transmission paths of the data input/output pins, to obtain a plurality of pieces of compressed data; a data input/output selector, a first input terminal of the data input/output selector being connected to an output terminal of the compression circuit, and the data input/output selector receiving the plurality of pieces of compressed data and being configured to: in a test mode, transmit the plurality of pieces of compressed data to a target data input/output pin, the target data input/output pin being any one of the plurality of data input/output pins; and data mask pins receiving check code data, wherein the memory checks, based on the check code data, the read data transmitted through the transmission paths of the plurality of data input/output pins, and a combination of other limitations in the independent claims.
Claim 21 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a compression circuit, an input terminal of the compression circuit receiving read data transmitted through transmission paths of a plurality of data input/output pins, and the compression circuit being configured to separately compress the read data transmitted through the transmission paths of the data input/output pins, to obtain a plurality of pieces of compressed data; a data input/output selector, a first input terminal of the data input/output selector being connected to an output terminal of the compression circuit, and the data input/output selector receiving the plurality of pieces of compressed data and being configured to: in a test mode, transmit the plurality of pieces of compressed data to a target data input/output pin, the target data input/output pin being any one of the plurality of data input/output pins; wherein a second input terminal of the data input/output selector receives read data transmitted through transmission paths of the target data input/output pin, and the data input/output selector is configured to transmit, to the target data input/output pin when the data input/output selector is in an operating mode, the read data transmitted through the transmission paths of the target data input/output pin; a first buffer, an input terminal thereof being connected to the data input/output selector, and the first buffer being configured to: store data output by the data input/output selector, and output, after a read command is received, the data output by the data input/output selector; a first parallel-to-serial conversion circuit, an input terminal thereof being connected to the first buffer, and the first parallel-to-serial conversion circuit receiving data output by the first buffer, performing parallel-to-serial conversion on the data output by the first buffer, and outputting data obtained through parallel-to-serial conversion to the target data input/output pin; wherein in the test mode, the first parallel-to-serial conversion circuit is specifically configured to sort the plurality of pieces of compressed data in a sequence of the data input/output pins, to convert the plurality of pieces of compressed data into serial data; wherein the plurality of data input/output pins comprise the target data input/output pin and other data input/output pins; anda second buffer, an input terminal thereof receiving read data transmitted through transmission paths of the other data input/output pins, and the second buffer being configured to: store the read data transmitted through the transmission paths of the other data input/output pins, and output, after a read command is received, the read data transmitted through the transmission paths of the other data input/output pins, and a combination of other limitations in the independent claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (Patent 10790038), hereinafter as Jang, in view of Kwon et al. (PGPUB 20250054551), hereinafter as Kwon.
Regarding claim 1, Jang teaches a memory, comprising: a compression circuit (Fig 7A, 531 and Fig 7B, 541), an input terminal of the compression circuit receiving read data transmitted through transmission paths of a plurality of data input/output pins (Fig 7A, IO2<0:7>), and the compression circuit being configured to separately compress the read data transmitted through the transmission paths of the data input/output pins (Fig 7A IO2<0:7>, and Fig 7B IO2<8:15>), to obtain a plurality of pieces of compressed data (Fig 7A and 7B, DATA_CMPR1/2); and
a data input/output selector (Fig 7A/B MUXB), and the data input/output selector receiving the plurality of pieces of compressed data (Fig 7A/B input of MUXB) and being configured to:
in a test mode (Fig 7A/B TM2), transmit the plurality of pieces of compressed data to a target data input/output pin, the target data input/output pin being any one of the plurality of data input/output pins (col 5, line 13-20, i.e. DQ4 could be any one of DQ0-7),
but not expressly a first input terminal of the data input/output selector being connected to an output terminal, nor the compression circuit comprises a plurality of compression sub-circuits, and an input terminal of each compression sub-circuit receives read data transmitted through transmission paths of one data input/output pin; and each compression sub-circuit is configured to compress read data transmitted through transmission paths of a data input/output pin corresponding to the compression sub-circuit, to obtain corresponding compressed data,
Kwon teaches a first input terminal of the data input/output selector being connected to an output terminal (Fig 1, e.g. R.DATA1 to C.DATA1), the compression circuit comprises a plurality of compression sub-circuits (Fig 1, compressing circuits 1200s), and an input terminal of each compression sub-circuit receives read data transmitted through transmission paths of one data input/output pin (Fig 1, e.g. receive data from C.DATA1); and each compression sub-circuit is configured to compress read data transmitted through transmission paths of a data input/output pin corresponding to the compression sub-circuit, to obtain corresponding compressed data (Fig 1, e.g. C.DATA1),
Since Kwon and Jang are both from the same field of semiconductor memory device, the purpose disclosed by Kwon would have been recognized in the pertinent art of Jang.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use compressing circuits as in Kwon into the device of Jang for the purpose of compressing data.
Regarding claim 5, Jang teaches a second input terminal of the data input/output selector receives read data transmitted through transmission paths of the target data input/output pin, and the data input/output selector is configured to transmit, to the target data input/output pin when the data input/output selector is in an operating mode, the read data transmitted through the transmission paths of the target data input/output pin (Fig 7A, TM1, select data either through 531 or bypassing 531).
Regarding claim 6, Jang teaches the data input/output selector comprises a plurality of first selectors (Fig 7A/B, 532 and 542), and each first selector corresponds to one transmission path of the target data input/output pin;
a first input terminal of each first selector receives compressed data corresponding to one data input/output pin, and a second input terminal of each first selector receives 1-bit data in the read data transmitted through the transmission paths of the target data input/output pin (Fig 7A/B); and
each first selector is configured to: in the test mode, transmit compressed data of a data input/output pin corresponding to the first selector to the target data input/output pin, and in the operating mode, transmit, to the target data input/output pin, 1-bit data in the read data transmitted through the transmission paths of the target data input/output pin (Fig 7A/B).
Regarding claim 7, Jang teaches a first buffer (Fig 7A, 533 PPLT), an input terminal thereof being connected to the data input/output selector, and the first buffer being configured to: store data output by the data input/output selector, and output, after a read command is received, the data output by the data input/output selector.
Regarding claim 8, Jang teaches a first parallel-to-serial conversion circuit (Fig 7A, 534 P2S), an input terminal thereof being connected to the first buffer, and the first parallel-to-serial conversion circuit receiving data output by the first buffer, performing parallel-to-serial conversion on the data output by the first buffer, and outputting data obtained through parallel-to-serial conversion to the target data input/output pin.
Regarding claim 9, Jang teaches in the test mode, the first parallel-to-serial conversion circuit is specifically configured to sort the plurality of pieces of compressed data in a sequence of the data input/output pins, to convert the plurality of pieces of compressed data into serial data (Fig 7A).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang and Kwon, in view of Yuan et al. (PGPUB 20110156742), hereinafter as Yuan.
Regarding claim 2, Jang and Kwon teach a device as in rejection of claim 1,
But not expressly compare compressed data with info of matching and mismatching.
Yuan teaches when read data transmitted through all transmission paths of any data input/output pin is the same, the plurality of pieces of compressed data are configured to indicate that the memory is normal if compressed data corresponding to each data input/output pin indicates that all bits of data in read data transmitted through transmission paths corresponding to the data input/output pin are the same; or the plurality of pieces of compressed data are configured to indicate that the memory is faulty if compressed data corresponding to each of some data input/output pins indicates that a part of data in read data transmitted through transmission paths corresponding to the data input/output pin is different ([0026]).
Since Yuan and Jang are both from the same field of semiconductor memory device, the purpose disclosed by Yuan would have been recognized in the pertinent art of Jang.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use compressed data to flag test data for the purpose of identify mismatching of test data.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827
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