Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 line 1 from bottom recites the limitation "the data curtailment process". There is insufficient antecedent basis for this limitation in the claim.
Claim 10 line 2 recites “a program status fail and/or an erase fail status”, it is unclear it is for a program status fail, or an erase fail status or both.
Any claim not specifically mentioned above, is rejected due to its dependency on the rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, 14-15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alhussien et al., US 20220044736, hereinafter Alhussien, in view of Majerus et al., US 11107509, hereinafter Majerus.
As per claim 1, Alhussien teaches A method comprising:
setting, by a controller (Fig.1 Memory Sub-System Controller ,115), a read voltage from a set of read voltages to be applied to memory cells of a memory device (Fig.1 Memory Device, 130);
issuing, by the controller, a bit count command ([0148] a calibration command) to the memory device to apply the read voltage to the memory cells to count a number of memory cells of the memory cells storing a zero bit;
repeating, by the controller, the setting and issuing operations until remaining read voltages of the set of read voltages have been applied to the memory cells to determine the number of memory cells storing the zero bit at each remaining read voltage applied to the memory cells;
receiving, by the controller, bit count data in response to the repeating operation, wherein the bit count data represents the number of memory cells of the memory cells storing the zero bit at each read voltage applied to the memory cells; and
(Fig. 23, 303, 305, 307; [0151] the memory device 130 can ramp up the read voltage applied on the group of memory cells to Vc to count the number of memory cells that output one (or zero) as the bit count CC at VC. [0150-[0154])
providing, by the controller,
([0137]-[0139]; [0150] At block 305, the memory device 130 determines a set of signal and noise characteristics of the group of memory cells from a result of reading the group of memory cells at the plurality of test voltages.)
Alhussien teaches all claim limitations above EXCEPT debug data
Majerus teaches debug data
(Fig. 7; 9:3-16; 12:59-13:5.......collect histogram data. This data can be used as an indicator of health of the memory device, which can be used directly to debug the memory device from saving and reporting VT profile... Valley depth or shape can be used as an indicator of data health.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien to incorporate the teaching of the limitation indicated above from Majerus as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
As per claim 15, Alhussien teaches A system for generating debug data for debugging a memory device (Fig.1 Memory Device, 130) comprising memory cells, the system comprising:
a processing device coupled to the memory device, the processing device to perform operations comprising:
generating the ([0148] a calibration command) and a second read voltage is applied to the memory cells to count the number of memory cells storing the zero bit at the second read voltage based on a second bit count command ([0148] a calibration command) to produce bit count data, the bit count data representing a number of memory cells of the memory cells storing the zero bit at each read voltage applied to the memory cells, and
the
Alhussien teaches all claim limitations above EXCEPT debug data
Majerus teaches debug data
(Fig. 7; 9:3-16; 12:59-13:5.......collect histogram data. This data can be used as an indicator of health of the memory device, which can be used directly to debug the memory device from saving and reporting VT profile... Valley depth or shape can be used as an indicator of data health.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien to incorporate the teaching of the limitation indicated above from Majerus as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
As per claim 19, Alhussien teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
setting a read voltage of a set of read voltages to be applied to memory cells of a memory device (Fig.1 Memory Device, 130);
issuing a bit count command ([0148] a calibration command) to the memory device to apply the read voltage to the memory cells to count a number of memory cells of the memory cells storing a zero bit;
repeating the setting and issuing operations until remaining read voltages of the set of read voltages have been applied to the memory cells to determine the number of memory cells storing the zero bit at each remaining read voltage applied to the memory cells;
receiving bit count data in response to the repeating operation, wherein the bit count data represents the number of memory cells of the memory cells storing the zero bit at each read voltage applied to the memory cells; and
(Fig. 23, 303, 305, 307; [0151] the memory device 130 can ramp up the read voltage applied on the group of memory cells to Vc to count the number of memory cells that output one (or zero) as the bit count CC at VC. [0150-[0154])
outputting
([0137]-[0139]; [0150] At block 305, the memory device 130 determines a set of signal and noise characteristics of the group of memory cells from a result of reading the group of memory cells at the plurality of test voltages.)
Alhussien teaches all claim limitations above EXCEPT debug data
Majerus teaches debug data
(Fig. 7; 9:3-16; 12:59-13:5.......collect histogram data. This data can be used as an indicator of health of the memory device, which can be used directly to debug the memory device from saving and reporting VT profile... Valley depth or shape can be used as an indicator of data health.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien to incorporate the teaching of the limitation indicated above from Majerus as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
As per claim 2, Alhussien-Majerus teaches The method as applied above in claim 1, Alhussien further teaches wherein the providing comprises evaluating, by the controller, each read voltage applied to the memory cells relative to thresholds to identify:
read voltages associated with one or more peaks of a voltage threshold (VT) distribution for the memory cells corresponding to peak read voltages; and
read voltages associated with one or more valleys of the VT distribution for the memory cells corresponding to valley read voltages.
([0137]-[0139]; [0153])
As per claim 3, Alhussien-Majerus teaches The method as applied above in claim 2, Alhussien further teaches further comprising providing, by the controller, an estimate of the VT distribution for the memory cells based on the valley and peak read voltages. ([0153])
As per claim 5, Alhussien-Majerus teaches The method as applied above in claim 3, Alhussien further teaches wherein the providing further comprises determining, by the controller, for each of the valley and peak read voltages a bit count value, the bit count value representing the number of memory cells of the memory cells that store a respective logical state of logical states at a corresponding read voltage of the set of read voltages applied to the memory cells, the estimate VT distribution being further provided based on bit count values for the valley and peak read voltages. ([0016], [0137]-[0139]; [0153])
As per claim 6, Alhussien-Majerus teaches The method as applied above in claim 1, Alhussien further teaches further comprising providing, by the controller, an estimate voltage threshold (VT) distribution for the memory cells based on the debug data. ([0016], [0137]-[0139]; [0153])
As per claim 20, Alhussien-Majerus teaches The The non-transitory computer-readable storage medium as applied above in claim 19, Alhussien further teaches wherein the instructions when executed by the processing device cause the processing device to perform operations further comprising estimating a voltage threshold (VT) distribution for the memory cells based on the debug data. ([0016], [0137]-[0139]; [0153])
As per claim 14, Alhussien-Majerus teaches The method as applied above in claim 1, Alhussien further teaches wherein the memory device is a Not-AND (NAND) memory device and the cells are multi-level cells. ([0046])
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alhussien et al., US 20220044736, hereinafter Alhussien, in view of Majerus et al., US 11107509, hereinafter Majerus, in further view of Roy et al., US 9384842, hereinafter Roy.
As per claim 4, Alhussien-Majerus teaches The method as applied above in claim 3, EXCEPT wherein the estimate VT distribution is provided prior to execution of an erase operation that erases data stored at the memory cells.
Roy teaches wherein the estimate VT distribution is provided prior to execution of an erase operation that erases data stored at the memory cells.
(4:17-20, A first OOF Vt distribution curve 210 represents a distribution of OOF threshold voltages carried by a first set of NVM cells before any program or erase operations have been performed on the first set of NVM cells)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien-Majerus to incorporate the teaching of the limitation indicated above from Roy as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
Claim(s) 7-13, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alhussien et al., US 20220044736, hereinafter Alhussien, in view of Majerus et al., US 11107509, hereinafter Majerus, in further view of Veluswamy et al., US 20220413737 hereinafter Veluswamy.
As per claim 7, Alhussien-Majerus teaches The method as applied above in claim 1, EXCEPT wherein the setting, issuing, and repeating operations are implemented for a debug data collection process, and the method further comprising:
monitoring, by the controller, the memory device for a memory failure condition;
executing, by the controller, a data loss curtailment process in response to detecting the memory failure condition; and
executing, by the controller, the debug data collection process in response to executing the data curtailment process.
Veluswamy teaches
wherein the setting, issuing, and repeating operations are implemented for a debug data collection process, and the method further comprising:
monitoring, by the controller, the memory device for a memory failure condition;
executing, by the controller, a data loss curtailment process in response to detecting the memory failure condition; and
executing, by the controller, the debug data collection process in response to executing the data curtailment process.
(Fig.3, [0077] In response to the block 310 determining the failure index (FI) to be less than the threshold, at a block 312, the management module executes the command to securely erase the at least one nonvolatile memory block in the data storage device,; [0048] usage information module 220-2 for collecting usage information of memory devices (e.g., NVM devices 140) including one or more of a retired block count 230, power-on hours 232, write amplification metric 234, program fail count 236, erase fail count 238, and percent of drive life metric 240;)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien-Majerus to incorporate the teaching of the limitation indicated above from Veluswamy as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
As per claim 16, Alhussien-Majerus teaches The system of claim applied above in claim 15, EXCEP wherein the operations further comprising:
monitoring the memory device for a memory failure condition;
executing a data loss curtailment process in response to detecting the memory failure condition; and
executing the debug data collection process in response to executing the data loss curtailment process.
Veluswamy teaches wherein the operations further comprising:
monitoring the memory device for a memory failure condition;
executing a data loss curtailment process in response to detecting the memory failure condition; and
executing the debug data collection process in response to executing the data loss curtailment process.
(Fig.3, [0077] In response to the block 310 determining the failure index (FI) to be less than the threshold, at a block 312, the management module executes the command to securely erase the at least one nonvolatile memory block in the data storage device,; [0048] usage information module 220-2 for collecting usage information of memory devices (e.g., NVM devices 140) including one or more of a retired block count 230, power-on hours 232, write amplification metric 234, program fail count 236, erase fail count 238, and percent of drive life metric 240;)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien-Majerus to incorporate the teaching of the limitation indicated above from Veluswamy as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
As per claim 8, Alhussien-Majerus-Veluswamy teaches The method as applied above in claim 7, Veluswamy further teaches wherein the memory device includes a memory block that include the memory cells, and the memory failure condition is a block failure condition for the memory block. ([0044]-0045])
As per claim 9, Alhussien-Majerus-Veluswamy teaches The method as applied above in claim 8, Veluswamy further teaches further comprising retiring, by the controller, the memory block in response to executing the debug data collection process. ([0048] usage information module 220-2 for collecting usage information of memory devices (e.g., NVM devices 140) including one or more of a retired block count 230, power-on hours 232, write amplification metric 234, program fail count 236, erase fail count 238, and percent of drive life metric 240;)
As per claim 10, Alhussien-Majerus-Veluswamy teaches The method as applied above in claim 9, Veluswamy further teaches wherein the block failure condition comprises a program status fail and/or an erase fail status. ([0048] usage information module 220-2 for collecting usage information of memory devices (e.g., NVM devices 140) including one or more of a retired block count 230, power-on hours 232, write amplification metric 234, program fail count 236, erase fail count 238, and percent of drive life metric 240;)
As per claim 11, Alhussien-Majerus teaches The method as applied above in claim 1, EXCEPT
wherein the setting, issuing, and repeating operations are implemented for a debug data collection process, the memory device comprising a retired memory block that include the memory cells, and the method further comprising:
receiving, by the controller, an erase command to remove data being stored on the memory device;
determining, by the controller, that the data is stored in the retired memory block in response to receiving the erase command; and
executing, by the controller, the debug data collection process in response to determining that the data is stored in the retired memory block.
Veluswamy teaches
wherein the setting, issuing, and repeating operations are implemented for a debug data collection process, the memory device comprising a retired memory block that include the memory cells, and the method further comprising:
receiving, by the controller, an erase command to remove data being stored on the memory device;
determining, by the controller, that the data is stored in the retired memory block in response to receiving the erase command; and
executing, by the controller, the debug data collection process in response to determining that the data is stored in the retired memory block.
([0046] The garbage collection module may further provide, in response to the failure index being less than a threshold, means for executing the command to securely erase the at least one nonvolatile memory block)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien-Majerus to incorporate the teaching of the limitation indicated above from Veluswamy as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
As per claim 17, Alhussien-Majerus teaches The system as applied above in claim 15, EXCEPT wherein the memory device includes a retired memory block that includes the memory cells, and the operations further comprising:
receiving an erase command to remove data being stored on the memory device;
determining that the data is stored in the retired memory block; and
executing the debug data collection process in response to determining that the data is stored in the retired memory block.
Veluswamy teaches
wherein the memory device includes a retired memory block that includes the memory cells, and the operations further comprising:
receiving an erase command to remove data being stored on the memory device;
determining that the data is stored in the retired memory block; and
executing the debug data collection process in response to determining that the data is stored in the retired memory block.
([0046] The garbage collection module may further provide, in response to the failure index being less than a threshold, means for executing the command to securely erase the at least one nonvolatile memory block)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Alhussien-Majerus to incorporate the teaching of the limitation indicated above from Veluswamy as indicated above, in order to provide reliable data in a shorter time (Majerus, 2:2).
As per claim 12, Alhussien-Majerus-Veluswamy teaches The method as applied above in claim 11, Veluswamy further teaches further comprising erasing, by the controller, the retired memory block to erase the data in response to executing the debug data collection process. ([0046] The garbage collection module may further provide, in response to the failure index being less than a threshold, means for executing the command to securely erase the at least one nonvolatile memory block)
As per claim 13, Alhussien-Majerus-Veluswamy teaches The method as applied above in claim 11, Veluswamy further teaches wherein the erase command comprises a secure erase command, a sanitize erase command or a Non-Volatile Memory (NVM) format command. (Fig.3, 312, at a block 312, the management module executes the command to securely erase the at least one nonvolatile memory block in the data storage device; Fig. 2; [0039] The secure erase module further provides a means for calculating a failure index that the at least one nonvolatile memory block will be securely erased;)
As per claim 18, Alhussien-Majerus-Veluswamy teaches The system as applied above in claim 16, Alhussien teaches further comprising computing an estimate voltage threshold (VT) distribution for the memory cells based on the debug data. ([0016], [0137]-[0139]; [0153])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Clark et al., US 20100185895, FAILURE-SPECIFIC DATA COLLECTION AND RECOVERY FOR ENTERPRISE STORAGE CONTROLLERS
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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