DETAILED ACTION
This action is responsive to the following communications: the Application filed on November 13, 2024, the Foreign Priority papers retrieved on November 27, 2023 and March 21, 2024 and the Information Disclosure Statements filed on November 13, 2024 and April 4, 2025.
Claims 1-20 are pending. Claims 1, 10 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDSs) filed on November 13, 2024 and April 4, 2025. These IDSs have been considered.
Claim Objections
Claims 2-3 are objected to because of the following informalities:
In claim 2, line 3, “a refresh cycle of the each bank array” should be --a refresh cycle of each bank array--.
In claim 3, line 3, “refresh cycles of first bank arrays of corresponding to first” should be --refresh cycles of first bank arrays corresponding to first--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6 and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
With respect to claim 6, the claim recites “the second temperature sensor is included in a second channel area within the logic die”. The specification describes a logic die including a temperature sensor and describes channel areas associated with core dies. However, the specification does not appear to describe a “channel area within the logic die” or show possession of a logic die having a “channel area” containing the second temperature sensor. Accordingly, the original disclosure does not reasonably convey possession of the limitation “the second temperature sensor is included in a second channel area within the logic die”.
With respect to claim 8, the claim recites estimation “based on a number of the plurality of bank arrays being less than a number of plurality of the first temperature sensors and the second temperature sensor”. However, the specification describes the opposite condition: when the number of temperature sensors is less than the number of bank arrays, the array temperature estimation circuit may estimate the temperature of the bank array to which no temperature sensor is assigned using methods such as interpolation, extrapolation, or a temperature sensor disposed in a horizontally adjacent channel area [para. 102 and 106]. Because the specification supports estimation when sensors are fewer than banks, but claim 8 recites estimation when bank arrays are fewer than sensors, the original disclosure does not reasonably convey possession of the claimed condition.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to independent claim 1, the claim recites “the memory controller is configured to independently adjust refresh cycles of the plurality of bank arrays based on temperature values obtained from a plurality of first temperature sensors included in the plurality of channel areas and a second temperature sensor included in the logic die”. This limitation does not make clear whether each bank array has a corresponding refresh cycle, whether groups of bank arrays share refresh cycles, or how the claimed independent adjustment is distinguished from adjusting refresh cycles collectively. The term “independently” is therefore unclear whether refresh cycles are independently adjusted per bank array or per group of banks arrays. Claim 1 is further indefinite because “a second temperature sensor included in the logic die” lacks clear antecedent basis. The claim previously recites “at least one temperature sensor” in the logic die, but does not clearly identify whether the later recited “second temperature sensor” is the same temperature sensor, one of the “at least one temperature sensor”, or an additional temperature sensor. Thus, the metes and bounds of the claim are unclear. Claims 2-9 are rejected for inheriting this issue from claim 1.
With respect to claims 4 and 19, each claim recites “channel areas including the plurality of first temperature sensors are arranged alternatingly in the vertical direction”. However, the claims do not specify what elements alternate with what other elements, what alternating pattern is required, or whether the alternating arrangement is based on channel number, physical channel position, sensor position or another reference. Although the specification describes distributed temperature sensors in channel area and vertically stacked core dies, the claim language “arranged alternatingly” does not clearly define the required structure or arrangement. Therefore, the metes and bounds of the claims are unclear. Claims 5 and 20 are rejected for inheriting this issue from claims 4 and 19.
With respect to claim 8, the claim recites “based on a number of the plurality of bank arrays being less than a number of plurality of the first temperature sensors and the second temperature sensor”. In particular, the phrase “a number of plurality of the first temperature sensors and the second temperature sensor” lacks proper structure and does not clearly identify whether the claimed number refers to: the number of plurality of the first temperature sensors only, the number of plurality of the first temperature sensors plus the second temperature sensor, or some other number. Therefore, the metes and bounds of the claim are unclear. Claim 9 is rejected for inheriting this issue from claim 8.
With respect to independent claim 10, the claim recites “independently updating refresh cycles of a plurality of bank arrays included in each core die from among the plurality of core dies”. This limitation does not clearly define whether the refresh cycles are updated independently for each bank array, each group of bank arrays, each channel area or each core die. The claim recites “estimating temperature values corresponding to a plurality of bank arrays”, but then recites “updating refresh cycles of a plurality of bank arrays included in each core die”, which may or may not be the same plurality of bank arrays. Thus, the scope of the updating step is unclear. Claims 11-15 are rejected for inheriting this issue from claim 10.
With respect to claims 11-13, each claim recites based on the plurality of first temperature sensors and the second temperature sensor being respectively assigned to all bank arrays”. This phase is unclear because the claim combines a plurality of first temperature sensors with a second temperature sensor and then states that they are “respectively assigned” to all or some bank arrays. It is unclear how the single second temperature sensor in the logic die is “respectively assigned” to all or some bank arrays, and it is unclear which bank array corresponding to the second temperature sensor. The specification describes temperature sensors in the core dies being respectively assigned to bank arrays, and separately describes using a logic die’s temperature sensor to estimate temperatures of banks in the lowest core die. The claims do not clearly distinguish between those two concepts. Therefore, the scope of claims 11-13 is unclear. Claim 14 is rejected for inheriting this issue from claim 13.
With respect to claims 15 and 18, each claim recites “a refresh cycle of first bank arrays. The phrase uses the singular “a refresh cycle” with the plural “first bank arrays”. It is unclear whether each of the first bank arrays has a separate uploaded refresh cycle or whether all of the first bank arrays share a single refresh cycle. The same ambiguity applies to the phrase “a refresh cycle of second bank arrays”.
With respect to independent claim 16, the claim recites “the memory controller is further configured to independently adjust refresh cycles of the plurality of bank arrays included in the plurality of core dies based on temperature values obtained from the plurality of first temperature sensors and the second temperature sensor”. This limitation does not make clear whether refresh cycles are independently adjusted per bank array, per group of banks arrays, or per core die. Thus, the metes and bounds of the claim are unclear. Claims 17-20 are rejected for inheriting this issue from claim 16.
With respect to independent claim 17, the claim recites “estimate a temperature of each bank array” and then “adjust a refresh cycle of each of the plurality of bank arrays based on the estimated temperature values”. The claim does not clearly identify the antecedent basis for “the estimated temperature values”, because the claim previously recites “a temperature” rather than “estimated temperature values”. Thus, the scope of the claim is unclear. Claim 18 is rejected for inheriting this issue from claim 17.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 14 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 14 depends on claim 13 but appears to conflict in the location of the “remaining banks arrays.” Claim 13 requires “a first core die including the remaining banks arrays.” But, further dependent claim 14 conflicts with its antecedent claim by reciting the “a first channel area including the remaining bank arrays among channel areas included in the second core die.” In short, claim 13 requires the remaining bank arrays to be in the first core die, and its further dependent claim 14 requires the remaining bank arrays to be in the second core die. Thus, claim 14 does not clearly further limit claim 13 and does not clearly include all limitations of claim 13.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 10 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over O (US 20210225430) in view of Walker et al. (US 20140281311).
Regarding independent claim 1, O discloses a memory device [Fig. 1: 1000] comprising:
a plurality of core dies [Fig. 1: 1100-1800, each of the memory/processor in memory (PIM) dies 1100 to 1800 may be also referred to a “memory die”, a “core die”, an “FIM die”, or a “slave die”, para. 13], wherein each core die of the plurality of core dies comprises a plurality of channel areas including a plurality of bank arrays [each of the PIM dies 1100 to 1800 of the memory device 1000 may include a memory cell array MCA, para. 15. The PIM die 1100 may include the bank groups BG0 to BG15 and the banks BK0 to BK63 allocated to four channels CH1 to CH4, para. 25], and wherein the plurality of core dies are stacked in a vertical direction [see Fig. 2, the PIM die 1100 may be stacked on the buffer die 1900, and the PIM die 1200 may be stacked on the PIM die 1100, para. 13]; and
a logic die [Fig. 1: 1900] below the plurality of core dies [the buffer die 1900 may be also referred to as an “interface die”, a “logic die”, or a “master die”. The PIM die 1100 may be stacked on the buffer die 1900, para. 13], wherein the logic die comprises a memory controller [see Fig. 1, the buffer die 1900 may receive a command, data, signals, etc. transmitted from the memory controller 2100 through the interposer 3000, para. 16], wherein the memory controller is configured to transmit data to the plurality of channel areas and to receive data from the plurality of channel areas using a plurality of channels [the memory controller 2100 may select one of a plurality of PIM dies allocated to one channel, by using the stack identifier SID of a memory address. The memory controller 2100 may access one of a plurality of PIM dies allocated to one channel, by using a memory address. For example, when the stack identifier SID has a first logical value (i.e., SID0), the command and address signals CA and the data input/output signals DQ transmitted through the channels CH1 to CH4 may be associated with the PIM dies 1100 to 1400, para. 58 and 72].
However, O is silent with respect to the logic die comprises at least one temperature sensor and wherein the memory controller is configured to independently adjust refresh cycles of the plurality of bank arrays based on temperature values obtained from a plurality of first temperature sensors included in the plurality of channel areas and a second temperature sensor included in the logic die.
Walker et al. teach a memory device comprising a logic die [Fig. 2: 230], wherein the logic die comprises at least one temperature sensor [thermal sensors (TS) may be included in the logic die 230, para. 22] and wherein the memory controller is configured to independently adjust refresh cycles of the plurality of bank arrays based on temperature values obtained from a plurality of first temperature sensors included in the plurality of channel areas [the refresh rate may change for each channel or region of memory independently, based on the sample taken from the local temperature sensor, para. 30. Thermal Control Logic (TCL) (FIG. 2) may read temperature values periodically, from thermal sensors, of a plurality of regions of the memory system 130 and set a refresh rate for each of the plurality of regions of the memory system based on the temperatures, para. 32-33] and a second temperature sensor included in the logic die [thermal sensors (TS) may be included in the logic die 230, para. 22].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Walker et al. to the teaching of O such that modifying O’s stacked memory device to include the temperature-based refresh rate control as taught by Walker et al. to reduce unnecessary refresh in cooler regions and thereby improve performance or power usage while maintaining data retention in hotter regions [see Waler et al.’s para. 34 and 48-49].
Regarding claim 2, O in combination with Walker et al. teach the limitations with respect to claim 1.
Furthermore, Walker et al. disclose the memory controller is further configured to estimate a temperature of each bank array of the plurality of bank arrays based on the temperature values, and to adjust a refresh cycle of the each bank array based on the estimated temperature [the memory dies 210 and 220 may include two or more regions of memory cells. Two or more of the plurality of regions of memory cells may each include a thermal sensor (TS) for sensing a temperature of a corresponding region of memory cells. Temperature Control Logic (TCL) may read the state of the thermal sensors and can be used to adjust the refresh rates of each region based on the temperature of that region. The TCL may read a plurality of thermal sensors, at least two of the plurality of thermal sensors corresponding to different regions of memory cells, para. 23 and 32-33].
Regarding claim 3, O in combination with Walker et al. teach the limitations with respect to claim 2.
Furthermore, Walker et al. disclose the memory controller is further configured to:
update, to a first cycle, refresh cycles of first bank arrays of corresponding to first estimated temperature values that are greater than or equal to a reference temperature value [Walker et al. provide Table 1 that is an example of how the Temperature Gradient Categories may be used to control refresh, para. 29. As can be seen in Table 1, the refresh rate may change for each channel or region of memory independently, based on the sample taken from the local temperature sensor. When the sample from the TS identifies the temperature is in the Hot2x region the device, or channel will be refreshed twice as fast as specified, para. 30], and
update, to a second cycle, refresh cycles of second bank arrays corresponding to second estimated temperature values that are less than the reference temperature value [when the samples show the device is in the Cold region the device or channel receives only 1/8 the normal refresh commands because the retention of the device is better when cold, para. 30].
However, Walker et al. are silent with respect to the first bank arrays are included in a first core die from among the plurality of core dies and the second bank arrays are included in the first core die.
O discloses the first bank arrays are included in a first core die from among the plurality of core dies and the second bank arrays are included in the first core die [each of the memory/processor in memory (PIM) dies 1100 to 1800 may be also referred to a “memory die”, a “core die”, an “FIM die”, or a “slave die”, para. 13. The PIM die 1100 may include the bank groups BG0 to BG15 and the banks BK0 to BK63 allocated to four channels CH1 to CH4, para. 25].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Walker et al. to the teaching of O such that applying different refresh rates as taught by Walker et al. to O’s different banks within the same core die to reduce unnecessary refresh in cooler regions and thereby improve performance or power usage while maintaining data retention in hotter regions [see Waler et al.’s para. 34 and 48-49].
Regarding claim 7, O in combination with Walker et al. teach the limitations with respect to claim 1.
Furthermore, O discloses a bank array is included in a channel area from among channel areas of a lowest core die from among the plurality of core dies [see Fig. 1, PIM die 1100 is the lowest core die above the buffer die, para. 13. The PIM die 1100 may include the bank groups BG0 to BG15 and the banks BK0 to BK63 allocated to four channels CH1 to CH4; as in the channel CH1 exemplified in FIG. 3, bank groups and banks for each channel may be implemented in the PIM die 1100, para. 25].
wherein the channel area vertically overlaps an area including the logic die [see Fig. 2, The PIM die 1100 may be stacked on the buffer die 1900 that is referred to as an “interface die”, a “logic die”, or a “master die”, para. 13].
However, O is silent with respect to a second temperature sensor within the logic die and wherein the memory controller is further configured to estimate a temperature value corresponding to the bank array based on a temperature value corresponding to the second temperature sensor.
Walker et al. teach a second temperature sensor within the logic die [thermal sensors (TS) may be included in the logic die 230, para. 22] and wherein the memory controller is further configured to estimate a temperature value corresponding to the bank array based on a temperature value corresponding to the second temperature sensor [Temperature Control Logic (TCL) may read the state of the thermal sensors and can be used to adjust the refresh rates of each region based on the temperature of that region, para. 23].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Walker et al. to the teaching of O such that using a temperature value from a temperature sensor in the logic die as taught by Waler et al. to estimate the temperature of a bank array in a vertically overlapping channel area of the lowest core die as taught by O to reduce unnecessary refresh in cooler regions and thereby improve performance or power usage while maintaining data retention in hotter regions [see Waler et al.’s para. 34 and 48-49].
Regarding independent claim 10, O discloses a memory device [Fig. 1: 1000] comprising:
a plurality of vertically stacked core dies [Fig. 1: 1100-1800, each of the memory/processor in memory (PIM) dies 1100 to 1800 may be also referred to a “memory die”, a “core die”, an “FIM die”, or a “slave die”, para. 13], a logic die below the plurality of core dies [the buffer die 1900 may be also referred to as an “interface die”, a “logic die”, or a “master die”. The PIM die 1100 may be stacked on the buffer die 1900, para. 13], and a plurality of bank arrays included in the plurality of core dies [each of the PIM dies 1100 to 1800 of the memory device 1000 may include a memory cell array MCA, para. 15. The PIM die 1100 may include the bank groups BG0 to BG15 and the banks BK0 to BK63 allocated to four channels CH1 to CH4, para. 25].
However, O is silent with respect to an operation method of a memory device, the method comprising:
obtaining a plurality of first temperature values from a plurality of first temperature sensors included in a plurality of vertically stacked core dies;
obtaining a second temperature value from a second temperature sensor included in a logic die below the plurality of core dies;
estimating temperature values corresponding to a plurality of bank arrays included in the plurality of core dies, based on the plurality of first temperature values and the second temperature value; and
based on the estimated temperature values, independently updating refresh cycles of a plurality of bank arrays included in each core die from among the plurality of core dies.
Walker et al. teach an operation method of a memory device [see Fig. 3], the method comprising:
obtaining a plurality of first temperature values from a plurality of first temperature sensors included in a plurality of vertically stacked core dies [The memory system 200 may include memory dies. Each of the plurality of memory dies may include at least one thermal sensors (TS), para. 22];
obtaining a second temperature value from a second temperature sensor included in a logic die below the plurality of core dies [The memory system 200 may include independent logic. Thermal sensors (TS) may be included in the logic die 230, para. 22];
estimating temperature values corresponding to a plurality of bank arrays included in the plurality of core dies, based on the plurality of first temperature values and the second temperature value [Fig. 3: step 310, Thermal Control Logic (TCL) (FIG. 2) may read temperature values periodically, from thermal sensors, of a plurality of regions of the memory system 130, para. 32]; and
based on the estimated temperature values, independently updating refresh cycles of a plurality of bank arrays included in each core die from among the plurality of core dies [Fig. 3: step 320, the Thermal Control Logic (TCL) may set a refresh rate for each of the plurality of regions of the memory system based on the temperatures, para. 33].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Walker et al. to the teaching of O such that modifying O’s stacked memory device to include the temperature-based refresh rate control as taught by Walker et al. to reduce unnecessary refresh in cooler regions and thereby improve performance or power usage while maintaining data retention in hotter regions [see Waler et al.’s para. 34 and 48-49].
Regarding claim 15, O in combination with Walker et al. teach the limitations with respect to claim 10.
Furthermore, Walker et al. disclose wherein the independently updating the refresh cycles comprises:
update, to a first cycle, a refresh cycle of first bank arrays of corresponding to first estimated temperature values that are greater than or equal to a reference temperature value [Walker et al. provide Table 1 that is an example of how the Temperature Gradient Categories may be used to control refresh, para. 29. As can be seen in Table 1, the refresh rate may change for each channel or region of memory independently, based on the sample taken from the local temperature sensor. When the sample from the TS identifies the temperature is in the Hot2x region the device, or channel will be refreshed twice as fast as specified, para. 30], and
update, to a second cycle, a refresh cycle of second bank arrays corresponding to second estimated temperature values that are less than the reference temperature value [when the samples show the device is in the Cold region the device or channel receives only 1/8 the normal refresh commands because the retention of the device is better when cold, para. 30].
However, Walker et al. are silent with respect to the first bank arrays are included in a first core die from among the plurality of core dies and the second bank arrays are included in the first core die.
O discloses the first bank arrays are included in a first core die from among the plurality of core dies and the second bank arrays are included in the first core die [each of the memory/processor in memory (PIM) dies 1100 to 1800 may be also referred to a “memory die”, a “core die”, an “FIM die”, or a “slave die”, para. 13. The PIM die 1100 may include the bank groups BG0 to BG15 and the banks BK0 to BK63 allocated to four channels CH1 to CH4, para. 25].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Walker et al. to the teaching of O such that applying different refresh rates as taught by Walker et al. to O’s different banks within the same core die to reduce unnecessary refresh in cooler regions and thereby improve performance or power usage while maintaining data retention in hotter regions [see Waler et al.’s para. 34 and 48-49].
Regarding independent claim 16, O discloses a semiconductor device [see Fig. 1] comprising:
an interposer [Fig. 1: 3000] comprising conductive materials [para. 18];
a stacked memory device on the interposer [Fig. 1: 1000], wherein the stacked memory device comprises a plurality of core dies and a buffer die [see Fig. 2, the memory device 1000 may include processing in memory/processor in memory (PIM) dies 1100 to 1800 and a buffer die 1900, para. 13], wherein the plurality of core dies comprises a plurality of bank arrays [each of the PIM dies 1100 to 1800 of the memory device 1000 may include a memory cell array MCA, para. 15. The PIM die 1100 may include the bank groups BG0 to BG15 and the banks BK0 to BK63 allocated to four channels CH1 to CH4, para. 25], and wherein the buffer die comprises a first interface circuit [the buffer die 1900 may include a physical layer (PHY) 1980, buffering circuits, or interface circuits that receive and amplify the above signals, para. 16]; and
a system-on-chip on the interposer [Fig. 1: 2000], wherein the system-on-chip comprises a second interface circuit and a memory controller, wherein the second interface circuit is configured to communicate with the first interface circuit through the conductive materials [the interposer 3000 may provide physical paths that connect between the memory device 1000 and the PHY 2180 of the system on chip 2000 and are formed of conductive materials for an electrical connection, para. 18], and wherein the memory controller is configured to control the plurality of core dies [the system on chip 2000 may include the memory controller 2100 that controls the memory device 1000 and performs a data input/output with the memory device 1000, para. 17].
However, O is silent with respect to the plurality of core dies comprises a plurality of first temperature sensors, the buffer die comprises a second temperature sensor and wherein the memory controller is further configured to independently adjust refresh cycles of the plurality of bank arrays included in the plurality of core dies based on temperature values obtained from the plurality of first temperature sensors and the second temperature sensor.
Walker et al. teach a memory device comprising the plurality of core dies comprises a plurality of first temperature sensors [the memory system 200 may include memory dies and each of the plurality of memory dies may include at least one thermal sensors (TS), para. 22], the buffer die comprises a second temperature sensor [the memory system 200 may include independent logic die. Thermal sensors (TS) may be included in the logic die 230, para. 22] and wherein the memory controller is further configured to independently adjust refresh cycles of the plurality of bank arrays included in the plurality of core dies based on temperature values obtained from the plurality of first temperature sensors and the second temperature sensor [the refresh rate may change for each channel or region of memory independently, based on the sample taken from the local temperature sensor, para. 30. Thermal Control Logic (TCL) (FIG. 2) may read temperature values periodically, from thermal sensors, of a plurality of regions of the memory system 130 and set a refresh rate for each of the plurality of regions of the memory system based on the temperatures, para. 32-33. The memory controller 120 or other block may read the data from the TCL or the TCL may transmit the required changes to the processor 110, para. 25].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Walker et al. to the teaching of O such that modifying O’s stacked memory device to include the temperature-based refresh rate control as taught by Walker et al. to reduce unnecessary refresh in cooler regions and thereby improve performance or power usage while maintaining data retention in hotter regions [see Waler et al.’s para. 34 and 48-49].
Regarding claim 17, O in combination with Walker et al. teach the limitations with respect to claim 16.
Furthermore, Walker et al. disclose the memory controller is further configured to estimate a temperature of each bank array of the plurality of bank arrays based on the temperature values, and adjust a refresh cycle of each of the plurality of bank arrays based on the estimated temperature values [the memory dies 210 and 220 may include two or more regions of memory cells. Two or more of the plurality of regions of memory cells may each include a thermal sensor (TS) for sensing a temperature of a corresponding region of memory cells. Temperature Control Logic (TCL) may read the state of the thermal sensors and can be used to adjust the refresh rates of each region based on the temperature of that region. The TCL may read a plurality of thermal sensors, at least two of the plurality of thermal sensors corresponding to different regions of memory cells, para. 23 and 32-33].
Regarding claim 18, O in combination with Walker et al. teach the limitations with respect to claim 17.
Furthermore, Walker et al. disclose the memory controller is further configured to:
update, to a first cycle, a refresh cycle of first bank arrays corresponding to first estimated temperature values that are greater than or equal to a reference temperature value [Walker et al. provide Table 1 that is an example of how the Temperature Gradient Categories may be used to control refresh, para. 29. As can be seen in Table 1, the refresh rate may change for each channel or region of memory independently, based on the sample taken from the local temperature sensor. When the sample from the TS identifies the temperature is in the Hot2x region the device, or channel will be refreshed twice as fast as specified, para. 30], and
update, to a second cycle, refresh cycles of second bank arrays corresponding to second estimated temperature values that are less than the reference temperature value [when the samples show the device is in the Cold region the device or channel receives only 1/8 the normal refresh commands because the retention of the device is better when cold, para. 30].
However, Walker et al. are silent with respect to the first bank arrays are included in a first core die from among the plurality of core dies and the second bank arrays are included in the first core die.
O discloses the first bank arrays are included in a first core die from among the plurality of core dies and the second bank arrays are included in the first core die [each of the memory/processor in memory (PIM) dies 1100 to 1800 may be also referred to a “memory die”, a “core die”, an “FIM die”, or a “slave die”, para. 13. The PIM die 1100 may include the bank groups BG0 to BG15 and the banks BK0 to BK63 allocated to four channels CH1 to CH4, para. 25].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Walker et al. to the teaching of O such that applying different refresh rates as taught by Walker et al. to O’s different banks within the same core die to reduce unnecessary refresh in cooler regions and thereby improve performance or power usage while maintaining data retention in hotter regions [see Waler et al.’s para. 34 and 48-49].
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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