DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 1-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 26 February 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 18 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu et al. (hereinafter “Liu” US 2025 / 0029542).
As pertaining to Claim 18, Liu discloses (see Fig. 1D) a gate driver (11, 12, 13) comprising (see Page 2, Para. [0016]-[0019] and [0021]-[0022]):
a carry generator (11) which generates a carry signal (Cas(C)) based on a previous carry signal (Cas(C-1)), a first clock signal (CLK1), a second clock signal (CLK2) and a low power voltage (VGL); and
a gate signal masking circuit (13, 12) connected to the carry generator (11),
wherein the carry generator (11) comprises:
a pull-up switching element (Tto1) which pulls up the carry signal (Cas(C)) in response to a signal of a first control node (N1); and
a pull-down switching element (Tto2) which pulls down the carry signal (Cas(C)) in response to a signal of a second control node (N2),
wherein the gate signal masking circuit (13, 12) outputs a gate pulse (Scan(C)) or does not output the gate pulse (Scan(C)) based on the signal of the second control node (N2), a first enable signal (FDL) and a second enable signal (N21), and
wherein the second enable signal (N21) has an inverted waveform of a waveform of the first enable signal (FDL; see Page 3 through Page 4, Para. [0027]-[0028], [0032], [0037]-[0038], [0040], and [0045]-[0046]; and see Page 5 through Page 6, Para. [0059]-[0060]; and note that a second enable signal (N21) has an inverted waveform of a waveform of the first enable signal (FDL) in so much as the second enable signal (N21) and the first enable signal (FDL) both have high and low signal waveforms and, as such, a low second enable signal (N21) is an inverted waveform of a high first enable signal (FDL), and a high second enable signal (N21) is an inverted waveform of a low first enable signal (FDL); see Page 11, Para. [0108], for example, and see Figs. 2A-2D for example waveforms of (N21) and (FDL)).
As pertaining to Claim 25, Liu discloses (see Fig. 1D) a display apparatus (see Page 1, Para. [0001]) comprising:
a display panel (see Fig. 3A, for example) including a pixel (P; see Page 1, Para. [0005]);
a gate driver (101, 102, 200, 300, 400) which outputs a gate signal (via (GL)) to the pixel (P); and
a data driver (see (DL) receiving data signals from a driver) which outputs a data voltage (via (DL)) to the pixel (see Page 13, Para. [0135]; Page 14, Para. [0142]; and Page 15, Para. [0155]),
wherein (see Fig. 1D) the gate driver (11, 12, 13) comprises (see Page 2, Para. [0016]-[0019] and [0021]-[0022]):
a carry generator (11) which generates a carry signal (Cas(C)) based on a previous carry signal (Cas(C-1)), a first clock signal (CLK1), a second clock signal (CLK2) and a low power voltage (VGL); and
a gate signal masking circuit (13, 12) connected to the carry generator (11),
wherein the carry generator (11) comprises:
a pull-up switching element (Tto1) which pulls up the carry signal (Cas(C)) in response to a signal of a first control node (N1); and
a pull-down switching element (Tto2) which pulls down the carry signal (Cas(C)) in response to a signal of a second control node (N2),
wherein the gate signal masking circuit (13, 12) outputs a gate pulse (Scan(C)) or does not output the gate pulse (Scan(C)) based on the signal of the second control node (N2), a first enable signal (FDL) and a second enable signal (N21), and
wherein the second enable signal (N21) has an inverted waveform of a waveform of the first enable signal (FDL; see Page 3 through Page 4, Para. [0027]-[0028], [0032], [0037]-[0038], [0040], and [0045]-[0046]; and see Page 5 through Page 6, Para. [0059]-[0060]; and note that a second enable signal (N21) has an inverted waveform of a waveform of the first enable signal (FDL) in so much as the second enable signal (N21) and the first enable signal (FDL) both have high and low signal waveforms and, as such, a low second enable signal (N21) is an inverted waveform of a high first enable signal (FDL), and a high second enable signal (N21) is an inverted waveform of a low first enable signal (FDL); see Page 11, Para. [0108], for example, and see Figs. 2A-2D for example waveforms of (N21) and (FDL)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee et al. (hereinafter “Lee” US 2021 / 0407427).
As pertaining to Claim 26, Liu discloses (see Fig. 1D) an electronic apparatus (see Page 1, Para. [0001]) comprising:
a display panel (see Fig. 3A, for example) including a pixel (P; see Page 1, Para. [0005]);
a gate driver (101, 102, 200, 300, 400) which outputs a gate signal (via (GL)) to the pixel (P); and
a data driver (see (DL) receiving data signals from a driver) which outputs a data voltage (via (DL)) to the pixel (see Page 13, Para. [0135]; Page 14, Para. [0142]; and Page 15, Para. [0155]);
wherein (see Fig. 1D) the gate driver (11, 12, 13) comprises (see Page 2, Para. [0016]-[0019] and [0021]-[0022]):
a carry generator (11) which generates a carry signal (Cas(C)) based on a previous carry signal (Cas(C-1)), a first clock signal (CLK1), a second clock signal (CLK2) and a low power voltage (VGL); and
a gate signal masking circuit (13, 12) connected to the carry generator (11),
wherein the carry generator (11) comprises:
a pull-up switching element (Tto1) which pulls up the carry signal (Cas(C)) in response to a signal of a first control node (N1); and
a pull-down switching element (Tto2) which pulls down the carry signal (Cas(C)) in response to a signal of a second control node (N2),
wherein the gate signal masking circuit (13, 12) outputs a gate pulse (Scan(C)) or does not output the gate pulse (Scan(C)) based on the signal of the second control node (N2), a first enable signal (FDL) and a second enable signal (N21), and
wherein the second enable signal (N21) has an inverted waveform of a waveform of the first enable signal (FDL; see Page 3 through Page 4, Para. [0027]-[0028], [0032], [0037]-[0038], [0040], and [0045]-[0046]; and see Page 5 through Page 6, Para. [0059]-[0060]; and note that a second enable signal (N21) has an inverted waveform of a waveform of the first enable signal (FDL) in so much as the second enable signal (N21) and the first enable signal (FDL) both have high and low signal waveforms and, as such, a low second enable signal (N21) is an inverted waveform of a high first enable signal (FDL), and a high second enable signal (N21) is an inverted waveform of a low first enable signal (FDL); see Page 11, Para. [0108], for example, and see Figs. 2A-2D for example waveforms of (N21) and (FDL)).
Liu does not explicitly show the driving circuit configuration of the disclosed display panel. That is, Liu does not explicitly provide for a driving controller which controls the gate driver and the data driver; and a processor which outputs image data and an input control signal to the driving controller. However, this configuration is the well-known driving circuit configuration of a display panel and is implicit in the teachings of Liu.
Further, in the same field of endeavor, Lee discloses (see Fig. 2 and Fig. 11) an electronic apparatus (DD) comprising a display panel (DP) including a pixel (PX), a gate driver (SD1, SD2), and a data driver (200), wherein the gate driver (SD1, SD2) comprises (see Fig. 11) a carry generator (DC) and a gate signal masking circuit (MSC) analogous to that disclosed by Liu (see Page 10, Para. [0151]-[0154]), wherein (see Fig. 2) a driving controller (100) controls the gate driver (SD1, SD2) and the data driver (200), and a processor (now shown) outputs input image data (RGB) and an input control signal (CTRL) to the driving controller (100; see Page 4, Para. [0058]-[0060]). It is a goal of Lee to provide a means for reducing power consumption in a display device by controlling driving frequency via a gate signal masking circuit analogous that disclosed by Liu (see Page 1, Para. [0008] and Page 2, Para. [0020] of Lee; and see Page 1, Para. [0004] of Liu).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liu with the teachings of Lee, such that the electronic apparatus of Liu comprises a driving controller which controls the gate driver and the data driver and a processor which outputs image data and an input control signal to the driving controller, as suggested by Lee, in an attempt to reduce power consumption using methods and structures that are well-known in the art and directly applicable to the structure disclosed by Liu.
Allowable Subject Matter
Claims 19-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the gate driver as recited in independent Claim 18 in combination with the structural features recited in dependent Claim 19. Claims 20-24 are directed to allowable subject matter due to their dependency from Claim 19.
Specifically, none of the references relied upon by the examiner teach or fairly suggest the gate driver of independent Claim 18, wherein the gate signal masking circuit comprises “a first switching element including a control electrode connected to a masking control node, a first electrode connected to the first control node and a second electrode connected to a third control node; a second switching element including a control electrode connected to the second control node, a first electrode which receives a masking power signal and a second electrode connected to a first intermediate node; a third switching element including a control electrode which receives the first enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the masking control node; a fourth switching element including a control electrode which receives the second enable signal, a first electrode connected to the masking control node and a second electrode connected to a second intermediate node; and a fifth switching element including a control electrode connected to the second control node, a first electrode connected to the second intermediate node and a second electrode which receives a second low power voltage” as recited in Claim 19.
The features of Claim 19 are disclosed by the originally filed drawings at Figure 7 and are characterized by first switching element (S1) and second through fifth switching elements (S2), (S3), (S4), and (S5). As shown, a first switching transistor (S1) is controlled by a masking control node (S-node) in order to control a driving frequency according to a second switching transistor (S2) and a fifth switching transistor (S5) having control electrodes connected to a “second control node” or Q-node (Q) and respective electrodes providing a masking power signal and a low power voltage, as well as a third switching transistor (T3) and a fourth switching transistor (T4) providing output signals to the masking control node (S-node) based on a voltage at the “second control node” or Q-node (Q) and first and second enable signals (EN, ENB), respectively.
As pertaining to the most relevant prior art relied upon by the examiner, Liu et al. (US 2025 / 0029542) discloses all of the features of independent Claim 18 at least at Figure 1D. Further, as shown in Figure 1D, Liu et al. suggests that the gate signal masking circuit (13, 12) comprises a first switching element (Tf2) including a control electrode (i.e., a gate electrode) connected to a masking control node (X), a first electrode (i.e., a lower electrode) connected to a first control node (N1) and a second electrode (i.e., an upper electrode) connected to a third control node (N3). Liu et al. further suggests a gate signal masking circuit that includes a combination of switching elements (Tst1, Tst2, Tf1, Tf3) configured to generate signals to drive the masking control node (X). In this regard, Liu et al. discloses second and fifth switching elements (Tst2, Tf1) comprising control electrodes connected to the second control node (N2), as well as a third switching element (Tst1) comprising a control electrode that receives the first enable signal (FDL) and a fourth switching element (Tf3) comprising a control electrode that receives the second enable signal (N21; see Page 3 through Page 4, Para. [0027]-[0028], [0032], [0037]-[0038], [0040], and [0045]-[0046]; and see Page 5 through Page 6, Para. [0059]-[0060]).
However, the structural configuration of the gate signal masking circuit disclosed by Liu et al. neither discloses nor suggests the structural configuration as recited in Claim 19. In fact, none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the gate driver as recited in independent Claim 18 in combination with the structural features recited in dependent Claim 19. The claimed structural configuration appears to be suggested solely by the applicant’s disclosure.
Response to Arguments
Applicant's arguments filed 07 July 2026 have been fully considered but they are not persuasive. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, namely Liu, teach or fairly suggest the newly recited feature wherein “the second enable signal has an inverted waveform of a waveform of the first enable signal” (see Remarks at Pages 12 through 14). The examiner respectfully disagrees. In fact, Liu explicitly discloses that a second enable signal (N21) has an inverted waveform of a waveform of the first enable signal (FDL) in so much as the second enable signal (N21) and the first enable signal (FDL) both have high and low signal waveforms and, as such, a low second enable signal (N21) is an inverted waveform of a high first enable signal (FDL), and a high second enable signal (N21) is an inverted waveform of a low first enable signal (FDL; see Page 11, Para. [0108], for example, and see Figs. 2A-2D for example waveforms of (N21) and (FDL)).
For at least these reasons, the rejection of Claims 18, 25, and 26 is maintained. Claims 19-24 remain objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The prior art is replete with references suggesting the implementation of gate signal masking circuits to provide control of a display driving frequency. At least In et al. (US 9,886,891), Lee et al. (US 11,373,600) corresponding to Lee et al. (US 2021 / 0407427), Cho et al. (US 11,244,629), Kim et al. (US 11,423,843), and Jeoung et al. (US 2017 / 0025068) suggest such features.
A number of commonly assigned references disclose a gate signal masking circuit having a structure similar to that recited in Claims 18 and 19. For example, Cha et al. (US 12,555,537) at Figure 13, Kim et al. (US 11,996,026) at Figure 3, and Kim et al. (US 12,518,678) at Figure 4 all disclose such structures. However, none of the claims as recited in these cited references appear to be directed to the specific structural embodiment of Claims 18 and 19, wherein “a first switching element including a control electrode connected to a masking control node, a first electrode connected to the first control node and a second electrode connected to a third control node; a second switching element including a control electrode connected to the second control node, a first electrode which receives a masking power signal and a second electrode connected to a first intermediate node; a third switching element including a control electrode which receives the first enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the masking control node; a fourth switching element including a control electrode which receives the second enable signal, a first electrode connected to the masking control node and a second electrode connected to a second intermediate node; and a fifth switching element including a control electrode connected to the second control node, a first electrode connected to the second intermediate node and a second electrode which receives a second low power voltage.”
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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