DETAILED ACTION
This action is responsive to the following communications: the Application filed on November 14, 2024, the Foreign Priority papers retrieved on November 21, 2023, January 3, 2024 and April 4, 2024, and the Information Disclosure Statements filed on November 14, 2024 and February 26, 2025.
Claims 1-25 are pending. Claims 1, 15 and 21 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDSs) filed on November 14, 2024 and February 26, 2025. These IDSs have been considered.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0048], lines 10-11, “(if they are the same, ‘1’, and otherwise ‘0’)” should be --(if they are the same, ‘0’, and otherwise ‘1’)--.
Appropriate correction is required.
Claim Objections
Claim 17 is objected to because of the following informalities:
In claim 17, line 6, “the N+1 resistance memory cells” should be --the N+1 resistive memory cells--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-10, 14 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claims 9 and 19, each claim recites “of which a predicted power consumption for writing is low”. The term “low” is a relative term or term of degree, and the claims do not provide an objective standard for determining when a predicted power consumption is “low”. Therefore, person of ordinary skill in the art cannot determine with reasonable certainly which resistance value combination satisfies the claimed “low” limitation.
With respect to claim 10, the claim recites “of which the number of resistance changes required for the N+1 resistive memory cells is small”. The term “small” is a relative term or term of degree, and the claim does not provide an objective standard for determining when the number of resistance changes required is “small”. Therefore, person of ordinary skill in the art cannot determine with reasonable certainly which resistance value combination satisfies the claimed “small” limitation.
With respect to claim 14, the claim recites “as a bit value for the two adjacent resistive memory cells”. The phrase “the two adjacent resistive memory cells” lacks antecedent basis in claim 12, from which claim 14 directly depends. Claims 12 recites “the N+1 resistive memory cells”, but does not previously introduce a particular pair of “two adjacent resistive memory cells”. Claim 13 recites “two adjacent resistive memory cells”, but claim 14 does not depend on claim 13. Therefore, it is unclear which two cells among the N+1 resistive memory cells are referenced by “the two adjacent resistive memory cells”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-13, 15-18 and 20-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chih et al. (US 20140157088) in view of Kanai (US 20090319867).
Regarding independent claim 1, Chih et al. disclose a non-volatile memory device [see Fig. 2], the memory device comprising:
a memory array [Fig. 2: 200] comprising resistive memory cells [see Fig. 2 with respect to Fig. 1, para. 10-11] for each word line [see Fig. 2, an array 200, which includes cells arranged M rows (words) and N columns (bits), wherein individual cells are labeled Crow-column, para. 12].
However, Chih et al. are silent with respect to N+1 resistive memory cells expressing a bit sequence of N bits, wherein N is an integer greater than or equal to 2.
Kanai discloses N+1 resistive memory cells expressing a bit sequence of N bits [see Fig. 1, Kanai discloses the redundancy decoding circuit 2 is provided with the "n+1"-bit data "RDout" that has been read from the memory 7 and performs a redundancy decoding process to convert the data into an n-bit data "Dout" and outputs the converted data, para. 49. See Fig. 5, the redundancy decoding circuit 2 is provided with the 9-bit data x0 - x8 read from the memory 7 and performs the redundancy decoding process to output the 8-bit data d0 - d7, para. 53], wherein
N is an integer greater than or equal to 2 [the redundancy coding process and the redundancy decoding process, taking "n=8", para. 50].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Kanai to the teachings of Chih et al. such that implementing Kanai’s N to N+1 redundancy encoding in the selected word line of MRAM array as taught by Chih et al. by storing Kanai’s N+1 encoded bits in N+1 respective MRAM cells of Chih et al. along a selected word line row, thereby the modification would predictably obtain Kanai’s reliability benefits in Chih et al.’s resistive memory architecture.
Regarding claim 2, Chih et al. in combination with Kanai teach the limitations with respect to claim 1.
Furthermore, Kanai discloses wherein,
when a bit value of a bit position in the bit sequence is a first bit value, resistance values of adjacent memory elements corresponding to the bit position among the N+1 resistive memory cells are the same [the redundancy decoding process can be represented by a logical formula as shown in FIG. 6, and the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28 as shown in FIG. 7. The XOR element 21 is provided with the bits x0 and x1, with its output resulting in the bit d0, para. 54. When this value "001000010" is provided to the redundancy decoding circuit shown in FIG. 7, the output will be "01100011", para. 58] and,
when the bit value of the bit position is a second bit value, the resistance values of adjacent memory elements corresponding to the bit position among the N+1 resistive memory cells are different [the redundancy decoding process can be represented by a logical formula as shown in FIG. 6, and the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28 as shown in FIG. 7. The XOR element 21 is provided with the bits x0 and x1, with its output resulting in the bit d0, para. 54. When this value "001000010" is provided to the redundancy decoding circuit shown in FIG. 7, the output will be "01100011", para. 58].
Regarding claim 3, Chih et al. in combination with Kanai teach the limitations with respect to claim 1.
Furthermore, Kanai discloses further comprising:
a write encoder [Fig. 1: 1] configured to generate N+1 write signals individually indicating resistance values to be set for the N+1 resistive memory cells, based on a reference signal and N bit signals individually indicating bit values of the bit sequence [see Fig. 1, the redundancy coding circuit 1 is provided with an n-bit ("n" is an integer of "1" or more) data "Din" and performs a redundancy coding process to convert the data "Din" into an "n+1"-bit data "RDin" and output the converted data, para. 45. See Fig. 2, the redundancy coding circuit 1 is provided with an 8-bit data d0 - d7 and performs the redundancy coding process to output a 9-bit data x0 - x8, para. 50].
Regarding claim 4, Chih et al. in combination with Kanai teach the limitations with respect to claim 3.
Furthermore, Kanai discloses wherein the write encoder comprises a plurality of exclusive-OR (XOR) elements [see Fig. 4, the redundancy coding circuit 1 can be configured by a logical circuit having XOR elements 11 to 18, para. 51], wherein
an output of at least one XOR element of the plurality of XOR elements is connected to an input of another XOR element [see Fig. 4, the XOR element 12 is provided with the output of the XOR element 11 and the bit d1, with its output resulting in the bit x2. The same applies to the subsequent elements, that is, an XOR element "k(13≤k≤18)" is provided with the output of an XOR element "k-1" and a bit "dk-11", with its output resulting in a bit "xk-10", para. 52].
Regarding claim 5, Chih et al. in combination with Kanai teach the limitations with respect to claim 3.
Furthermore, Kanai discloses wherein the write encoder is configured to generate the N+1 write signals comprising outputs of a plurality of XOR elements and the reference signal [see Fig. 4, the XOR element 12 is provided with the output of the XOR element 11 and the bit d1, with its output resulting in the bit x2. The same applies to the subsequent elements, that is, an XOR element "k(13≤k≤18)" is provided with the output of an XOR element "k-1" and a bit "dk-11", with its output resulting in a bit "xk-10", para. 52].
Regarding claim 6, Chih et al. in combination with Kanai teach the limitations with respect to claim 3.
Furthermore, Kanai discloses wherein the write encoder comprises:
a first XOR element configured to receive a bit signal corresponding to a most significant bit (MSB) and the reference signal and generate a first XOR result between a bit value of the MSB and a bit value of the reference signal [see Fig. 4, the XOR element 11 is provided with "0" and the bit d0, with its output resulting in the bit x1, para. 51]; and
a second XOR element configured to receive a subsequent bit signal of the MSB and the first XOR result and generate a second XOR result between a bit value of the subsequent bit signal and the first XOR result [see Fig. 4, the XOR element 12 is provided with the output of the XOR element 11 and the bit d1, with its output resulting in the bit x2, para. 52].
Regarding claim 7, Chih et al. in combination with Kanai teach the limitations with respect to claim 1.
Furthermore, Kanai discloses wherein resistance values according to a result of encoding the bit sequence based on XOR are set for resistive memory cells arranged along a word line selected for writing [see Fig. 1, the redundancy coding process is performed by the redundancy coding circuit 1 to output the "n+1"-bit data "RDin" and then the data "RDin" is written on the address "A" of the memory 7, para. 66-67. It would have been obvious to write Kanai’s XOR generated N+1 bit sequence as N+1 low/high resistance states in corresponding Chih et al.’s MRAM cells along the selected word line row].
Regarding claim 8, Chih et al. in combination with Kanai teach the limitations with respect to claim 1.
Furthermore, Kanai discloses wherein the memory device is configured to set one resistance value combination among available resistance value combinations expressing the bit sequence for the N+1 resistive memory cells of a word line selected for writing [memory cells storing the 9-bit data x0 - x8 after the redundancy coding process, para. 60. For example, the memory cells storing the 9-bit data "001000010" after the redundancy coding process, para. 62].
Regarding claim 11, Chih et al. in combination with Kanai teach the limitations with respect to claim 8.
Furthermore, Chih et al. disclose wherein the memory device is configured to
change a resistance value of a resistive memory cell comprising a different resistance value from the resistance value combination selected from among the N+1 resistive memory cells of the word line selected for writing [Chih et al. disclose a method compares the actual bits read from memory to the expected bits which were attempted to be written to memory, thereby allowing identification of any erroneous bits in the word, para. 19. The method re-writes the expected bits to the bit locations where erroneous bits were identified. This occurs by performing a bit-wise write operation to correct the erroneous bits, para. 31], and
maintain a resistance value of a resistive memory cell comprising the same resistance value as the resistance value combination selected from among the N+1 resistive memory cells of the word line selected for writing [correctly written bits are left unperturbed, para. 15. The number of erroneous bits is re-written to the memory location without attempting to re-write correct bits stored in the memory location, para. 34].
Regarding claim 12, Chih et al. in combination with Kanai teach the limitations with respect to claim 1.
Furthermore, Kanai discloses further comprising:
a readout circuit [Fig. 1: 2] configured to generate bit read signals based on XOR results for resistance values set for the N+1 resistive memory cells arranged along a word line selected for reading [see Fig. 1, the redundancy decoding circuit 2 is provided with the "n+1"-bit data "RDout" that has been read from the memory 7, and performs a redundancy decoding process to convert the data into an n-bit data "Dout" and outputs the converted data, para. 49. See Fig. 7, the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28, para. 54].
Regarding claim 13, Chih et al. in combination with Kanai teach the limitations with respect to claim 12.
Furthermore, Kanai discloses wherein the readout circuit comprises an XOR element connected to two adjacent resistive memory cells among the N+1 resistive memory cells [see Fig. 7, the XOR element 21 is provided with the bits x0 and x1, with its output resulting in the bit d0. The same applies to the subsequent elements, that is, an XOR element "j(22≤j≤28)" is provided with bits "xj-21" and if "xj-20", with its output resulting in a bit "dj-21", para. 54-55].
Regarding independent claim 15, Chih et al. disclose operating method of a non-volatile memory device [see Fig. 2], the operating method comprising:
setting values expressing a bit sequence of bits for resistive memory cells [see Fig. 2 with respect to Fig. 1, para. 10-11] arranged in a word line selected [see Fig. 2, an array 200, which includes cells arranged M rows (words) and N columns (bits), wherein individual cells are labeled Crow-column, para. 12] for writing in a memory array [see Fig. 6, the MRAM device 600 includes a memory array 602 made up of a number of MRAM cells, typically arranged in rows and columns. Write circuitry 604 can write multi-bit words (or individual bits) into the array 602, para. 33]; and
outputting bit read signals from resistive memory cells arranged in a word line selected for reading in the memory array [see Fig. 6, read circuitry 606 can read the multi-bit words from the array 602, para. 33].
However, Chih et al. are silent with respect to setting resistance values expressing a bit sequence of N bits for N+1 resistive memory cells arranged in a word line selected for writing in a memory array; and
outputting N bit read signals from N+1 resistive memory cells arranged in a word line selected for reading in the memory array, wherein
N is an integer greater than or equal to 2.
Kanai discloses setting resistance values expressing a bit sequence of N bits for N+1 resistive memory cells for writing in a memory array [see Fig. 1, the redundancy coding circuit 1 is provided with an n-bit ("n" is an integer of "1" or more) data "Din" and performs a redundancy coding process to convert the data "Din" into an "n+1"-bit data "RDin", para. 45. The data "RDin" is written on the address "A" of the memory 7, para. 67]; and
outputting N bit read signals from N+1 resistive memory cells for reading in the memory array [see Fig. 1, the redundancy decoding circuit 2 is provided with the "n+1"-bit data "RDout" that has been read from the memory 7, and performs a redundancy decoding process to convert the data into an n-bit data "Dout" and outputs the converted data, para. 49], wherein
N is an integer greater than or equal to 2 [the redundancy coding process and the redundancy decoding process, taking "n=8", para. 50].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Kanai to the teachings of Chih et al. such that implementing Kanai’s N to N+1 redundancy encoding in the selected word line of MRAM array as taught by Chih et al. by storing Kanai’s N+1 encoded bits in N+1 respective MRAM cells of Chih et al. along a selected word line row, thereby the modification would predictably obtain Kanai’s reliability benefits in Chih et al.’s resistive memory architecture.
Regarding claim 16, Chih et al. in combination with Kanai teach the limitations with respect to claim 15.
Furthermore, Kanai discloses wherein the setting the resistance values comprises:
when a bit value of a bit position in the bit sequence is a first bit value, setting the same resistance value for adjacent memory elements corresponding to the bit position [the redundancy decoding process can be represented by a logical formula as shown in FIG. 6, and the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28 as shown in FIG. 7. The XOR element 21 is provided with the bits x0 and x1, with its output resulting in the bit d0, para. 54. When this value "001000010" is provided to the redundancy decoding circuit shown in FIG. 7, the output will be "01100011", para. 58] and,
when the bit value of the bit position is a second bit value, setting different resistance values for adjacent memory elements corresponding to the bit position [the redundancy decoding process can be represented by a logical formula as shown in FIG. 6, and the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28 as shown in FIG. 7. The XOR element 21 is provided with the bits x0 and x1, with its output resulting in the bit d0, para. 54. When this value "001000010" is provided to the redundancy decoding circuit shown in FIG. 7, the output will be "01100011", para. 58].
Regarding claim 17, Chih et al. in combination with Kanai teach the limitations with respect to claim 15.
Furthermore, Kanai discloses wherein the setting the resistance values comprises:
through a write encoder [Fig. 1: 1], generating N+1 write signals individually indicating resistance values to be set for the N+1 resistive memory cells, based on a reference signal and N bit signals individually indicating bit values of the bit sequence [see Fig. 1, the redundancy coding circuit 1 is provided with an n-bit ("n" is an integer of "1" or more) data "Din" and performs a redundancy coding process to convert the data "Din" into an "n+1"-bit data "RDin" and output the converted data, para. 45. See Fig. 2, the redundancy coding circuit 1 is provided with an 8-bit data d0 - d7 and performs the redundancy coding process to output a 9-bit data x0 - x8, para. 50]; and,
through a write driver [Fig. 1: 6], setting resistance values of the N+1 resistance memory cells by using the N+1 write signals [see Fig. 1, the selecting signal "Sel" is outputted from the write control circuit 6 so that the selector 4 can select the data "RDin". Further, the write control circuit 6 gives writing instructions to the memory 7, while altering the logical value from "0" to "1" for the write signal "MWrite" provided to the memory 7, by which the data "RDin" is written on the address "A" of the memory 7, para. 67].
Regarding claim 18, Chih et al. in combination with Kanai teach the limitations with respect to claim 15.
Furthermore, Kanai discloses wherein the setting the resistance values comprises:
writing one resistance value combination among available resistance value combinations expressing the bit sequence in the N+1 resistive memory cells of a word line selected for writing [memory cells storing the 9-bit data x0 - x8 after the redundancy coding process, para. 60. For example, the memory cells storing the 9-bit data "001000010" after the redundancy coding process, para. 62].
Regarding claim 20, Chih et al. in combination with Kanai teach the limitations with respect to claim 15.
Furthermore, Kanai discloses wherein the outputting comprises:
generating the N bit read signals based on exclusive-OR (XOR) results for resistance values set for the N+1 resistive memory cells arranged along a word line selected for reading [see Fig. 1, the redundancy decoding circuit 2 is provided with the "n+1"-bit data "RDout" that has been read from the memory 7, and performs a redundancy decoding process to convert the data into an n-bit data "Dout" and outputs the converted data, para. 49. See Fig. 7, the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28, para. 54].
Regarding independent claim 21, Chih et al. disclose a non-volatile memory device [see Fig. 2], the memory device comprising:
a memory array [Fig. 2: 200] comprising resistive memory cells [see Fig. 2 with respect to Fig. 1, para. 10-11] for each word line [see Fig. 2, an array 200, which includes cells arranged M rows (words) and N columns (bits), wherein individual cells are labeled Crow-column, para. 12] and two resistive memory cells that are adjacent to each other [see Fig. 2, two resistive memory cells C1,1 and C1,2]
However, Chih et al. are silent with respect to a method of encoding a bit value by using two resistive memory cells that are adjacent to each other, the memory encoding method comprising:
when the bit value is a first value, setting the same resistance value for the two resistive memory cells; and,
when the bit value is a second value that is different from the first value, setting different resistance values for the two resistive memory cells.
Kanai a method of encoding a bit value by using two resistive memory cells that are adjacent to each other, the memory encoding method comprising:
when the bit value is a first value, setting the same resistance value for the two resistive memory cells; and when the bit value is a second value that is different from the first value, setting different resistance values for the two resistive memory cells [the redundancy decoding process can be represented by a logical formula as shown in FIG. 6, and the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28 as shown in FIG. 7. The XOR element 21 is provided with the bits x0 and x1, with its output resulting in the bit d0, para. 54. When this value "001000010" is provided to the redundancy decoding circuit shown in FIG. 7, the output will be "01100011", para. 58].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Kanai to the teachings of Chih et al. such that implementing Kanai’s N to N+1 redundancy encoding in the selected word line of MRAM array as taught by Chih et al. by storing Kanai’s N+1 encoded bits in N+1 respective MRAM cells of Chih et al. along a selected word line row, thereby the modification would predictably obtain Kanai’s reliability benefits in Chih et al.’s resistive memory architecture.
Regarding claim 22, Chih et al. in combination with Kanai teach the limitations with respect to claim 21.
Furthermore, Kanai discloses wherein
the encoding is an exclusive OR (XOR), wherein the first value is 0 and the second value is 1 [see Fig. 7, the redundancy decoding circuit 2 can be configured by a logical circuit having XOR elements 21 to 28, para. 54. When this value "001000010" is provided to the redundancy decoding circuit shown in FIG. 7, the output will be "01100011", para. 58. When a value of the bit to be stored in the bad memory cell is "0" (or "1"), the data x0 - x8 is ensured to be written, para. 60].
Regarding claim 23, Chih et al. in combination with Kanai teach the limitations with respect to claim 21.
Furthermore, Kanai discloses wherein
the encoding is an exclusive negative OR (XNOR), wherein the first value is 1 and the second value is 0 [when a value of the bit to be stored in the bad memory cell is "1" (or "0"), a negation of the data x0 - x8 is ensured to be written, para. 60].
Regarding claim 24, Chih et al. in combination with Kanai teach the limitations with respect to claim 21.
Furthermore, Kanai discloses further comprising encoding N bit values by using N+1 resistive memory cells [see Fig. 5, the redundancy decoding circuit 2 is provided with the 9-bit data x0 - x8 read from the memory 7 and performs the redundancy decoding process to output the 8-bit data d0 - d7, para. 53].
Regarding claim 25, Chih et al. in combination with Kanai teach the limitations with respect to claim 24.
Furthermore, Chih et al. disclose wherein the N+1 resistive memory cells are connected to a shared word line, wherein N is an integer greater than or equal to 2 [see Fig. 2, an array 200, which includes cells arranged M rows (words) and N columns (bits), wherein individual cells are labeled Crow-column, para. 12].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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