Prosecution Insights
Last updated: April 19, 2026
Application No. 18/947,903

MODIFICATION METHOD AND MODIFICATION DEVICE

Non-Final OA §103
Filed
Nov 14, 2024
Examiner
CHAN, WEI
Art Unit
2844
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
89%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
418 granted / 565 resolved
+6.0% vs TC avg
Moderate +15% lift
Without
With
+14.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
25 currently pending
Career history
590
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
67.0%
+27.0% vs TC avg
§102
7.1%
-32.9% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 565 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2022-082818, filed on 05/20/2022. Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/14/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al [US 2013/0029494 A1] in view of Hayashi et al [US 2011/0223750 A1] In regards to claim 1. Sasaki discloses a method of modifying a film (Abstract) formed on a substrate, the method comprising: generating plasma by a microwave (Fig. 1, 34) in an interior of a processing container (Fig. 1, 1) in which a stage on which a substrate (Fig. 1, W) is placed is provided; and applying a DC voltage (Fig. 1, 15 to 14 to W) to the stage in the interior of the processing container (Fig. 1, 1) in which the plasma is generated by the generating the plasma (Paragraph [0048]), and Sasaki does not specify periodically applying a DC voltage; irradiating the substrate with electrons in the plasma. Hayashi discloses periodically applying a DC voltage (Fig. 2, 17a & Paragraph [0032]); irradiating the substrate (Fig. 1, W and 12) with electrons (Fig. 4, 130) in the plasma (Fig. 1, 110). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Sasaki with periodically applying a DC voltage; irradiating the substrate with electrons in the plasma for purpose of improve the positive charge-up occurring at the bottom portion of the recess pattern such as a groove or a hole by etching with use of positive ions can be alleviated for purpose of Hayashi (Paragraph [0042]). In regards to claim 2. Sasaki in view of Hayashi discloses the method of Claim 1, wherein the irradiating the substrate (Hayashi Fig. 1, W and 12) includes periodically applying DC voltages of two different voltage levels (Hayashi: Paragraph [0034]). In regards to claim 3. Sasaki in view of Hayashi discloses the method of Claim 1, wherein the irradiating the substrate (Hayashi Fig. 1, W and 12) includes periodically applying a negative DC voltage (Hayashi: Paragraph [0034]). In regards to claim 7. Sasaki in view of Hayashi discloses the method of Claim 1, wherein in the generating the plasma, power of the microwave for generating the plasma in the interior of the processing container is 175 to 1500 [W] (SasaKi Paragraph [0053]), an internal pressure of the processing container is 2 to 100 [Pa] (SasaKi Paragraph [0053]), and a gas species of a processing gas supplied to the interior of the processing container is He and N2, (Hayashi: Paragraph [0030]) and wherein in the irradiating the substrate (Hayashi Fig. 1, W), the DC voltage which is periodically applied to the stage is -400[V] or less (Hayashi: Paragraph [0034]). In regards to claim 9. Sasaki in view of Hayashi discloses a modification device comprising: a processing container (Fig. 1, 1) including a stage (Fig. 1, 19) provided in an interior of the processing container (Fig. 1, 1), wherein a substrate (Fig. 1, W) on which a film (Abstract) to be modified is formed is placed on the stage (Fig. 1, 19); a generator (Fig. 1, 34) configured to generate plasma (Paragraph [0059]) by a microwave in the interior of the processing container (Fig. 1, 1); a voltage applier (Fig. 1, 15) configured to apply a DC voltage to the stage (Fig. 1, 10 and 14); and Sasaki does not specify a controller configured to control the voltage applier to periodically apply a DC voltage to the stage while controlling the generator to generate the plasma in the interior of the processing container. Hayashi discloses a controller (Fig. 1, 19) configured to control the voltage applier to periodically apply a DC voltage (Fig. 2, 17a & Paragraph [0032]) to the stage (Fig. 1, 12) while controlling the generator to generate the plasma (Fig. 1, 110) in the interior of the processing container (Fig. 1, 11). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Sasaki with a controller configured to control the voltage applier to periodically apply a DC voltage to the stage while controlling the generator to generate the plasma in the interior of the processing container for purpose of improve the positive charge-up occurring at the bottom portion of the recess pattern such as a groove or a hole by etching with use of positive ions can be alleviated for purpose of Hayashi (Paragraph [0042]). Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al [US 2013/0029494 A1] in view of Hayashit et al [US 2011/0223750 A1] and further in view of Klyosue et al [US 2024/0047179 A1]. In regards to claim 4. Sasaki in view of Hayashi discloses the method of Claim 1, and includes an electrode (Hayashi: Fig. 3 & Paragraph [0013]) provided in the stage (Hayashi: Fig. 1, 12), the DC voltage being applied to the electrode (Hayashi: Fig. 3 & Paragraph [0013]). Sasaki in view of Hayashi does not specify wherein the stage is formed of a dielectric material Klysosue discloses wherein the stage is formed of a dielectric material (Paragraph [0034]) It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Sasaki with the stage is formed of a dielectric material for purpose of generated electrostatic force holds the wafer on dielectric film by Klyosue (Paragraph [0033-34]). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al [US 2013/0029494 A1] in view of Hayashit et al [US 2011/0223750 A1] and further in view of Ohse et al [US 2010/0243607 A1] In regards to claim 5. Sasaki in view of Hayashi discloses the method of Claim 1, Sasaki in view of Hayashi does not specify wherein a frequency when the DC voltage is applied is 200 kHz or less, and a proportion of a period during which the DC voltage is in an ON state in each cycle is 80% or more. Ohse discloses wherein a frequency when the DC voltage is applied is 200 kHz or less (Paragraph [0029]), and a proportion of a period during which the DC voltage is in an ON state in each cycle is 80% or more (Paragraph [0066]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Sasaki in view of Hayashi with wherein a frequency when the DC voltage is applied is 200 kHz or less, and a proportion of a period during which the DC voltage is in an ON state in each cycle is 80% or more for purpose of improving efficiently generate plasma by exciting process gas components asd disclosed by Ohse (Paragraph [0023]). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al [US 2013/0029494 A1] in view of Hayashit et al [US 2011/0223750 A1] and further in view of Sangle et al [US 2022/0285129 A1] In regards to claim 6. Sasaki in view of Hayashi discloses the method of Claim 1, Sasaki in view of Hayashi does not specify wherein a period during which the DC voltage is in an ON state in each cycle during which the DC voltage is periodically applied is set to 4 to 10 μ[sec]. Sangle discloses wherein a period during which the DC voltage is in an ON state in each cycle during which the DC voltage is periodically applied is set to 4 to 10 μ[sec] (Paragraph [0028-33]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Sasaki in view of Hayashi with wherein a period during which the DC voltage is in an ON state in each cycle during which the DC voltage is periodically applied is set to 4 to 10 μ[sec] for purpose of independently controlled depending upon the impedance of the target and chamber as disclosed by Sangle (Paragraph [0028]). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al [US 2013/0029494 A1] in view of Hayashit et al [US 2011/0223750 A1] and further in view of Nozawa et al [US 2021/0043447 A1] In regards to claim 8. Sasaki in view of Hayashi the method of Claim 1, wherein the processing container includes an irradiator provided on a ceiling wall portion (Hayashi: Fig. 1, 11) of the processing container to irradiate with the microwave (Sasaki Fig. 1, 34), and Sasaki in view of Hayashi does not specify wherein a gap between the ceiling wall portion and the stage is 100 to 200 mm Nozawa discloses wherein a gap between the ceiling wall portion and the stage is 100 to 200 mm (Paragraph [0082 & 0084]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Sasaki in view of Hayashi with wherein a gap between the ceiling wall portion and the stage is 100 to 200 mm for purpose of uniformity of film thickness Unify of the organic film formed on each wafer W was ±10% or more as disclosed by Nozawa (Paragraph [0084]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI (VICTOR) CHAN whose telephone number is (571)272-5177. The examiner can normally be reached M-F 9:00am to 6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. WEI (VICTOR) CHAN Primary Examiner Art Unit 2844 /WEI (VICTOR) Y CHAN/Primary Examiner, Art Unit 2844
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Prosecution Timeline

Nov 14, 2024
Application Filed
Jan 28, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
89%
With Interview (+14.7%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 565 resolved cases by this examiner. Grant probability derived from career allow rate.

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