DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-11, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPub 2023/0154411) in view of Kim et al. (US PGPub 2023/0360427).
Regarding claim 1, Lee discloses a display device (fig. 1, display device 1), comprising:
([0073], “output the reset control signal RCS to the reset driver 260 through a reset control line”), a sensing line ([0008], “a display device may comprise a display panel which comprises scan lines, sensing lines, pixels electrically connected to each of the scan lines, and photo sensors electrically connected to each of the scan lines and the sensing lines”), and an emission control line ([0073], “output the emission control signal ECS to the emission driver 250 through an emission control line”);
an emission driving circuit (fig. 2, emission driver 250) which supplies an emission control signal to the emission control line ([0073], “output the emission control signal ECS to the emission driver 250 through an emission control line”);
a reset circuit (fig. 2, reset driver 260) which supplies a reset control signal to the reset control line ([0073], “output the reset control signal RCS to the reset driver 260 through a reset control line”);
a pixel (fig. 2, pixel PX), wherein the pixels includes a pixel circuit connected to the emission control line (fig. 2, EML connected to PX), and a light emitting element ([0059], “Each pixel PX may include a light emitting element EL (refer to FIG. 5)”) which receives a current from the pixel circuit in response to the emission control signal of a turn-on level ([0099], “The light emitting element EL emits light according to the driving current Isd. The amount of light emitted from the light emitting element EL may be proportional to the driving current Isd”);
a photo sensor (fig. 2, photo sensor PS), wherein the photo sensor includes a photo sensor driving circuit connected to the reset control line and the sensing line ([0110], “each of the photo sensors PS may include a first node N1 between the first sensing transistor LT1, the third sensing transistor LT3 and the photoelectric converter PD and a second node N2 between the second driving voltage line VSSL and the photoelectric converter PD. The first sensing transistor LT1 may be a driving transistor, and the second and third sensing transistors LT2 and LT3 may be transistors serving as switch elements that are turned on or off according to a reset signal and a scan signal transmitted to their respective gate electrodes”), and a light receiving element which receives a reset voltage in response to the reset control signal of a turn-on level ([0110] and fig. 5, “Each of the photo sensors PS may include sensing transistors and a photoelectric converter PD. The sensing transistors may include first through third sensing transistors LT1 through LT3. Each of the photo sensors PS may include a first node N1 between the first sensing transistor LT1, the third sensing transistor LT3 and the photoelectric converter PD and a second node N2 between the second driving voltage line VSSL and the photoelectric converter PD. The first sensing transistor LT1 may be a driving transistor, and the second and third sensing transistors LT2 and LT3 may be transistors serving as switch elements that are turned on or off according to a reset signal and a scan signal transmitted to their respective gate electrodes”); and
a readout circuit (figs 2 and 9, readout circuit 300) which differentially amplifies and outputs voltages of the sensing line respectively sensed in response to a first sampling signal and a second sampling signal ([0081], “The readout circuit 300 may generate fingerprint sensing data according to the magnitude of a current sensed by each photo sensor PS and transmit the fingerprint sensing data to the processor 100” and fig. 9 where the readout circuit 300 includes amplifier 310 and sample/hold circuit 320),
wherein a length of a reset period, during which the reset control signal of the turn-on level is inputted, is equal to or greater than twice a length of a sensing period which is a cycle on which the first sampling signal of a turn-on level is sequentially inputted (where in fig. 7, RST is high for 6 sections and in fig. 10, st4, the SW2 is turned on for 4 sections, where in fig. 10, 19 sections make up 4H and in fig. 7, only 4 sections make up 4H therefore 1H in figure 7 is more than double the length of 1H in fig. 10. also see [0176], “During the fourth readout period st4, the second switch SW2 is turned on. Accordingly, the output terminal ot1 of the first operational amplifier OP1 may be electrically connected to the second sampling capacitor Csh2. Since the output voltage Vout of the first operational amplifier OP1 corresponds to the sensing signal voltage Vsignal in the fourth readout period st4, the sensing signal voltage Vsignal may be stored in the second sampling capacitor Csh2. A voltage of “Vin+Vnoise+Vsignal” may be stored in the second sampling capacitor Csh2”).
In a similar field of endeavor of display devices, Kim discloses a substrate ([0019], a substrate) on which a plurality of lines, a pixel and a photosensor are disposed ([0018]-[0019] and fig. 6, “The reset control line may be connected in common to the first photo sensor and the second photo sensor. A circuit layer including the first and second transistors and the first, second, and third sensor transistors may be disposed on a substrate, and the light emitting element and the light receiving element may be disposed on the circuit layer”).
In view of the teachings of Lee and Kim, it would have been obvious to one of ordinary skill in the art to include the substrate of Kim within the structure of Lee, for the purpose of providing a known type of structure which improves structure support to the various layers of a device.
Regarding claim 2, the combination of Lee and Kim further discloses wherein the pixel circuit comprises:
a driving transistor (Lee: fig. 5, transistor T1) connected between a second node and a third node, and including a gate electrode connected to a first node (Lee: fig. 5 and [0096]-[0097], “The first transistor T1 may be a driving transistor…The first transistor T1 may include a gate electrode, a first electrode, and a second electrode”);
a first emission control transistor (Lee: fig. 5, transistor T5) connected between the second node and a first power line (Lee: fig. 5, transistor T5 connected to VDDL and connected to T1), and including a gate electrode connected to the emission control line (Lee: fig. 5, EML); and
a second emission control transistor (Lee: fig. 5, transistor T6) connected between the third node and the light emitting element (Lee: fig. 5, transistor T6 connected to T1 and element EL), and including a gate electrode connected to the emission control line (Lee: fig. 5, EML).
Regarding claim 3, the combination of Lee and Kim further discloses wherein the pixel circuit further comprises a switching transistor (Lee: fig. 5, transistor T2) connected between a data line and the second node (Lee: fig. 5, transistor T2 connected to DL and node between transistor T5 and T1), and including a gate electrode connected to a first scan line (Lee: fig. 5, GWL1),
wherein the photo sensor driving circuit comprises:
a first sensor transistor (Lee: fig. 5, transistor LT1) connected to a fifth power line to which a power voltage is applied (Lee: fig. 5, Vint2), and including a gate electrode connected to the light receiving-element (Lee: fig. 5, node N1);
a second sensor transistor (Lee: fig. 5, transistor LT2) connected between the first sensor transistor and the sensing line (Lee: fig. 5, transistor LT2 connected to LT1 and connected to fingerprint sensing lines FRL), and including a gate electrode connected to the first scan line (Lee: fig. 5, GWL1); and
a third sensor transistor (Lee: fig. 5, transistor LT3) connected between the light receiving element and a fourth power line to which the reset voltage is applied (Lee: fig. 5, transistor LT3 connected to Vrst and node N1), and including a gate electrode connected to the reset control line (Lee: fig. 5, reset line RSTL).
Regarding claim 4, the combination of Lee and Kim further discloses wherein the pixel circuit further comprises:
a compensation transistor (Lee: fig. 5, transistor T3) connected between the first node and the third node (Lee: fig. 5, transistor T3 connected to T1), and including a gate electrode connected to a fourth scan line (Lee: fig. 5, GCL);
a first initialization transistor (Lee: fig. 5, transistor T4) connected between the first node and a second power line (Lee: fig. 5, transistor T4 connected to gate of T1 and Vint2), and including a gate electrode connected to a second scan line (Lee: fig. 5, GIL);
a second initialization transistor (Lee: fig. 5, transistor T7) connected between the light emitting element and a third power line (Lee: fig. 5, transistor T7 connected to element EL and Vint1), and including a gate electrode connected to a third scan line (Lee: fig. 5, GWL2); and
a storage capacitor (Lee: fig. 5, capacitor Cst) including a first side electrode connected to the first node (Lee: fig. 5, capacitor Cst connected to gate of T1), and a second side electrode connected to the first power line (Lee: fig. 5, VDDL).
Regarding claim 5, the combination of Lee and Kim further discloses wherein a length of a period in which the emission driving circuit supplies the emission control signal of a turn-off level to the emission control line is greater than the length of the reset period (Lee: figs. 6 and 7; EM at a Voff level shown in fig. 6 for longer than RSP shown in fig. 7).
Regarding claim 6, the combination of Lee and Kim further discloses
wherein the readout circuit includes an integrator (Lee: fig. 9, amplifier 310) and a sample-and-hold circuit (Lee: fig. 9, sample/hold circuit 320), and
wherein the integrator comprises:
an operational amplifier (Lee: fig. 9, first operational amplifier OP1) including a first input terminal connected to the sensing line (Lee: fig. 9, input of OP1 connected to FRL), and a second input terminal to which a constant voltage is applied (Lee: fig. 9, input of OP1 connected to Vin);
a feedback capacitor (Lee: fig. 9, feedback capacitor Cfb) connected between the first input terminal of the operational amplifier and an output terminal of the operational amplifier (Lee: fig. 9, capacitor Cfb connected to input and output terminals of OP1); and
a first switching element (Lee: fig. 9, switch SWR0) connected between the first input terminal of the operational amplifier and the output terminal of the operational amplifier (Lee: fig. 9, switch SWR0 connected between input and output terminals of OP1),
wherein the sample-and-hold circuit comprises:
a second switching element (Lee: fig. 9, switch SW1) which switches electrical connection between the output terminal of the operational amplifier and a first sampling capacitor in response to the second sampling signal (Lee: fig. 9, switch SW1 connected to Vout and capacitor Csh1);
a third switching element (Lee: fig. 9, switch SW2) which switches electrical connection between the output terminal of the operational amplifier and a second sampling capacitor in response to the first sampling signal (Lee: fig. 9, switch SW2 connected to Vout and capacitor Csh2); and
a differential amplifier (Kim: [0203], “a differential amplifier”) including a first input terminal which receives a voltage corresponding to a voltage stored in the first sampling capacitor, and a second input terminal which receives a voltage corresponding to a voltage stored in the second sampling capacitor (Kim: [0203], “For example, the analog-digital converter ADC may be implemented as a single analog-digital converter, and a differential amplifier configured to differentiate the first sampling signal V_SHR and the second sampling signal V_SHS and output the differentiated value may be provided between the correlated double sampling circuit CDS and the analog-digital converter ADC”).
Regarding claim 7, the combination of Lee and Kim further discloses
wherein the first switching element electrically connects the first input terminal of the operational amplifier to the output terminal of the operational amplifier in response to an integrator reset signal (Lee: fig. 10 and [0173], “During the first readout period st1, the capacitor reset switch SWRO is turned on. Accordingly, both ends of the feedback capacitor Cfb may be electrically connected to reset the feedback capacitor Cfb. In the first readout period st1, the output voltage Vout of the first operational amplifier OP1 may be substantially the same as the initial voltage Vin of the first input terminal (−)”), and
wherein the integrator reset signal of a turn-on level, the second sampling signal of a turn-on level, and the first sampling signal of a turn-on level are sequentially inputted (Lee: fig. 10 and [0172], “The fingerprint readout period ROP may be divided into a first readout period st1 in which the feedback capacitor Cfb is reset, a second readout period st2 in which a voltage is stored in the first sampling capacitor Csh1, a third readout period st3 in which a photocurrent generated in response to light exposure is output to the readout circuit 300, and a fourth readout period st4 in which a sensing voltage according to the photocurrent is stored in the second sampling capacitor Csh2”).
Regarding claim 9, the combination of Lee and Kim further discloses wherein the length of the sensing period is equal to or greater than two horizontal periods (Lee: fig. 7, fingerprint readout period ROP shown as longer than 2H).
Regarding claim 10, the combination of Lee and Kim further discloses
wherein the pixel and the photo sensor are positioned in an area on the substrate (Kim: [0019], “A circuit layer including the first and second transistors and the first, second, and third sensor transistors may be disposed on a substrate, and the light emitting element and the light receiving element may be disposed on the circuit layer”), and
wherein the reset control signal is inputted within a period during which the emission control signal of a turn-off level is supplied to the pixel (Lee: figs. 6 and 7, in fig. 6 EM signal is high during time periods between t5 during which GW1 and GW2 go low while in fig. 7 RSP occurs just after GW1 and GW2 go low, where fig. 6 illustrates FOM1 and fig. 7 illustrates a plurality of FOM1s).
Regarding claim 11, the combination of Lee and Kim further discloses wherein a length of a period during which the first sampling signal is at a turn-on level is greater than a length of a period during which the second sampling signal is at a turn-on level (Kim: fig. 13, SHS signal is high for a longer length than SHR signal).
Regarding claim 21, the combination of Lee and Kim further discloses an electronic device (Lee: fig. 1, display device 1) comprising: a processor to receive a data ([0066], “The processor 100 supplies an image signal RGB and control signals supplied from the outside to a timing controller 210”) ; and a display device to output the data (Lee: [0071], “The display driving circuit 200 may generate signals and voltages for driving the pixels PX and the photo sensors PS of the display panel 10”), wherein the display device is within the scope of claim 1 and is therefore interpreted and rejected based on similar reasoning.
Regarding claim 22, the combination of Lee and Kim further discloses wherein the processor includes at least one of a central processing unit, an application processor, a graphic processing unit, a neural processing unit, an image signal processor, a sensor hub processor, and a communication processor (Lee: [0066], “The processor 100 may further include a graphics processing unit (GPU) that provides graphics for the image signal RGB received from the outside”).
Regarding claim 23, the combination of Lee and Kim further discloses wherein the electronic device includes a wearable device (Kim: [0057], “The display device 1000 may be a flat display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, or a rollable display device. Furthermore, the display device may be applied to a transparent display device, a head-mounted display device, a wearable display device, or the like”).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Kim further in view of Chun et al. (US PGPub 2025/0252903).
Regarding claim 8, the combination of Lee and Kim further discloses wherein the readout circuit further comprises:
a (Kim: [0203], “The analog-digital converter ADC may differentiate the first sampling signal V_SHR and the second sampling signal V_SHS that are provided from the correlated double sampling circuit CDS, and may convert the differentiated signals to a digital sensing value VOUT and output the digital sensing value VOUT. For example, the analog-digital converter ADC may be implemented as a differential analog-digital converter. The present disclosure is not limited thereto. For example, the analog-digital converter ADC may be implemented as a single analog-digital converter, and a differential amplifier configured to differentiate the first sampling signal V_SHR and the second sampling signal V_SHS and output the differentiated value may be provided between the correlated double sampling circuit CDS and the analog-digital converter ADC”); and
an analog-to-digital converter (Lee: fig. 9, analog-digital (AD) converter 330) which converts a sensing voltage inputted thereto (Lee: [0165], “an analog-digital (AD) converter 330 converting an analog signal corresponding to the output voltage into digital data”).
While the combination of Kim and Lee teaches a differential amplifier and an analog-to-digital converter, it has been known to include a switch before an analog-to-digital converter. In a similar field of endeavor of display devices, Chun discloses a fourth switching element ([0085]-[0086] and fig. 3, “The analog-digital converter ADC may differentiate the first sampling signal V_SHR and the second sampling signal V_SHS that are provided from the correlated double sampling circuit CDS, and may convert the differentiated signals to a digital sensing value VOUT and output the digital sensing value VOUT. For example, the analog-digital converter ADC may be implemented as a differential analog-digital converter. The present disclosure is not limited thereto. For example, the analog-digital converter ADC may be implemented as a single analog-digital converter, and a differential amplifier configured to differentiate the first sampling signal V_SHR and the second sampling signal V_SHS and output the differentiated value may be provided between the correlated double sampling circuit CDS and the analog-digital converter ADC…Meanwhile, a sample and hold circuit, an amplifier, an integrator, and the like may be added between the fourth switch transistor M4 and the ADC); and
an analog-to-digital converter which converts a sensing voltage inputted thereto through the fourth switching element to a digital value and outputs the digital value ([0086] and fig. 3, “The ADC converts the sensing voltage Vsen into the digital data and outputs sensing data Dsen”).
In view of the teachings of Kim, Lee and Chun, it would have been obvious to one of ordinary skill in the art to include the fourth switch of Chun within the system of Kim and Lee, for the purpose of providing a switch before an analog-to-digital converter which has the known advantage of controlling when data is input to the analog-to-digital converter.
Response to Arguments
Applicant's arguments filed 02/26/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicants argue “However, Applicant respectfully notes that Lee does not disclose a length of a reset period, during which the reset control signal of the turn-on level is inputted, is equal to or greater than twice a length of a sensing period which is a cycle on which the first sampling signal of a turn-on level is sequentially inputted, as in claim 1” (page 17, paragraph 3), however Examiner respectfully disagrees.
Examiner maintains that Lee teaches that for reset period: in fig. 7, RST is high for 6 sections or horizontal units of time, and for scale, Fig. 7 shows 4 sections or horizontal units of time for 4H. For sensing period: in Fig. 10, st4, the SW2 is turned on for 4 sections or horizontal units of time, and for scale, Fig. 10 shows 19 sections or horizontal units of time for 4H. Therefore, the ratio of units of time scale between Fig. 7 and Fig. 10 is 4 to 19, or 4/19= 0.21. Adjusting for scale of 0.21, comparatively the reset period RST (6 units of time) would be more than twice the length of the sensing period st4 (4 units of time x .021=0.84 units of time).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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