Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 9/4/2026. The changes and remarks disclosed therein have been considered. Claim 9 has been cancelled by the amendment. Claims 1-4, 8, and 11-19 have been amended. New Claim 21 has been added. Therefore, claims 1-8, 10-21 remain pending in the application.
Response To Arguments
The Applicant' arguments (REMARKS, filed 09/04/2026) have been fully considered. The Examiner agrees with the Applicant (REMARKS, page 7, Drawings Objections, claim rejection under 35 USC § 112) that amendments made by the Applicant removes grounds for objections to drawings and claim rejection under 35 USC § 112.
In regard to amendment of the independent claims 1, 11, and 17, Applicant arguments have been fully considered but they are not persuasive. Applicant has amended the independent claims with additional limitation(s): "applying a programming pulse to the target memory cell in a write operation; and after the programming pulse is applied, conducting the read-verification operation to check a state of the target memory cell," The Applicant argues that the prior arts of record do not specifically teach this limitation. However, the independent claim 1 is now rejected as being unpatentable over Seo in view of Chen. The Examiner respectfully submits that Seo teaches all features recited in the independent claim 1, except the newly added limitation. However, Chen teaches a programming operation including applying a program voltage to a selected word lines and thereafter performing a sensing/verify process The Examiner respectfully submits that Seo in view of Chen teach all limitations recited in claim 1 including the newly added limitation. The independent claims 11 and 17 are now rejected under 35 U.S.C. 103(a) as being unpatentable over Seo in view of Chen. The Examiner respectfully submits that combination of Seo and Chen references disclose all limitations recited in the independent claims 11 and 17.
Accordingly, the Examiner maintains the position previously set forth.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-8, 10-15, 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over SEO PG PUB 20210027848 (hereinafter SEO), in view of Chen PG PUB 20190074062 (hereinafter Chen).
Regarding independent claim 1, Seo teaches a method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device (figures 3-11 of Seo, [0009] of Seo), comprising:
applying, on an unselected top select gate (Unsel DSL(DSL1) in figure 8, 11 of Seo) of an unselected memory string, a first prepare voltage (V2 in figures 8, 11 of Seo) during a first time period (t1 in figures 8, 11 of Seo) and an off voltage (ground in figure 8, 11 of Seo) during a second time period (t2 in figure 8, or time period after T1 in figure 11 of Seo, [0075] of Seo, “…the drain select line voltage (for example, V.sub.DSL1) of the unselected memory string … may be set to a voltage to turn on the drain select transistor DST…during a first time period…”);
applying, on a selected word line (Sel WL in figures 8, 11 of Seo) associated with the target memory cell, a first voltage (ground in figures 8, 11 of Seo) to switch off the target memory cell during the first time period (t1 in figures 8, 11 of Seo) and a read voltage (Vread in figure 8 of Seo, or V5 in figure 11 of Seo, under BRI, a voltage applied to the selected WL during a read operation to facilitate reading can qualify as a “read voltage”) during the second time period (t2 in figure 8 of Seo, or time period after t1 in figure 11 of Seo); and
applying, on an unselected word line (Unsel WLs in figure 8 of Seo), a pass voltage (Vpass in figure 8 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8, or time period after t1 in figure 11 of Seo), wherein the first time period (t1 in figure 8) is prior to the second time period (t2 in figure 8 of Seo).
But Seo does not expressly teach applying a programming pulse to the target memory cell in a write operation; and after the programming pulse is applied, conducting the read-verification operation to check a state of the target memory cell.
Chen teaches a programming operation including applying a program voltage to a selected word lines and thereafter performing a sensing/verify process (figure 13C, figure 14). In particular, Chen teaches in [0163] that step 1333 “applies the program voltage to a selected word line” and in [0164] “Step 1335 includes performing a sensing process, e.g., one or more verify tests, for the selected memory cells”. Chen further explains that the verify test determines whether the selected memory cells are in a conductive or non-conductive state. Thus Chen teaches performing the verification after application of the programming pulse/voltage in the programming loop.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to incorporate Chen conventional program-and-verify sequence into Seo’s memory operation so that, applying a programming pulse to the target memory cell in a write operation; and after the programming pulse is applied, conducting the read-verification operation to check a state of the target memory cell (figure 13C and 14 of Chen), because verification following programming determines whether the selective memory cell has reached the intended programmed state and whether further programming is required.
Regarding claim 2, the combination of Seo and Chen teaches the method of claim 1, further comprising:
applying, on a selected top select gate (Sel DSL in figure 8 of Seo) of a selected memory string including the target memory cell, a top select gate voltage (V1 in figure 8 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8 of Seo) to switch on a top select transistor coupled to the selected top select gate; and
applying, on a lower select gate (SSL0 in figure 8 of Seo) of the memory device, a lower select gate voltage (V1 in figure 8 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8 of Seo) to switch on a lower select transistor (SST in figure 4 of Seo) coupled to the lower select gate (SSL0 in figures 4, 8 of Seo).
Regarding claim 3, the combination of Seo and Chen teaches the method of claim 1, further comprising ramping up the first prepare voltage (V2 in figure 8 of Seo) on the unselected top select gate (Unsel DSL(DSL1) of Seo) before ramping up the pass voltage (Vpass in figure 8 of Seo) on the unselected word line (Unsel WLs in figure 8 of Seo).
Regarding claim 4, the combination of Seo and Chen teaches the method of claim 3, wherein the unselected word line (Unsel WLs in figure 8 of Seo) reaches the pass voltage (Vpass in figure 8 of Seo) after the unselected top select gate (Unsel DSL(DSL1) of Seo) at the first prepare voltage (V2 in figure 8 of Seo).
Regarding claim 5, the combination of Seo and Chen teaches the method of claim 2, further comprising ramping up the top select gate voltage (V1 in figure 8 of Seo) on the selected top select gate (Sel DSL in figure 8 of Seo) and the lower select gate voltage (V1 in figure 8 of Seo) on the lower select gate (SSL0 in figure 8 of Seo) before ramping up the pass voltage (Vpass in figure 8 of Seo) on the unselected word line (Unsel WLs in figure 8 of Seo).
Regarding claim 6, the combination of Seo and Chen teaches the method of claim 5, wherein the unselected word line (Unsel WLs in figure 8 of Seo) reaches the pass voltage (Vpass in figure 8 of Seo) after the selected top select gate (Sel DSL in figure 8 of Seo) at the selected top select gate voltage (V1 in figure 8 of Seo) and the lower select gate (SSL0 in figure 8 of Seo) at the lower select gate voltage (V1 in figure 8 of Seo).
Regarding claim 7, the combination of Seo and Chen teaches the method of claim 1, further comprising: applying the first prepare voltage (V2 in figure 8, or V2 in figure 11 of Seo) on the unselected top select gate (Unsel DSL(DSL1) of Seo) during the first time period (t1 in figure 8 of Seo) to switch on an unselected top select transistor coupled to the unselected top select gate; and applying the off voltage (ground in figure 8 of Seo) on the unselected top select gate during the second time period (t2 in figure 8 or time period after t1 in figure 11 of Seo, [0075] of Seo, “…the drain select line voltage (for example, V.sub.DSL1) of the unselected memory string … may be set to a voltage to turn on the drain select transistor DST…during a first time period…” and applying the off voltage (ground in figure 8 of Seo) on the unselected top select gate during the second time period) to switch off the unselected top select transistor.
Regarding claim 8, the combination of Seo and Chen teaches the method of claim 7, further comprising: applying the read voltage (V5 in figure 11 of Seo) on the selected word line (Sel WL in figure 8 of Seo) before the unselected top select transistor is switched off.
Regarding claim 10, the combination of Seo and Chen teaches the method of claim 1, wherein applying the read voltage comprises applying multiple read voltages on the selected word line during the second time period (Chen teaches applying multiple read voltages to the selected word line during a sensing /verify process, for example, Chen teaches in [0151] “A sensing process can involve applying one or more voltages to a selected word line while sensing whether the associated memory cells are in a conductive or non-conductive state”, and in figure 14 and [0143] that “Read voltages VrA, VrB, VrC, VrD, VrE, VrF and VrG can be used for reading the states of the cells in a read operation”).
Regarding independent claim 11, the combination of Seo and Chen teaches a method for conducting a read-verification operation (figure 13C, 14 of Chen) on a target memory cell in a three-dimensional (3D) memory device (figure 3 of Seo, figure 5 of Chen), comprising:
applying a programming pulse to the target memory cell in a write operation (figure 13C, 14 of Chen); and
after the programming pulse is applied, conducting the read-verification operation to check a state of the target memory cell (figure 13C, 14 of Chen), the read-verification operation comprising:
applying, on a selected word line (Sel WL in figures 8, 11 of Seo) associated with the target memory cell, a first voltage (ground in figure 8 of Seo, or V5 in figure 11 of Seo) during a first time period (t1 in figures 8, 11 of Seo) and a read voltage (Vread in figure 8 of Seo, or Vread in figure 11 of Seo, under BRI, a voltage applied to the selected WL during a read operation to facilitate reading can qualify as a “read voltage”) during a second time period (t2 in figure 8 of Seo, or time period after t1 in figure 11 of Seo), wherein the first time period is prior to the second time period (t2 in figure 8 of Seo, or time period after t1 in figure 11 of Seo) and the first voltage comprises a first prepare voltage (ground in figure 8 of Seo, or V5 in figure 11 of Seo);
applying, on an unselected word line (Unsel WLs in figure 8, 11 of Seo), a pass voltage (Vpass in figure 8, 11 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8, or time period after t1 in figure 11 of Seo) to switch on memory cells coupled to the unselected word line; and
applying, on a selected top select gate (Sel DSL in figure 8 of Seo) of a selected memory string containing including the target memory cell, a top select gate voltage (V1 in figures 8, 11 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8 of Seo) to switch on a top select transistor coupled to the selected top select gate.
Regarding claim 12, the combination of Seo and Chen teaches the method of claim 11, further comprising applying the first prepare voltage (V5 in figure 11 of Seo) on the selected word line during the first time period to switch on memory cells coupled to the selected word line ([0104] of Seo, “…A fifth voltage V5 may be applied to the selected word line Sel WL during a predetermined time period. For an embodiment, the fifth voltage V5 may have the same potential level as the pass voltage Vpass...”)
Regarding claim 13, the combination of Seo and Chen teaches the method of claim 11, further comprising applying an off voltage (ground in figure 8 of Seo) on the selected word line during the first time period to switch off memory cells coupled to the selected word line.
Regarding claim 14, the combination of Seo and Chen teaches the method of claim 11, further comprising applying, on an unselected top select gate (Unsel SSL(SSL1) of Seo) of an unselected memory string, an off voltage (ground in figure 8 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8 of Seo, or time period after t1 in figure 11 of Seo) to switch off an unselected top select transistor coupled to the unselected top select gate.
Regarding claim 15, the combination of Seo and Chen teaches the method of claim 11, further comprising applying, on an unselected top select gate (Unsel DSL(DSL1) of Seo) of an unselected memory string, a second prepare voltage (V2 in figure 11 of Seo) during the first time period to switch on an unselected top select transistor coupled to the unselected top select gate and an off voltage (ground in figure 11 of Seo) during the second time period to switch off the unselected top select transistor.
Regarding independent claim 17, the combination of Seo and Chen teaches a three-dimensional (3D) memory device (figure 3 of Seo), comprising:
memory strings (figure 3 of Seo), each of the memory strings comprising memory cells;
word lines (WL1-WLn in figure 3 of Seo) coupled to the memory strings;
an unselected top select gate (Unsel DSL(DSL1) in figure 8, 11 of Seo) coupled to an unselected memory string of the memory strings; and
a peripheral circuit (120/150 in figure 1 of Seo) coupled to the word lines (WL1-WLn in figure 3 of Seo) and unselected top select gates (Unsel DSL(DSL1) in figure 8, 11 of Seo), wherein the peripheral circuit (120/150 in figure 1 of Seo) is configured to:
apply, on the unselected top select gate (Unsel DSL(DSL1) in figure 8, 11 of Seo), a prepare voltage (V2 in figure 8, 11 of Seo) during a first time period (t1 in figures 8, 11) and an off voltage (ground in figure 8, 11 of Seo) during a second time period (t2 in figure 8 of Seo, or time period after T1 in figure 11 of Seo, [0075] of Seo, “…the drain select line voltage (for example, V.sub.DSL1) of the unselected memory string … may be set to a voltage to turn on the drain select transistor DST…during a first time period…”);
apply, on a selected word line (Sel WL in figures 8, 11 of Seo) of the word lines, a first voltage (ground in figures 8, 11 of Seo) to switch off a target memory cell coupled to the selected word line during the first time period (t1 in figures 8, 11 of Seo) and a read voltage (Vread in figure 8 of Seo, or V5 in figure 11 of Seo, under BRI, a voltage applied to the selected WL during a read operation to facilitate reading can qualify as a “read voltage”) during the second time period (t2 in figure 8 of Seo, or time period after t1 in figure 11 of Seo); and
apply, on an unselected word line (Unsel WLs in figure 8, 11 of Seo) of the word lines, a pass voltage (Vpass in figure 8, 11 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8, or time period after t1 in figure 11 of Seo), wherein the first time period is prior to the second time period (t2 in figure 8, or time period after t1 in figure 11 of Seo).
Regarding claim 18, the combination of Seo and Chen teaches the 3D memory device of claim 17, wherein the peripheral circuit (120/150 in figure 1 of Seo) is further configured to: ramp up the prepare voltage (V2 in figure 8, 11 of Seo) on the unselected top select gate (Unsel DSL(DSL1) in figure 8, 11 of Seo) before ramp up the pass voltage (Vpass in figure 8, 11 of Seo) on the unselected word line (Unsel WLs in figure 8, 11 of Seo).
Regarding claim 19, the combination of Seo and Chen teaches the 3D memory device of claim 18, wherein the unselected word line (Unsel WLs in figure 8, 11 of Seo) reaches the pass voltage (Vpass in figure 8, 11 of Seo) after the unselected top select gate (Unsel DSL(DSL1) in figure 8, 11 of Seo) at the prepare voltage (V2 in figure 8, 11 of Seo).
Regarding claim 20, the combination of Seo and Chen teaches the 3D memory device of claim 17, wherein the peripheral circuit is further configured to apply the read voltage (V5 in figure 11) on the selected word line (Sel WL in figures 8, 11 of Seo) before an unselected top select transistor (Unsel DSL(DSL1) in figure 8, 11 of Seo) is switched off.
Regarding claim 21, the combination of Seo and Chen teaches the 3D memory device of claim 17, wherein the peripheral circuit is further configured to: apply, on a selected top select gate (Sel DSL in figure 8 of Seo) of a selected memory string including the target memory cell, a top select gate voltage (V1 in figure 8 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8 of Seo) to switch on a top select transistor coupled to the selected top select gate; and
apply, on a lower select gate (SSL0 in figure 8 of Seo) of the memory device, a lower select gate voltage (V1 in figure 8 of Seo) during the first time period (t1 in figure 8 of Seo) and the second time period (t2 in figure 8 of Seo) to switch on a lower select transistor (SST in figure 4 of Seo) coupled to the lower select gate (SSL0 in figures 4, 8 of Seo).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over SEO PG PUB 20210027848 (hereinafter SEO), in view of Chen PG PUB 20190074062 (hereinafter Chen), further in view of NAM PG PUB 20160035431 (hereinafter Nam).
Regarding claim 16, the combination of Seo and Chen teaches the method of claim 15, but does not expressly teach further comprising applying the read voltage on the selected word line during the second time period before the unselected top select transistor is switched off.
However, Nam teaches applying a second read voltage VR2 to a selected word line (figure 10, [0107]). Nam further teaches subsequently switching off the first unselected string select transistor by applying a turn-off voltage VOFF to the corresponding first unselected string selection line SSL2 (figure 10, [0109], “…At time T3, turn-off voltage VOFF is applied to the first unselected string selection line SSL2…”). Thus the read voltage VR2 is applied to the selected word line before the unselected string select transistor is switched off.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the read operation of Seo as modified by Chen to employ the read/select-gate timing taught by Nam, such that the read voltage is applied to the selected word line before switching off the unselected string select transistor, in order to provide the known read-operation sequencing and reduce or prevent read disturbance, as taught by Nam ([0093], [0103]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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