DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 11 and 17.
b. Pending: 1-20.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a second prepare voltage” as claimed in claim 9, “the first voltage comprise a first prepare voltage and an off voltage” as claimed in claim 11, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121 (d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New"
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9, 11-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites, “applying, on a selected word line associated with the target memory cell, a first voltage to switch off the target memory cell during the first time period”, Claim 9 recites, “applying a second prepare voltage to the selected word line during the first time period”. But the drawings (figures 5-8) do not clearly show two distinct voltages on Sel_WL during the 1st period. There is no explicit “first voltage” and “second prepare voltage” on Sel_WL during the same first period.
Claim 11 recites, “the first voltage comprise a first prepare voltage and an off voltage”. But the drawings (figures 5-8) do not clearly show two distinct voltages on Sel_WL during the 1st period. There is no explicit “first prepare voltage” and “off voltage” on Sel_WL during the same first period.
Claims 12-16 are also rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph due to their dependency to claim 11.
Regarding claims 9, 11-16, no art is being applied at this time with regarding to these claims due to the nature of the 112 set forth above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7, 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwak PG PUB 20140241069 (hereinafter Kwak).
Regarding independent claim 1, Kwak teaches a method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device ([0054], “…a sensing operation may be performed to sense on/off states of memory cells corresponding to the selected word line WLm-3 and the selected string selection line SSL1…”, figures 3-4), comprising:
applying, on an unselected top select gate (UNSEL_SSLs in figure 4) of an unselected memory string, a first prepare voltage (Vread in figure 4) during a first time period (ST Set up in figure 4) and an off voltage (GND in figure 4) during a second time period (1st Sensing period in figure 4);
applying, on a selected word line (1st SEL WL1 in figure 4) associated with the target memory cell, a first voltage (Ground voltage during ST Setup in figure 4) to switch off the target memory cell during the first time period (ST Set up in figure 4) and a read voltage (Vr in figure 4, [0054], “…a read voltage Vr may be applied to a selected word line WLm-3, and the read pass voltage Vread may be applied to the remaining word lines WL0 to WLm-4 and WLm-2 to WLm…”) during the second time period (1st Sensing period in figure 4); and
applying, on an unselected word line (UNSEL WLs in figure 4), a pass voltage (Vread in figure 4) during the first time period (ST Set up in figure 4) and the second time period (1st Sensing period in figure 4), wherein the first time period (ST Set up in figure 4) is prior to the second time period (1st Sensing period in figure 4).
Regarding claim 2, Kwak teaches the method of claim 1, further comprising:
applying, on a selected top select gate (SEL SSL in figure 4) of a selected memory string containing the target memory cell, a top select gate voltage (Vread in figure 4) during the first time period (ST Set up in figure 4) and the second time period (1st Sensing period in figure 4) to switch on a top select transistor (SST1 in figure 3) coupled to the selected top select gate; and
applying, on a lower select gate (GSL in figure 4) of the memory device, a lower select gate voltage (Vread in figure 4) during the first time period (ST Set up in figure 4) and the second time period (1st Sensing period in figure 4) to switch on a lower select transistor (GST1 in figure 3) coupled to the lower select gate.
Regarding claim 7, Kwak teaches the method of claim 1, further comprising: applying the first prepare voltage (Vread in figure 4) on the unselected top select gate (SEL SSL in figure 4) during the first time period (ST Set up in figure 4) to switch on an unselected top select transistor coupled to the unselected top select gate; and applying the off voltage (GND in figure 4) on the unselected top select gate during the second time period (1st Sensing period in figure 4) to switch off the unselected top select transistor.
Regarding independent claim 17, Kwak teaches a three-dimensional (3D) memory device (figure 1), comprising:
memory strings (figure 3), each of the memory strings comprising memory cells;
word lines (WL0-WLm in figure 3) coupled to the memory strings;
an unselected top select gate (gate connecting to SSL2 in figure 3) coupled to an unselected memory string (string connected to SSL2 in figure 3 when string connected to SSL1 is selected) of the memory strings; and
a peripheral circuit (120 in figure 1) coupled to the word lines (WL0-WLm in figure 3) and unselected top select gates (gate connecting to SSL2-SSL4 in figure 3), wherein the peripheral circuit is configured to:
apply, on the unselected top select gate (UNSEL_SSLs in figure 4, e.g., SSL2), a prepare voltage (Vread in figure 4) during a first time period (ST Set up in figure 4) and an off voltage (GND in figure 4) during a second time period (1st Sensing period in figure 4);
apply, on a selected word line (1st SEL WL1 in figure 4) of the word lines, a first voltage (Ground voltage during ST Setup in figure 4) to switch off a target memory cell coupled to the selected word line during the first time period (ST Set up in figure 4) and a read voltage (Vr in figure 4, [0054], “…a read voltage Vr may be applied to a selected word line WLm-3, and the read pass voltage Vread may be applied to the remaining word lines WL0 to WLm-4 and WLm-2 to WLm…”) during the second time period (1st Sensing period in figure 4); and
apply, on an unselected word line of the word lines (UNSEL WLs in figure 4), a pass voltage (Vread in figure 4) during the first time period (ST Set up in figure 4) and the second time period (1st Sensing period in figure 4), wherein the first time period is prior to the second time period.
Claims 1-8, 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SEO PG PUB 20210027848 (hereinafter SEO).
Regarding independent claim 1, Seo teaches a method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device (figures 3-11, [0009]), comprising:
applying, on an unselected top select gate (Unsel DSL(DSL1) in figure 8, 11) of an unselected memory string, a first prepare voltage (V2 in figures 8, 11) during a first time period (t1 in figures 8, 11) and an off voltage (ground in figure 8, 11) during a second time period (t2 in figure 8, or time period after T1 in figure 11, [0075], “…the drain select line voltage (for example, V.sub.DSL1) of the unselected memory string … may be set to a voltage to turn on the drain select transistor DST…during a first time period…”);
applying, on a selected word line (Sel WL in figures 8, 11) associated with the target memory cell, a first voltage (ground in figures 8, 11) to switch off the target memory cell during the first time period (t1 in figures 8, 11) and a read voltage (Vread in figure 8, or V5 in figure 11, under BRI, a voltage applied to the selected WL during a read operation to facilitate reading can qualify as a “read voltage”) during the second time period (t2 in figure 8, or time period after t1 in figure 11); and
applying, on an unselected word line (Unsel WLs in figure 8), a pass voltage (Vpass in figure 8) during the first time period (t1 in figure 8) and the second time period (t2 in figure 8, or time period after t1 in figure 11), wherein the first time period (t1 in figure 8) is prior to the second time period (t2 in figure 8).
Regarding claim 2, Seo teaches the method of claim 1, further comprising:
applying, on a selected top select gate (Sel DSL in figure 8) of a selected memory string containing the target memory cell, a top select gate voltage (V1 in figure 8) during the first time period (t1 in figure 8) and the second time period (t2 in figure 8) to switch on a top select transistor coupled to the selected top select gate; and
applying, on a lower select gate (SSL0 in figure 8) of the memory device, a lower select gate voltage (V1 in figure 8) during the first time period (t1 in figure 8) and the second time period (t2 in figure 8) to switch on a lower select transistor (SST in figure 4) coupled to the lower select gate (SSL0 in figures 4, 8).
Regarding claim 3, Seo teaches the method of claim 1, further comprising: ramping up the first prepare voltage (V2 in figure 8) on the unselected top select gate (Unsel DSL(DSL1) before ramping up the pass voltage (Vpass in figure 8) on the unselected word line (Unsel WLs in figure 8).
Regarding claim 4, Seo teaches the method of claim 3, wherein the unselected word line (Unsel WLs in figure 8) reaches the pass voltage (Vpass in figure 8) after the unselected top select gate (Unsel DSL(DSL1) at the first prepare voltage (V2 in figure 8).
Regarding claim 5, Seo teaches the method of claim 2, further comprising ramping up the top select gate voltage (V1 in figure 8) on the selected top select gate (Sel DSL in figure 8) and the lower select gate voltage (V1 in figure 8) on the lower select gate (SSL0 in figure 8) before ramping up the pass voltage (Vpass in figure 8) on the unselected word line (Unsel WLs in figure 8).
Regarding claim 6, Seo teaches the method of claim 5, wherein the unselected word line (Unsel WLs in figure 8) reaches the pass voltage (Vpass in figure 8) after the selected top select gate (Sel DSL in figure 8) at the selected top select gate voltage (V1 in figure 8) and the lower select gate (SSL0 in figure 8) at the lower select gate voltage (V1 in figure 8).
Regarding claim 7, Seo teaches the method of claim 1, further comprising: applying the first prepare voltage (V2 in figure 8, or V2 in figure 11) on the unselected top select gate (Unsel DSL(DSL1) during the first time period (t1 in figure 8) to switch on an unselected top select transistor coupled to the unselected top select gate; and applying the off voltage (ground in figure 8) on the unselected top select gate during the second time period (t2 in figure 8 or time period after t1 in figure 11, [0075], “…the drain select line voltage (for example, V.sub.DSL1) of the unselected memory string … may be set to a voltage to turn on the drain select transistor DST…during a first time period…”) to switch off the unselected top select transistor.
Regarding claim 8, Seo teaches the method of claim 7, further comprising: applying the read voltage (V5 in figure 11) on the selected word line (Sel WL in figure 8) before the unselected top select transistor is switched off.
Regarding independent claim 17, Seo teaches a three-dimensional (3D) memory device (figure 3), comprising:
memory strings (figure 3), each of the memory strings comprising memory cells;
word lines (WL1-WLn in figure 3) coupled to the memory strings;
an unselected top select gate (Unsel DSL(DSL1) in figure 8, 11) coupled to an unselected memory string of the memory strings; and
a peripheral circuit (120/150 in figure 1) coupled to the word lines (WL1-WLn in figure 3) and unselected top select gates (Unsel DSL(DSL1) in figure 8, 11), wherein the peripheral circuit (120/150 in figure 1) is configured to:
apply, on the unselected top select gate (Unsel DSL(DSL1) in figure 8, 11), a prepare voltage (V2 in figure 8, 11) during a first time period (t1 in figures 8, 11) and an off voltage (ground in figure 8, 11) during a second time period (t2 in figure 8, or time period after T1 in figure 11, [0075], “…the drain select line voltage (for example, V.sub.DSL1) of the unselected memory string … may be set to a voltage to turn on the drain select transistor DST…during a first time period…”);
apply, on a selected word line (Sel WL in figures 8, 11) of the word lines, a first voltage (ground in figures 8, 11) to switch off a target memory cell coupled to the selected word line during the first time period (t1 in figures 8, 11) and a read voltage (Vread in figure 8, or V5 in figure 11, under BRI, a voltage applied to the selected WL during a read operation to facilitate reading can qualify as a “read voltage”) during the second time period (t2 in figure 8, or time period after t1 in figure 11); and
apply, on an unselected word line (Unsel WLs in figure 8, 11) of the word lines, a pass voltage (Vpass in figure 8, 11) during the first time period (t1 in figure 8) and the second time period (t2 in figure 8, or time period after t1 in figure 11), wherein the first time period is prior to the second time period (t2 in figure 8, or time period after t1 in figure 11).
Regarding claim 18, Seo teaches the 3D memory device of claim 17, wherein the peripheral circuit (120/150 in figure 1) is further configured to: ramp up the prepare voltage (V2 in figure 8, 11) on the unselected top select gate (Unsel DSL(DSL1) in figure 8, 11) before ramp up the pass voltage (Vpass in figure 8, 11) on the unselected word line (Unsel WLs in figure 8, 11).
Regarding claim 19, Seo teaches the 3D memory device of claim 18, wherein the unselected word line (Unsel WLs in figure 8, 11) reaches the pass voltage (Vpass in figure 8, 11) after the unselected top select gate (Unsel DSL(DSL1) in figure 8, 11) at the prepare voltage (V2 in figure 8, 11).
Regarding claim 20, Seo teaches the 3D memory device of claim 17, wherein the peripheral circuit is further configured to apply the read voltage (V5 in figure 11) on the selected word line (Sel WL in figures 8, 11) before an unselected top select transistor (Unsel DSL(DSL1) in figure 8, 11) is switched off.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over SEO PG PUB 20210027848 (hereinafter SEO), in view of Chen PG PUB 20190074062 (hereinafter Chen).
Regarding claim 10, Seo teaches the method of claim 1, but does not teach wherein applying the read voltage comprises applying multiple read voltages on the selected word line during the second time period.
However, Chen teaches applying multiple read voltages to the selected word line during a sensing /verify process, for example, Chen teaches in [0151] “A sensing process can involve applying one or more voltages to a selected word line while sensing whether the associated memory cells are in a conductive or non-conductive state”, and in figure 14 and [0143] that “Read voltages VrA, VrB, VrC, VrD, VrE, VrF and VrG can be used for reading the states of the cells in a read operation”.
It would have been obvious to one of ordinary skill in the art at the time of the effective filing to modify Seo read operation to include multiple read voltages as taught by Chen, in order to improve sensing granularity, support multi-bit state verification/read operations, and improve accuracy/reliability when determining threshold voltage states of memory cells.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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