Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-20 are present for examination.
Claim Objections
Claim(s) 12 is objected to because of the following informalities:
Claim 12 objected to under 37 CFR 1.75 as being a substantial duplicate of claim 4. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 7-9, and 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jan et al. (US 20160293268 A1) in view of Sanjeevarao et al. (US 11049539 B1).
Regarding claims 1, 7-8 and 13-14: Jan discloses an integrated circuit including magnetic OTP memory array (FIG. 3), comprising: A memory device (integrated circuit device 300, FIG. 5), comprising: a magnetoresistive random-access memory (MRAM) cell array (MRAM array 305, FIG. 5) comprising: a first MRAM bit cell (MRAM cells MC00, FIG. 5); a reference MRAM cell (reference MRAM cell RC01, FIG. 5); a one-time programmable (OTP) MRAM cell (OTP MRAM cell OC00, FIG. 5); a memory cell select transistor (transistor M1, FIG. 5) having a first threshold (M1 activates by select signal supplied to gate of transistor, par. 37) configured to selectively apply a first write current to the MRAM bit cell (write current through MTJ stack 110 of MRAM cell 105, par. 38, FIG. 2a-d; through bit liens BLT/BLC, FIG. 5) to selectively write the MRAM bit cell to a parallel state (MTJ stack in parallel state, FIG. 2a) or an anti-parallel state (MTJ in antiparallel state, FIG. 2b); and a reference select transistor (transistor to reference MRAM cells, FIG. 5) connected to the reference MRAM cell, the reference select transistor configured to apply a second write current (through reference bit lines BLTR/BLCR, FIG. 5) to write the reference MRAM cell to the parallel state (reference MRAM cells programmed to parallel orientation, par. 62).
Jan does not disclose a dedicated OTP select transistor having a second threshold lower than the first threshold configured to selectively apply a breakdown current higher than the first write current to the OTP MRAM cell to write the OTP MRAM cell to a breakdown state.
Sanjeevarao does disclose a magnetoresistive random access memory array (FIG. 1), comprising: a OTP select transistor (e.g., OTP row select transistor 152, FIG. 1) having a second threshold lower than the first threshold (OTP devices to be blown have lower voltage requirements, col. 2 ll. 8-14) configured to selectively apply a breakdown current higher than the first write current (higher current driven through OTP cell, col. 9 ll. 49-52)to the OTP MRAM cell to write the OTP MRAM cell to a breakdown state (write to OTP, blowing MTJ, resulting in a very low resistance state, col. 11 ll. 13-15).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jan with the dedicated OTP select transistor of Sanjeevarao to allow the system to control the higher breakdown current specifically to the OTP MRAM cells like the claimed invention.
Regarding claim 3 and 11: Jan discloses an integrated circuit including magnetic OTP memory array (FIG. 3), wherein the MRAM bit cell (memory cell MC, FIG. 5), the reference MRAM cell (reference cell RC, FIG. 5), and the OTP MRAM cell (OTP cell OC, FIG. 5) each comprise a magnetic tunnel junction (MTJ) element (each contain an MTJ element, FIG. 5).
Regarding claims 4 and 12: Jan does not disclose a memory device wherein: the memory cell select transistor is coupled between the MRAM bit cell and a source line; the reference select transistor is coupled between the reference MRAM cell and the source line; and the OTP select transistor is coupled between the OTP MRAM cell and the source line.
Sanjeevarao does disclose a magnetoresistive random access memory array (FIG. 1), comprising wherein: the memory cell select transistor is coupled between the MRAM bit cell and a source line (select transistor 136 connected between MTJ 138 of bit cell 118 and source line (ASL1,1), FIG. 1); the reference select transistor is coupled between the reference MRAM cell and the source line (select transistors connected between their given bit cell and source line ASL, FIG. 1); and the OTP select transistor is coupled between the OTP MRAM cell and the source line (OTP select transistor 152 connected between MTJ 138 of bit cell 154 and source line (ASL1,2), FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jan with the configuration of Sanjeevarao to allow the system to have the MTJ bit cells between a bit line and source line like the claimed invention.
Regarding claim 5: Jan discloses an integrated circuit including magnetic OTP memory array (FIG. 3), further comprising: a second MRAM cell array (second MRAM array e.g, 510, FIG. 7) comprising: a second MRAM bit cell (MRAM cells MC00 of array 510 structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7); a second reference MRAM cell (reference MRAM cell RC01 of array 510 structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7); a second OTP MRAM cell (OTP MRAM cell OC00 of array 510 structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7); a second memory cell select transistor (transistor M1 structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7) configured to selectively apply a third write current to the second MRAM bit cell (M1 activates by select signal supplied to gate of transistor, this current to second array different from first write current applied to first memory array 305, par. 38, FIG. 2a-2d) to selectively write the second MRAM bit cell to the parallel state (MTJ stack in parallel state, FIG. 2a) or the anti-parallel state (MTJ in antiparallel state, FIG. 2b); and a second reference select transistor (transistor to reference MRAM cells structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7) connected to the second reference MRAM cell (FIG. 5), the reference select transistor configured to apply a fourth write current (through reference bit lines BLTR/BLCR, FIG. 5) to write the reference MRAM cell to the parallel state (reference MRAM cells programmed to parallel orientation, par. 62).
Jan does not disclose a second OTP select transistor configured to selectively apply any one of: (i) a second breakdown current higher than the third write current to the second OTP MRAM cell to write the second OTP MRAM cell to the breakdown state or (ii) a fifth write current to write the second OTP MRAM cell to the anti-parallel state.
Sanjeevarao does disclose a magnetoresistive random access memory array (FIG. 1), comprising: a second OTP select transistor (e.g., OTP row select transistor 152, FIG. 1) configured to selectively apply any one of: (i) a second breakdown current higher than the third write current (higher current driven through OTP cell, col. 9 ll. 49-52) to the second OTP MRAM cell to write the second OTP MRAM cell to the breakdown state (write to OTP, blowing MTJ, resulting in a very low resistance state, col. 11 ll. 13-15) or (ii) a fifth write current to write the second OTP MRAM cell to the anti-parallel state.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jan with the dedicated OTP select transistor of Sanjeevarao to allow the system to further comprise of dedicated OTP select transistors among the plurality of memory arrays to control the higher breakdown current specifically to the OTP MRAM cells like the claimed invention.
Regarding claim 9 and 15: Jan does not disclose a memory device, wherein the OTP select transistor is any one of: (i) a larger size compared to the memory cell select transistor, (ii) a lower threshold than the memory cell select transistor, (iii) a thinner oxide transistor than the memory cell select transistor, or (iv) multiple transistors.
Sanjeevarao does disclose a magnetoresistive random access memory array (FIG. 1), wherein the OTP select transistor is any one of: (i) a larger size compared to the memory cell select transistor, (ii) a lower threshold than the memory cell select transistor (OTP devices to be blown have lower voltage requirements, col. 2 ll. 8-14), (iii) a thinner oxide transistor than the memory cell select transistor, or (iv) multiple transistors.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jan with the OTP select transistor configuration of Sanjeevarao to allow the system to share the same lower OTP select transistor threshold like the claimed invention.
Regarding claim 16: Jan discloses an integrated circuit including magnetic OTP memory array (FIG. 3), further comprising: providing a second MRAM bit cell (MRAM cells MC00 of array 510 structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7); controlling a second memory cell select transistor (controlling transistor M1 activates by select signal supplied to gate of transistor, par. 37, FIG. 5) to selectively apply a third write current to the second MRAM bit cell (write current through MTJ stack 110 of MRAM cell 105, par. 38, FIG. 2a-d; through bit liens BLT/BLC, FIG. 5) to selectively write the second MRAM bit cell to the parallel state (MTJ stack in parallel state, FIG. 2a) or the anti-parallel state (MTJ in antiparallel state, FIG. 2b); providing a second reference MRAM cell (reference MRAM cell RC01 of array 510 structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7); controlling a second reference select transistor (controlling transistor connected to reference MRAM cell by select signal supplied to gate of transistor, par. 37, FIG. 5) to selectively apply a fourth write current (through reference bit lines BLTR/BLCR, FIG. 5) to write the reference MRAM cell to the parallel state (reference MRAM cells programmed to parallel orientation, par. 62); providing a second OTP MRAM cell (OTP MRAM cell OC00 of array 510 structured and function as shown as 305 of FIG. 5, par. 73, FIG. 5 and 7).
Regarding claim 17: Jan does not disclose a method further comprising performing a write-verify operation on the OTP MRAM cell and the second OTP MRAM cell to verify the breakdown state of the OTP MRAM cell.
Sanjeevarao does disclose a magnetoresistive random access memory array (FIG. 1), further comprising performing a write-verify operation on the OTP MRAM cell and the second OTP MRAM cell to verify the breakdown state of the OTP MRAM cell (OTP read mode reads the cells as blown or non-blown, col. 12 ll. 10-19, FIG. 4).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jan with the verify operation of Sanjeevarao to allow the system to verify the state of the OTP MRAM cells after each write to ensure proper operation.
Regarding claim 18: Jan does not disclose a method further comprising: controlling a second OTP select transistor to write the second OTP MRAM cell to the anti- parallel state; and comparing read currents of the OTP MRAM cell and the second OTP MRAM cell.
Sanjeevarao does disclose a magnetoresistive random access memory array (FIG. 1), further comprising: controlling a second OTP select transistor to write the second OTP MRAM cell to the anti-parallel state (OTP select transistor 152 can program MTJ 154 of OTP cell 125 to antiparallel, col. 8 ll. 40-65); and comparing read currents (resistance of cells tied to current through, col. 11 ll. 49 – col. 12 ll. 9, FIG. 3) of the OTP MRAM cell (e.g., blown OTP cell distribution 301, FIG. 3) and the second OTP MRAM cell (e.g., another OTP cell written to parallel or antiparallel, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jan with the configuration of Sanjeevarao to allow the system to compare the various OTP MRAM cells in operation to ensure operation like the claimed invention.
Claim(s) 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jan et al. (US 20160293268 A1) in view of Sanjeevarao et al. (US 11049539 B1), in further view of Lee et al. (US 20120087184 A1).
Regarding claim s 2 and 10: Jan does not disclose a memory device, wherein the MRAM cell array further comprises a dummy cell not connected to any of the memory cell select transistor, the reference select transistor, or the OTP select transistor.
Lee does disclose a magnetic random access memory layout (FIG. 2), wherein the MRAM cell array further comprises a dummy cell not connected to any of the memory cell select transistor, the reference select transistor, or the OTP select transistor (dummy bit cells, non-functional memory cells such as floating MTJs not connected to control circuitry, placed around MRAM sub array, par. 7, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Jan and Sanjeevarao with the dummy cell layout of Lee to allow the system to have similar protection for the active MRAM cells of the memory array from outside inference like the claimed invention.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jan et al. (US 20160293268 A1) in view of Sanjeevarao et al. (US 11049539 B1), in further view of Kasuga (US 20040062101 A1).
Regarding claim 6: Jan does not disclose a memory device, wherein the MRAM cell array and the second MRAM cell array are arranged symmetrically.
Kasuga does disclose a semiconductor memory device wherein the MRAM cell array and the second MRAM cell array are arranged symmetrically (a first sub array 13 has cell units arranged in one configuration, adjacent second sub array 15 has a symmetrically arranged configuration relative to sub array 13, par. 36-52, FIG. 7).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the array layout of Jan and Sanjeevarao with the configuration of Kasuga to allow the system to have the mirrored layout like the claimed invention for high efficiency.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jan et al. (US 20160293268 A1) in view of Sanjeevarao et al. (US 11049539 B1), in further view of Okayama (US 20100220517 A1).
Regarding claim 19: Jan does not disclose a memory device, further comprising: performing a write-verify operation to verify the breakdown state of the OTP MRAM cell, wherein performing the write-verify operation comprises: controlling the reference select transistor to apply the second write current to write the reference MRAM cell to the parallel state; applying a read voltage to a bit line the OTP MRAM cell and the reference MRAM cell are connected to; and comparing a OTP MRAM cell read current and a reference MRAM cell read current to verify the breakdown state of the OTP MRAM cell.
Okayama does disclose a semiconductor device (FIG. 1), further comprising: performing a write-verify operation to verify the breakdown state of the OTP MRAM cell (OTP write verify, FIG. 18), wherein performing the write-verify operation comprises: controlling the reference select transistor to apply the second write current to write the reference MRAM cell to the parallel state (writing to reference memory cell, ST30-ST31, par. 204-205, FIG. 18); applying a read voltage to a bit line the OTP MRAM cell and the reference MRAM cell are connected to (read operation ST32, FIG. 18); and comparing a OTP MRAM cell read current and a reference MRAM cell read current to verify the breakdown state of the OTP MRAM cell (read-out current of OTP cell, curve I or III, compared to reference current curve II, par. 159-163, FIG. 12B).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Jan and Sanjeevarao with the operation of Okayama to allow the system to perform the specific write and verify operation to compare an OTP MRAM cell and reference MRAM cell by their read currents to verify breakdown like the claimed invention.
Allowable Subject Matter
Claim(s) 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a method step of controlling the OTP select transistor to apply a third write current to the OTP MRAM cell to attempt to write the OTP MRAM cell to the anti-parallel state, determining the OTP MRAM cell is not in the breakdown state when the OTP select transistor is able to write the OTP MRAM cell to the anti-parallel state, and verifying the OTP MRAM cell and reference MRAM cell by comparing read currents after determining the OTP select transistor is not able to write the OTP MRAM cell to the anti-parallel state as in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights