CTNF 18/948,486 CTNF 99282 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-48 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 12,354,689), hereinafter Lee, in view of Jun et al. (US 2009/0106625), hereinafter Jun . Regarding claim 1 , Lee teaches an integrated circuit ( Lee, Fig. 1, ECC circuit 110 ) comprising: an ECC encoder circuit ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) configured to operate an H matrix on transmission data ( Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability" ) , to generate a transmission parity to be transmitted together with the transmission data, the transmission parity corresponding to the transmission data ( Lee, col. 6, lines 17-19, "The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120" ) ; and an ECC decoder circuit ( Lee, Fig. 3, ECC Decoder (ECC-DEC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) configured to operate the H matrix on reception data ( Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability" ) and a reception parity to detect and correct an error in the reception data ( Lee, col. 6, lines 24-28, "In contrast, the ECC decoder ECC-DEC may output read data RDT_COR, in which an error is corrected, by performing ECC decoding based on read data RDT and the previously generated parity data PRT, which are read from the memory cell array 120" ) . Lee fails to teach wherein a data portion of the H matrix is divided into N groups, each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k. However, Jun, in an analogous art, teaches wherein a data portion of the H matrix is divided into N groups ( Jun, para. [0098], lines 1-2, "The parity check matrix H of LDPC code is set as (Mxz)x(Nxz) matrix. It consists of MxN block matrices" ) , each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group ( Jun, para. [0098], lines 2-5, "each block matrix being different powers of zxz basic permutation matrix... Each block matrix can be uniquely identified by such powers" ; teaches that each block matrix of matrix H corresponds to different powers of a basic permutation matrix which identifies the block location, and the block matrix is a permutation matrix which defines bit relationships within the block matrix ) , the group matrix portion is used by k group matrices that circulate in the N groups ( Jun, para. [0052], lines 2-5, "the identity matrix and the cyclic shift matrix thereof are employed as the basic permutation matrix to extend the said base matrix to be the parity check matrix"; para. [0163] , lines 6-8, "a zxz identity matrix after a night cyclic shift of j bits is used to replace other non-negative coefficient j" ; indicates that the matrix uses multiple cyclic shifted identity matrices ) , and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted (Jun, Fig. 6 teaches multiple cyclic shift matrices inside of matrix H ) , where k is an integer equal to or more than 2 and N is an integer greater than k ( Jun implies this limitation since multiple cyclic shift matrices are used and the H matrix has N block columns ) . Lee and Jun are both considered to be analogous to the claimed invention because both are in the same field of encoder/decoders that utilize matrices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of a H matrix that is divided into N groups, and consists of a group matrix used by group matrices that circulate in the N groups, shifting the positions of the k group matrices every time the group matrices circulate one round. The suggestion/motivation for doing so would be to improve error-correction and allow for efficient encoding/decoding. Regarding claim 2 , the combination of Lee in view of Jun teaches the integrated circuit of claim 1, wherein the non-group matrix portion of each of the N groups has a form in which weights of all column vectors are 1 ( Jun, para. [0132], lines 1-6, “The detailed Bit-filling method in step 3 is as follows: firstly, determining the row weight vector and column weight vector of the original base matrix, then placing "1 "s into the check matrix one by one, while satisfying the constrain condition of short cycle (i.e. the number of the short cycles with length should be as few as possible)” ) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of each of the groups in the non-group matrix position have column vectors with weight that are 1. The suggestion/motivation for doing so would be to maintain matrix sparsity. Regarding claim 3 , the combination of Lee in view of Jun teaches the integrated circuit of claim 2, wherein in the group matrix portion of each of the N groups, all column vectors within a same group have a same form ( Jun, para. [0098] teaches constructing matrix H by expanding identity matrices and cyclic matrices, and using an extension factor greater than 1, the matrices are constructed to have columns having the same form ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of each of the groups in the group matrix position have column vectors with the same form. The suggestion/motivation for doing so would be for simple implementation of ECC matrices. Regarding claim 4 , the combination of Lee in view of Jun teaches the integrated circuit of claim 3, wherein a parity code portion of the H matrix has a form in which weights of all column vectors are 1 ( Jun teaches constructing parity check matrices using identity matrices and cyclic shift matrices and identity matrices inherently have a column weight of 1 per column ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of the parity code portion of the H matrix having all column weights equal 1. The suggestion/motivation for doing so would be that this is a known implementation for identity matrices. Regarding claim 5 , the combination of Lee in view of Jun teaches the integrated circuit of claim 4, wherein all column vectors of the H matrix are linearly independent. While Lee does not explicitly teach the limitation, it does teach using an H matrix for syndrome-based error detection/correction. In order for the matrix to generate syndromes, the column vectors must be linearly independent. Regarding claim 6 , the combination of Lee in view of Jun teaches the integrated circuit of claim 5, wherein the ECC decoder circuit is able to correct a 1-bit error in the reception data ( Lee, col. 5, lines 11-12, “As an example, an ECC circuit included in a DRAM device is configured to correct a 1-bit error” ) . Regarding claim 7 , the combination of Lee in view of Jun teaches the integrated circuit of claim 5, wherein the ECC decoder circuit is able to detect up to X errors within consecutive X bits of the reception data, where X is a maximum column size of the N groups ( Jun, para. [0065], lines 10-14, “This invention improves the performances of such LDPC code under high Signal-to-noise ratio (SNR), accelerates the descending speed of the BER curve, eliminates the error floor of such LDPC code, and has a universal applicability” ; teaches reducing error floors which implies detecting multiple errors ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of the ECC circuit being able to detect up to X errors. The suggestion/motivation for doing so would be to reduce error floors and improve error correction performance. Regarding claim 8 , the combination of Lee in view of Jun teaches the integrated circuit of claim 1, wherein the shift in the positions of the k group matrices indicates a shift of a row where the k group matrices are inserted (Jun, para. [0052], lines 2-5, “the identity matrix and the cyclic shift matrix thereof are employed as the basic permutation matrix to extend the said base matrix to be the parity check matrix” ; teaches using cyclic shift matrices to generate parity-check matrices, where the positions of matrix blocks are shifted relative to each other ) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of shifting rows in matrices. The suggestion/motivation for doing so would be to simplify the implementation of matrices and reduce the amount of storage used in the matrix. Regarding claim 9 , the combination of Lee in view of Jun teaches the integrated circuit of claim 1, wherein each of the transmission data and the reception data comprises normal data and meta data . The reference does not explicitly teach the limitation, however transmitting data and metadata ta is standard in memory systems. The reference already teaches data and parity being stored in memory systems. Regarding claim 10 , the combination of Lee in view of Jun teaches the integrated circuit of claim 1, wherein, when the integrated circuit is a memory controller ( Lee, col. 4, lines 49-50, “The memory device 100 may operate under control of the memory controller 11”; memory devices inherently contain some sort of memory controller ) , the transmission data is write data to be written to a memory, the reception data is read data read from the memory ( Lee, col. 21, lines 59-63, “The controller ECC circuit 3110 may generate a first parity for write data to be stored in the memory device 3200 and may correct an error of read data based on the read data and the first parity that are received from the memory device 3200” ) , and the memory controller further comprises: a data transmission circuit configured to transmit the transmission data and the transmission parity to the memory ( Lee, col. 4, lines 40-43, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100...” ) ; and a data reception circuit configured to receive the read data and the reception parity transmitted from the memory ( Lee, col. 4, lines 40-45, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100 or may be transmitted from the memory device 100 to the memory controller 11” ) . Regarding claim 11 , the combination of Lee in view of Jun teaches the integrated circuit of claim 1, wherein, when the integrated circuit is a memory, the reception data is write data and the reception parity is a write parity, the transmission data is read data and the transmission parity is a read parity, and the memory further comprises: a data reception circuit configured to receive the write data and the write parity transmitted from a memory controller; a memory core configured to store write data processed by the ECC decoder circuit and provide the stored data to the ECC encoder circuit as the read data; and a data transmission circuit configured to transmit the read data and the read parity to the memory controller. This limitation teaches the ECC functionality residing on the memory versus controller-based ECC. This is a well-known design choice for error correction in memory systems. Regarding claim 12 , Lee teaches a memory system ( Lee, Fig. 1, memory system 10 ) comprising a memory controller (Lee, Fig. 1, memory controller 11 ) and a memory ( Lee, Fig. 1, memory device 100 ) , wherein the memory controller ( Lee, col. 4, lines 49-50, “The memory device 100 may operate under control of the memory controller 11”; memory devices inherently contain some sort of memory controller ) comprises: a first ECC encoder circuit configured to operate an H matrix on write data to generate a write parity corresponding to the write data ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) ; a first data transmission circuit configured to transmit the write data and the write parity to the memory ( Lee, col. 4, lines 40-43, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100...” ) ; a first data reception circuit configured to receive read data and a read parity transmitted from the memory ( Lee, col. 4, lines 40-45, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100 or may be transmitted from the memory device 100 to the memory controller 11” ) ; and a first ECC decoder circuit configured to operate the H matrix on the read data and the read parity to detect and correct an error in the read data ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) . Lee fails to teach wherein a data portion of the H matrix is divided into N groups, each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k. However, Jun, in an analogous art, teaches wherein a data portion of the H matrix is divided into N groups ( Jun, para. [0098], lines 1-2, "The parity check matrix H of LDPC code is set as (Mxz)x(Nxz) matrix. It consists of MxN block matrices" ) , each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group ( Jun, para. [0098], lines 2-5, "each block matrix being different powers of zxz basic permutation matrix... Each block matrix can be uniquely identified by such powers" ; teaches that each block matrix of matrix H corresponds to different powers of a basic permutation matrix which identifies the block location, and the block matrix is a permutation matrix which defines bit relationships within the block matrix ) , the group matrix portion is used by k group matrices that circulate in the N groups ( Jun, para. [0052], lines 2-5, "the identity matrix and the cyclic shift matrix thereof are employed as the basic permutation matrix to extend the said base matrix to be the parity check matrix"; para. [0163] , lines 6-8, "a zxz identity matrix after a night cyclic shift of j bits is used to replace other non-negative coefficient j" ; indicates that the matrix uses multiple cyclic shifted identity matrices ) , and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted (Jun, Fig. 6 teaches multiple cyclic shift matrices inside of matrix H ) , where k is an integer equal to or more than 2 and N is an integer greater than k ( Jun implies this limitation since multiple cyclic shift matrices are used and the H matrix has N block columns ) . Lee and Jun are both considered to be analogous to the claimed invention because both are in the same field of encoder/decoders that utilize matrices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of a H matrix that is divided into N groups, and consists of a group matrix used by group matrices that circulate in the N groups, shifting the positions of the k group matrices every time the group matrices circulate one round. The suggestion/motivation for doing so would be to improve error-correction and allow for efficient encoding/decoding. Regarding claim 13 , the combination of Lee in view of Jun teaches the memory system of claim 12, wherein the memory comprises: a second data reception circuit configured to receive the write data and the write parity transmitted from the memory controller; a second ECC decoder circuit configured to operate the H matrix on the write data and the write parity received through the second data reception circuit to detect and correct an error in the write data, a memory core configured to store the write data processed by the second ECC decoder circuit, and provide the stored data as the read data; a second ECC encoder circuit configured to operate the H matrix on the read data to generate a read parity; and a second data transmission circuit configured to transmit the read data and the read parity to the memory controller. Lee already teaches an ECC encoder and decoder operating with a memory device. It would have been obvious to include additional ECC circuitry in the memory, including reception, decoding, encoding circuitry, and a memory core to store and provide data. This structure is commonly incorporated in memory devices with on-die ECC processing for data reliability and reduce the complexity of the memory controller. Claim 14 is a memory system with limitations similar to the integrated circuit of claim 2, and is rejected under the same rationale. Claim 15 is a memory system with limitations similar to the integrated circuit of claim 3, and is rejected under the same rationale. Claim 16 is a memory system with limitations similar to the integrated circuit of claim 4, and is rejected under the same rationale. Claim 17 is a memory system with limitations similar to the integrated circuit of claim 5, and is rejected under the same rationale. Regarding claim 18 , the combination of Lee in view of Jun teaches the memory system of claim 17, wherein each of the first ECC decoder circuit and the second ECC decoder circuit is able to correct a 1-bit error in data processed by each of the first ECC decoder circuit and the second ECC decoder circuit ( Lee, col. 5, lines 11-12, “As an example, an ECC circuit included in a DRAM device is configured to correct a 1-bit error” ) . Regarding claim 19 , the combination of Lee in view of Jun teaches the memory system of claim 17, wherein each of the first ECC decoder circuit and the second ECC decoder circuit is able to detect up to X errors within consecutive X bits of data processed by each of the first ECC decoder circuit and the second ECC decoder circuit, where X is a maximum column size of the N groups ( Jun, para. [0065], lines 10-14, “This invention improves the performances of such LDPC code under high Signal-to-noise ratio (SNR), accelerates the descending speed of the BER curve, eliminates the error floor of such LDPC code, and has a universal applicability” ; teaches reducing error floors which implies detecting multiple errors ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of the ECC circuit being able to detect up to X errors. The suggestion/motivation for doing so would be to reduce error floors and improve error correction performance. Claim 20 is a memory system with limitations similar to the integrated circuit of claim 8, and is rejected under the same rationale. Claim 21 is a memory system with limitations similar to the integrated circuit of claim 9, and is rejected under the same rationale. Regarding claim 22 , Lee teaches a memory system ( Lee, Fig. 1, memory system 10 ) comprising a memory controller (Lee, Fig. 1, memory controller 11 ) and a memory ( Lee, Fig. 1, memory device 100 ) , wherein the memory controller ( Lee, col. 4, lines 49-50, “The memory device 100 may operate under control of the memory controller 11”; memory devices inherently contain some sort of memory controller ) comprises: a first ECC encoder circuit configured to operate an H matrix on 272-bit write data to generate a 16-bit write parity ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) ; a first data transmission circuit configured to transmit the write data and the write parity to the memory ( Lee, col. 4, lines 40-43, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100...” ) ; a first data reception circuit configured to receive 272-bit read data and a 16-bit read parity transmitted from the memory ( Lee, col. 4, lines 40-45, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100 or may be transmitted from the memory device 100 to the memory controller 11” ) ; and a first ECC decoder circuit configured to operate the H matrix on the read data and the read parity to detect and correct an error in the read data ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) . The reference does not explicitly teach a (288,272) block code; however, these parameters are treated as a design choice/routine optimization as parameters are typically chosen based on the desired error correction capacity, and do not convey novelty. Lee fails to teach wherein the H matrix has a size of 16 X 288, a data portion of the H matrix is divided into 22 groups each having a size of 16 X 12 and one group having a size of 16 X 8, each of the 22 groups and the one group comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in each of the 22 groups and the one group, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups is shifted, where k is an integer equal to or more than 2 and smaller than 23. However, Jun, in an analogous art, teaches wherein the H matrix has a size of 16 X 288, a data portion of the H matrix is divided into 22 groups each having a size of 16 X 12 and one group having a size of 16 X 8 ( Jun, para. [0098], lines 1-2, "The parity check matrix H of LDPC code is set as (Mxz)x(Nxz) matrix. It consists of MxN block matrices" ) , each of the 22 groups and the one group comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group ( Jun, para. [0098], lines 2-5, "each block matrix being different powers of zxz basic permutation matrix... Each block matrix can be uniquely identified by such powers" ; teaches that each block matrix of matrix H corresponds to different powers of a basic permutation matrix which identifies the block location, and the block matrix is a permutation matrix which defines bit relationships within the block matrix ) , the group matrix portion is used by k group matrices that circulate in each of the 22 groups and the one group ( Jun, para. [0052], lines 2-5, "the identity matrix and the cyclic shift matrix thereof are employed as the basic permutation matrix to extend the said base matrix to be the parity check matrix"; para. [0163] , lines 6-8, "a zxz identity matrix after a night cyclic shift of j bits is used to replace other non-negative coefficient j" ; indicates that the matrix uses multiple cyclic shifted identity matrices ) , and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups is shifted (Jun, Fig. 6 teaches multiple cyclic shift matrices inside of matrix H ) , where k is an integer equal to or more than 2 and smaller than 23 ( Jun implies this limitation since multiple cyclic shift matrices are used and the H matrix has N block columns ) . The reference does not explicitly teach the H matrix and k group matrices design parameters; however, these parameters are treated as a design choice/routine optimization as parameters are typically chosen based on the desired error correction capacity, and do not convey novelty. Lee and Jun are both considered to be analogous to the claimed invention because both are in the same field of encoder/decoders that utilize matrices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of a H matrix that is divided into N groups, and consists of a group matrix used by group matrices that circulate in the N groups, shifting the positions of the k group matrices every time the group matrices circulate one round. The suggestion/motivation for doing so would be to improve error-correction and allow for efficient encoding/decoding. Claim 23 is a memory system with limitations similar to the memory system of claim 13, and is rejected under the same rationale. Regarding claim 24 , the combination of Lee in view of Jun teaches the memory system of claim 23, wherein the non-group matrix portion of each of the 22 groups and the one group has a form in which weights of all column vectors are 1 ( Jun, para. [0132], lines 1-6, “The detailed Bit-filling method in step 3 is as follows: firstly, determining the row weight vector and column weight vector of the original base matrix, then placing "1 "s into the check matrix one by one, while satisfying the constrain condition of short cycle (i.e. the number of the short cycles with length should be as few as possible)” ) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of each of the groups in the non-group matrix position have column vectors with weight that are 1. The suggestion/motivation for doing so would be to maintain matrix sparsity. Regarding claim 25 , the combination of Lee in view of Jun teaches the memory system of claim 24, wherein in the group matrix portion of each of the 22 groups and the one group, all column vectors within a same group have a same form ( Jun, para. [0098] teaches constructing matrix H by expanding identity matrices and cyclic matrices, and using an extension factor greater than 1, the matrices are constructed to have columns having the same form ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of each of the groups in the group matrix position have column vectors with the same form. The suggestion/motivation for doing so would be for simple implementation of ECC matrices. Regarding claim 26 , the combination of Lee in view of Jun teaches the memory system of claim 25, wherein, in the 22 groups each having a size of 16 X 12, the group matrix portion has a size of 4 X 12, and , in the one group having a size of 16 X 8, the group matrix portion has a size of 4 X 8, in the 22 groups each having a size of 16 X 12, the non-group matrix portion has a size of 12 X 12, and, in the one group having a size of 16 X 8, the non-group matrix portion has a size of 12 X 8 ( Jun, para. [0043] – [0048] teaches constructing parity-check matrices by expanding a base matrix using cyclic shift matrices and the size of the resulting matrix depends on code paraments like code rate, code size, number of parity bits, etc. ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of selecting specific matrix dimensions. The suggestion/motivation for doing so would be that this is a known technique when designing ECC systems in order for the system to satisfy the demands of a large amount of data correction. Regarding claim 27 , the combination of Lee in view of Jun teaches the memory system of claim 26, wherein a parity code portion of the H matrix has a size of 16 X 16 ( Jun, para. [0043] – [0048] teaches constructing parity-check matrices by expanding a base matrix using cyclic shift matrices and the size of the resulting matrix depends on code paraments like code rate, code size, number of parity bits, etc. ) and has a form in which weights of all column vectors are 1 ( Jun teaches constructing parity check matrices using identity matrices and cyclic shift matrices and identity matrices inherently have a column weight of 1 per column ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of the parity code portion of the H matrix having all column weights equal 1. The suggestion/motivation for doing so would be that this is a known implementation for identity matrices. Claim 28 is a memory system with limitations similar to the integrated circuit of claim 5, and is rejected under the same rationale. Claim 29 is a memory system with limitations similar to the memory system of claim 18, and is rejected under the same rationale. Claim 30 is a memory system with limitations similar to the memory system of claim 19, and is rejected under the same rationale. Claim 31 is a memory system with limitations similar to the integrated circuit of claim 8, and is rejected under the same rationale. Claim 32 is a memory system with limitations similar to the integrated circuit of claim 9, and is rejected under the same rationale. Regarding claim 33 , Lee teaches a memory system ( Lee, Fig. 1, memory system 10 ) comprising: a memory core ( Lee, Fig. 1, memory device 100; col. 4, lines 50-56, “In an embodiment, the memory device 100 may be a dynamic random access memory (DRAM) device, but the scope of the present disclosure is not limited thereto. For example, the memory device 100 may include a volatile memory such as an SRAM or a non-volatile memory such as a flash memory, a PRAM, and/or an RRAM” ) ; and an ECC encoder circuit ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) configured to operate an H matrix ( Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability" ) on write data to be stored in the memory core to generate a write parity code to be stored in the memory core together with the write data, the write parity code corresponding to the write data ( Lee, col. 6, lines 17-19, "The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120" ) . Lee fails to teach wherein a data portion of the H matrix is divided into N groups, each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k. However, Jun, in an analogous art, teaches wherein a data portion of the H matrix is divided into N groups ( Jun, para. [0098], lines 1-2, "The parity check matrix H of LDPC code is set as (Mxz)x(Nxz) matrix. It consists of MxN block matrices" ) , each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group ( Jun, para. [0098], lines 2-5, "each block matrix being different powers of zxz basic permutation matrix... Each block matrix can be uniquely identified by such powers" ; teaches that each block matrix of matrix H corresponds to different powers of a basic permutation matrix which identifies the block location, and the block matrix is a permutation matrix which defines bit relationships within the block matrix ) , the group matrix portion is used by k group matrices that circulate in the N groups ( Jun, para. [0052], lines 2-5, "the identity matrix and the cyclic shift matrix thereof are employed as the basic permutation matrix to extend the said base matrix to be the parity check matrix"; para. [0163] , lines 6-8, "a zxz identity matrix after a night cyclic shift of j bits is used to replace other non-negative coefficient j" ; indicates that the matrix uses multiple cyclic shifted identity matrices ) , and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted (Jun, Fig. 6 teaches multiple cyclic shift matrices inside of matrix H ) , where k is an integer equal to or more than 2 and N is an integer greater than k ( Jun implies this limitation since multiple cyclic shift matrices are used and the H matrix has N block columns ) . Lee and Jun are both considered to be analogous to the claimed invention because both are in the same field of encoder/decoders that utilize matrices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of a H matrix that is divided into N groups, and consists of a group matrix used by group matrices that circulate in the N groups, shifting the positions of the k group matrices every time the group matrices circulate one round. The suggestion/motivation for doing so would be to improve error-correction and allow for efficient encoding/decoding. Claim 34 is a memory system with limitations similar to the integrated circuit of claim 2, and is rejected under the same rationale. Claim 35 is a memory system with limitations similar to the integrated circuit of claim 3, and is rejected under the same rationale. Claim 36 is a memory system with limitations similar to the integrated circuit of claim 4, and is rejected under the same rationale. Claim 37 is a memory system with limitations similar to the integrated circuit of claim 5, and is rejected under the same rationale. Regarding claim 38 , the combination of Lee in view of Jun teaches the memory system of claim 37, further comprising: an ECC decoder circuit ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) configured to operate the H matrix on read data read from the memory core and a read parity code read from the memory core to detect and correct an error in the read data ( Lee, col. 6, lines 24-28, "In contrast, the ECC decoder ECC-DEC may output read data RDT_COR, in which an error is corrected, by performing ECC decoding based on read data RDT and the previously generated parity data PRT, which are read from the memory cell array 120" ) . Claim 39 is a memory system with limitations similar to the integrated circuit of claim 6, and is rejected under the same rationale. Claim 40 is a memory system with limitations similar to the integrated circuit of claim 7, and is rejected under the same rationale. Regarding claim 41 , the combination of Lee in view of Jun teaches the memory system of claim 38, wherein the memory system comprises a memory ( Lee, Fig. 1, memory device 100 ) , and the memory core, the ECC encoder circuit, and the ECC decoder circuit are included in the memory ( Lee, Fig. 1 & Fig. 3, memory device 100; col. 4, lines 50-56, “In an embodiment, the memory device 100 may be a dynamic random access memory (DRAM) device, but the scope of the present disclosure is not limited thereto. For example, the memory device 100 may include a volatile memory such as an SRAM or a non-volatile memory such as a flash memory, a PRAM, and/or an RRAM” ). Regarding claim 42 , the combination of Lee in view of Jun teaches the memory system of claim 38, wherein the memory system comprises a memory ( Lee, Fig. 1, memory device 100 ) and a memory controller (Lee, Fig. 1, memory controller 11 ) , the memory core is included in the memory ( Lee, col. 4, lines 50-56, “In an embodiment, the memory device 100 may be a dynamic random access memory (DRAM) device, but the scope of the present disclosure is not limited thereto. For example, the memory device 100 may include a volatile memory such as an SRAM or a non-volatile memory such as a flash memory, a PRAM, and/or an RRAM” ) , and the ECC encoder circuit and the ECC decoder circuit are included in the memory controller ( Lee, Fig. 3; col. 4, lines 49-50, “The memory device 100 may operate under control of the memory controller 11”; memory devices inherently contain some sort of memory controller ) . Regarding claim 43 , Lee teaches an integrated circuit ( Lee, Fig. 1, ECC circuit 110 ) comprising: an ECC encoder circuit ( Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC" ) configured to operate an H matrix on data ( Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability" ) to generate a parity code corresponding to the data ( Lee, col. 6, lines 17-19, "The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120" ) . Lee fails to teach wherein the H matrix comprises N groups each comprising a plurality of column vectors, each of the column vectors of each of the N groups comprises group index bits with a same value within a same group and non-group index bits with different values within the same group, the group index bits are used by k group index bits that circulate in the N groups, and each time the k group index bits circulate one cycle, positions of the group index bits inserted in column vectors are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k. However, Jun, in an analogous art, teaches wherein the H matrix comprises N groups ( Jun, para. [0098], lines 1-2, "The parity check matrix H of LDPC code is set as (Mxz)x(Nxz) matrix. It consists of MxN block matrices" ) each comprising a plurality of column vectors ( Jun, para. [0012], lines 1-2, “Step 2, determining a row weight vector and a column weight vector of said base matrix” ) , each of the column vectors of each of the N groups comprises group index bits with a same value within a same group and non-group index bits with different values within the same group ( Jun, para. [0047], lines 1-3, “based on said original base matrix constructed, choosing values from set { 0, 1,2,L,z-1}, placing them one by one on all of "1" positions in the matrix”; teaches the position of the “1” values being different among the columns within the matrix ) , the group index bits are used by k group index bits that circulate in the N groups ( Jun, para. [0052], lines 2-5, "the identity matrix and the cyclic shift matrix thereof are employed as the basic permutation matrix to extend the said base matrix to be the parity check matrix"; para. [0163] , lines 6-8, "a zxz identity matrix after a night cyclic shift of j bits is used to replace other non-negative coefficient j" ; indicates that the matrix uses multiple cyclic shifted identity matrices ) , and each time the k group index bits circulate one cycle, positions of the group index bits inserted in column vectors are shifted (Jun, Fig. 6 teaches multiple cyclic shift matrices inside of matrix H ) , where k is an integer equal to or more than 2 and N is an integer greater than k ( Jun implies this limitation since multiple cyclic shift matrices are used and the H matrix has N block columns ) . Lee and Jun are both considered to be analogous to the claimed invention because both are in the same field of encoder/decoders that utilize matrices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of a H matrix that is divided into N groups with each group containing column vectors that have group index bits with the same value and non-group index bits with different values, shifting the positions of the column vectors every time the group index bits circulate one round. The suggestion/motivation for doing so would be to improve error-correction, allow for efficient encoding/decoding, and reduce storage requirements for the matrix. Regarding claim 44 , the combination of Lee in view of Jun teaches the integrated circuit of claim 43, wherein each time the k group index bits circulate one cycle, the positions of the group index bits inserted in the column vectors are shifted by a number of the group index bits (Jun, Fig. 6 teaches multiple cyclic shift matrices inside of matrix H ) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of using the number of the group index bits as a shift value. The suggestion/motivation for doing so would be to control the structure of the matrix and improve decoding performance. Regarding claim 45 , the combination of Lee in view of Jun teaches the integrated circuit of claim 43, wherein the N groups are portions corresponding to the data in the H matrix ( Lee teaches the ECC encoder operating on data bits to generate parity bits, which means the matrix would inherently contain columns that correspond to the data portion of a codeword ) . Regarding claim 46 , the combination of Lee in view of Jun teaches the integrated circuit of claim 45, wherein the non-group index bits each have a weight of 1 ( Jun, para. [0132], lines 1-6, “The detailed Bit-filling method in step 3 is as follows: firstly, determining the row weight vector and column weight vector of the original base matrix, then placing "1 "s into the check matrix one by one, while satisfying the constrain condition of short cycle (i.e. the number of the short cycles with length should be as few as possible)” ) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Jun by including the functionality of each of the groups in the non-group matrix bits having weights that are 1. The suggestion/motivation for doing so would be to maintain matrix sparsity. Claim 47 is a memory system with limitations similar to the integrated circuit of claim 4, and is rejected under the same rationale. Claim 48 is a memory system with limitations similar to the integrated circuit of claim 5, and is rejected under the same rationale . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cho et al. (US 11,106,535) teaches an ECC encoder/decoder that generates parity and performs ECC using parity-check matrices. Kim et al. (US 11,462,292) teaches ECC circuitry for memory systems that perform encoding and decoding of data using parity information. Tsuboi et al. (US 9,647,693) teaches generating and using ECC parity matrices for error detection & correction. Yang (US 10,944,429) teaches structured parity check matrices for ECC decoding operations. Lee et al. (US 2023/0146904) teaches ECC processing in an encoder/decoder using parity information. Sharon et al. (US 2018/0159553) teaches LDPC decoding architecture for memory syst3ems utilizing parity-check matrices. Gao et al. (US 2008/0104474) teaches constructing and using LDPC parity check matrices for error correction. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE V BRADEN whose telephone number is (703)756-5381. The examiner can normally be reached Mon-Fri: 9AM-5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /G.V.B./Examiner, Art Unit 2112 /ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112 Application/Control Number: 18/948,486 Page 2 Art Unit: 2112 Application/Control Number: 18/948,486 Page 3 Art Unit: 2112 Application/Control Number: 18/948,486 Page 4 Art Unit: 2112 Application/Control Number: 18/948,486 Page 5 Art Unit: 2112 Application/Control Number: 18/948,486 Page 6 Art Unit: 2112 Application/Control Number: 18/948,486 Page 7 Art Unit: 2112 Application/Control Number: 18/948,486 Page 8 Art Unit: 2112 Application/Control Number: 18/948,486 Page 9 Art Unit: 2112 Application/Control Number: 18/948,486 Page 10 Art Unit: 2112 Application/Control Number: 18/948,486 Page 11 Art Unit: 2112 Application/Control Number: 18/948,486 Page 12 Art Unit: 2112 Application/Control Number: 18/948,486 Page 13 Art Unit: 2112 Application/Control Number: 18/948,486 Page 14 Art Unit: 2112 Application/Control Number: 18/948,486 Page 15 Art Unit: 2112 Application/Control Number: 18/948,486 Page 16 Art Unit: 2112 Application/Control Number: 18/948,486 Page 17 Art Unit: 2112 Application/Control Number: 18/948,486 Page 18 Art Unit: 2112 Application/Control Number: 18/948,486 Page 19 Art Unit: 2112 Application/Control Number: 18/948,486 Page 20 Art Unit: 2112 Application/Control Number: 18/948,486 Page 21 Art Unit: 2112 Application/Control Number: 18/948,486 Page 22 Art Unit: 2112 Application/Control Number: 18/948,486 Page 23 Art Unit: 2112
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