Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 15th, 2026 has been entered. Claims 1-7, 9-19, 21-30, and 32-48 are pending in this application. Applicant amended independent claims 1, 12, 22, 33 and 43, as well as dependent claim 44. Claims 8, 20, and 31 has been canceled. Independent claims 1, 12, 22, 33 and 43 have been amended to clarify that, as the k group matrices (or group index bits) circulate through the N groups, the row positions of the group matrices (or group index bits) inserted in the groups are shifted.
Applicant’s amendments to the claims have been fully considered. The previous rejections set forth in the previously set forth in the previous Office action mailed March 17th, 2026 have been withdrawn in light of the claim amendments and/or applicant’s arguments, which have been found persuasive with respect to the prior art previously relied upon. However, upon further consideration of the amended claims, a new ground(s) of rejection has been made, as set forth below.
Response to Arguments
Applicant's arguments filed June 15th, 2026 have been fully considered but they are not persuasive.
Applicant argues that the applied prior art fails to teach the claimed group matrix portion/non-group matrix portion hierarchy (or group index bits/non-group index bits) and that the cited reference’s cyclic shifting differs from the claimed shifting of row positions. However, the rejection relies on the teachings of the newly applied secondary reference, which teaches a parity-check matrix divided into groups, row permutation, and grouped matrix organization. The combined teachings of the applied references are relied upon to teach or suggest the claimed grouped H-matrix architecture and row position shifting, Accordingly, the applicant’s arguments directed to the previously applied secondary reference are not persuasive with respect to the present rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 9-13, 21-23, 32-33, and 43-45 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 12,354,689), hereinafter Lee, in view of Myung et al. (US 9,768,806), hereinafter Myung.
Regarding claim 1, Lee teaches an integrated circuit (Lee, Fig. 1, ECC circuit 110) comprising:
an ECC encoder circuit (Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC") configured to operate an H matrix on transmission data (Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability"), to generate a transmission parity to be transmitted together with the transmission data, the transmission parity corresponding to the transmission data (Lee, col. 6, lines 17-19, "The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120"); and
an ECC decoder circuit (Lee, Fig. 3, ECC Decoder (ECC-DEC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC") configured to operate the H matrix on reception data (Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability") and a reception parity to detect and correct an error in the reception data (Lee, col. 6, lines 24-28, "In contrast, the ECC decoder ECC-DEC may output read data RDT_COR, in which an error is corrected, by performing ECC decoding based on read data RDT and the previously generated parity data PRT, which are read from the memory cell array 120").
Lee fails to teach wherein a data portion of the H matrix is divided into N groups, each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k.
However, Myung, in an analogous art, teaches wherein a data portion of the H matrix is divided into N groups (Myung, Fig. 4D teaches groups 441-444; col. 2, lines 4-9, “The above LDPC encoding method may further include generating the parity check matrix by performing row permutation and column permutation on a preset parity check matrix; dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a modulation mode”), each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group (Myung, col. 2, lines 4-29 teaches dividing the parity-check matrix into a plurality of groups, where each group includes grouped matrix structures made of sup-groups corresponding to information-word columns, and the grouped matrix structures distinguish one group from another, while the columns and sub-groups within each group distinguish individual bit locations within the corresponding group; while the reference does not explicitly teach the limitation, it would have been obvious to organize the structures taught in Myung into respective portions that distinguish groups and bit locations because organizing portions of a party-check matrix according to their functions would be a predictable implementation choice that allows for matrix organization and hardware processing), the group matrix portion is used by k group matrices that circulate in the N groups (Myung, col. 10, lines 57-63, “Accordingly, as illustrated in FIG. 4B, a sub-group 431 among the sub-groups of the parity check matrix 400 may be a matrix with the circulant permutation matrix structure. The circulant permutation matrix is a square matrix, which may have a structure in which the unit matrix [or, identity matrix] is cyclic shifted”), and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups are shifted (Myung, col. 10, lines 37-38, “The row permutation changes an order of rows of the preset parity check matrix”; col. 10, lines 47-51, “Accordingly, the row permutation may be performed in a variety of manners. As the row permutation is performed on the parity check matrix 400 of FIG. 4A in this manner, the parity check matrix 400 of FIG. 4B may be generated”), where k is an integer equal to or more than 2 and N is an integer greater than k (Myung, col. 8, lines 55-57, “the columns constituting the information word
K
l
d
p
c
sub-matrix 310 are divided into a plurality of groups each having
M
columns”; col. 8, lines 60-65, “Here,
M
denotes an interval at which a same column pattern repeats in the information word sub-matrix 310, and is a size of the cyclic shift appearing in each column
Q
l
d
p
c
of the information word sub-matrix 310. Both
M
and
Q
l
d
p
c
are integers, and are determined to satisfy
Q
l
d
p
c
=
(
N
l
d
p
c
-
K
l
d
p
c
)
/
M
”; col. 12, lines 49-54, “a parity check matrix is divided into a plurality of groups after the row and column permutations so that the number of groups can be an integer multiple of the number of bits constituting a modulation symbol. That is, when the number of bits constituting the modulation symbol is
N
b
, the number of groups may be a multiple of
N
b
”; Myung teaches selecting group parameters in a way where the multiple groups are formed from the overall matrix, which corresponds to the claimed relationship between k and N).
Lee and Myung are both considered to be analogous to the claimed invention because both are in the same field of error correction coding using parity-check matrices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Myung by including the functionality of grouped parity-check matrix structure.
The suggestion/motivation for doing so would be to improve the organization and implementation of the parity-check matrix while still allowing for encoding and decoding functionality.
Regarding claim 9, the combination of Lee in view of Myung teaches the integrated circuit of claim 1, wherein each of the transmission data and the reception data comprises normal data and meta data (Myung, Figs. 2 & 3; col. 6, lines 15-24, “Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC. The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120. For example, with regard to the write data WDT of 128 b, the ECC encoder ECC-ENC may generate the parity data PRT of 8 b by using basis bits BB of 8 b. The write data WDT and the parity data PRT may be stored in the memory cell array 120 through the S/A & W/D 160”; the write data and parity data equate to normal data and meta data, respectively).
Regarding claim 10, the combination of Lee in view of Myung teaches the integrated circuit of claim 1, wherein, when the integrated circuit is a memory controller (Lee, col. 4, lines 49-50, “The memory device 100 may operate under control of the memory controller 11”; memory devices inherently contain some sort of memory controller), the transmission data is write data to be written to a memory, the reception data is read data read from the memory (Lee, col. 21, lines 59-63, “The controller ECC circuit 3110 may generate a first parity for write data to be stored in the memory device 3200 and may correct an error of read data based on the read data and the first parity that are received from the memory device 3200”), and the memory controller further comprises: a data transmission circuit configured to transmit the transmission data and the transmission parity to the memory (Lee, col. 4, lines 40-43, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100...”); and a data reception circuit configured to receive the read data and the reception parity transmitted from the memory (Lee, col. 4, lines 40-45, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100 or may be transmitted from the memory device 100 to the memory controller 11”).
Regarding claim 11, the combination of Lee in view of Myung teaches the integrated circuit of claim 1, wherein, when the integrated circuit is a memory, the reception data is write data and the reception parity is a write parity, the transmission data is read data and the transmission parity is a read parity, and the memory further comprises: a data reception circuit configured to receive the write data and the write parity transmitted from a memory controller (Lee, Fig. 1; col. 4, lines 35-40, “The memory controller 11 may store data in the memory device 100 or may read out data stored in the memory device 100. For example, the memory controller 11 may transmit a clock signal CK and a command/address signal CA to the memory device 100 and may exchange a data signal DQ and a data strobe signal DQS with the memory device 100”); a memory core configured to store write data processed by the ECC decoder circuit (Lee, Figs. 2 & 3; col. 6, lines 24-28, “ the ECC decoder ECC-DEC may output read data RDT_COR, in which an error is corrected, by performing ECC decoding based on read data RDT and the previously generated parity data PRT, which are read from the memory cell array 120”) and provide the stored data to the ECC encoder circuit as the read data (Lee, Figs. 2 & 3; col. 6, lines 15-24, “Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC. The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120…The write data WDT and the parity data PRT may be stored in the memory cell array 120 through the S/A & W/D 160”); and a data transmission circuit configured to transmit the read data and the read parity to the memory controller (Lee, Fig. 1; col. 4, lines 35-40, “The memory controller 11 may store data in the memory device 100 or may read out data stored in the memory device 100. For example, the memory controller 11 may transmit a clock signal CK and a command/address signal CA to the memory device 100 and may exchange a data signal DQ and a data strobe signal DQS with the memory device 100”).
Regarding claim 12, Lee teaches a memory system (Lee, Fig. 1, memory system 10) comprising a memory controller (Lee, Fig. 1, memory controller 11) and a memory (Lee, Fig. 1, memory device 100), wherein the memory controller (Lee, col. 4, lines 49-50, “The memory device 100 may operate under control of the memory controller 11”; memory devices inherently contain some sort of memory controller) comprises:
a first ECC encoder circuit configured to operate an H matrix on write data to generate a write parity corresponding to the write data (Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC");
a first data transmission circuit configured to transmit the write data and the write parity to the memory (Lee, col. 4, lines 40-43, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100...”);
a first data reception circuit configured to receive read data and a read parity transmitted from the memory (Lee, col. 4, lines 40-45, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100 or may be transmitted from the memory device 100 to the memory controller 11”); and
a first ECC decoder circuit configured to operate the H matrix on the read data and the read parity to detect and correct an error in the read data (Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC").
Lee fails to teach wherein a data portion of the H matrix is divided into N groups, each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k.
However, Myung, in an analogous art, teaches wherein a data portion of the H matrix is divided into N groups (Myung, Fig. 4D teaches groups 441-444; col. 2, lines 4-9, “The above LDPC encoding method may further include generating the parity check matrix by performing row permutation and column permutation on a preset parity check matrix; dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a modulation mode”), each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group (Myung, col. 2, lines 4-29 teaches dividing the parity-check matrix into a plurality of groups, where each group includes grouped matrix structures made of sup-groups corresponding to information-word columns, and the grouped matrix structures distinguish one group from another, while the columns and sub-groups within each group distinguish individual bit locations within the corresponding group; while the reference does not explicitly teach the limitation, it would have been obvious to organize the structures taught in Myung into respective portions that distinguish groups and bit locations because organizing portions of a party-check matrix according to their functions would be a predictable implementation choice that allows for matrix organization and hardware processing), the group matrix portion is used by k group matrices that circulate in the N groups (Myung, col. 10, lines 57-63, “Accordingly, as illustrated in FIG. 4B, a sub-group 431 among the sub-groups of the parity check matrix 400 may be a matrix with the circulant permutation matrix structure. The circulant permutation matrix is a square matrix, which may have a structure in which the unit matrix [or, identity matrix] is cyclic shifted”), and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups are shifted (Myung, col. 10, lines 37-38, “The row permutation changes an order of rows of the preset parity check matrix”; col. 10, lines 47-51, “Accordingly, the row permutation may be performed in a variety of manners. As the row permutation is performed on the parity check matrix 400 of FIG. 4A in this manner, the parity check matrix 400 of FIG. 4B may be generated”), where k is an integer equal to or more than 2 and N is an integer greater than k (Myung, col. 8, lines 55-57, “the columns constituting the information word
K
l
d
p
c
sub-matrix 310 are divided into a plurality of groups each having
M
columns”; col. 8, lines 60-65, “Here,
M
denotes an interval at which a same column pattern repeats in the information word sub-matrix 310, and is a size of the cyclic shift appearing in each column
Q
l
d
p
c
of the information word sub-matrix 310. Both
M
and
Q
l
d
p
c
are integers, and are determined to satisfy
Q
l
d
p
c
=
(
N
l
d
p
c
-
K
l
d
p
c
)
/
M
”; col. 12, lines 49-54, “a parity check matrix is divided into a plurality of groups after the row and column permutations so that the number of groups can be an integer multiple of the number of bits constituting a modulation symbol. That is, when the number of bits constituting the modulation symbol is
N
b
, the number of groups may be a multiple of
N
b
”; Myung teaches selecting group parameters in a way where the multiple groups are formed from the overall matrix, which corresponds to the claimed relationship between k and N).
Lee and Myung are both considered to be analogous to the claimed invention because both are in the same field of error correction coding using parity-check matrices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Myung by including the functionality of grouped parity-check matrix structure.
The suggestion/motivation for doing so would be to improve the organization and implementation of the parity-check matrix while still allowing for encoding and decoding functionality.
Regarding claim 13, the combination of Lee in view of Myung teaches the memory system of claim 12, wherein the memory comprises: a second data reception circuit configured to receive the write data and the write parity transmitted from the memory controller; a second ECC decoder circuit configured to operate the H matrix on the write data and the write parity received through the second data reception circuit to detect and correct an error in the write data, a memory core configured to store the write data processed by the second ECC decoder circuit, and provide the stored data as the read data; a second ECC encoder circuit configured to operate the H matrix on the read data to generate a read parity; and a second data transmission circuit configured to transmit the read data and the read parity to the memory controller. Lee already teaches an ECC encoder and decoder operating with a memory device. It would have been obvious to include additional ECC circuitry in the memory, including reception, decoding, encoding circuitry, and a memory core to store and provide data. This structure is commonly incorporated in memory devices with on-die ECC processing for data reliability and reduce the complexity of the memory controller.
Regarding claim 21, the combination of Lee in view of Myung teaches the memory system of claim 12, wherein each of the write data and the read data comprises normal data and meta data (Myung, col. 4, lines 57-65, “the memory device 100 may include an error correction code (ECC) circuit 110. The ECC circuit 110 may be configured to detect and correct an error(s) within data stored in the memory device 100. For example, the ECC circuit 110 may generate parity data by performing ECC encoding on first data received from the memory controller 11. The memory device 100 may store first data received from the memory controller 11 and parity data generated by the ECC circuit 110 together”).
Regarding claim 22, Lee teaches a memory system (Lee, Fig. 1, memory system 10) comprising a memory controller (Lee, Fig. 1, memory controller 11) and a memory (Lee, Fig. 1, memory device 100), wherein the memory controller (Lee, col. 4, lines 49-50, “The memory device 100 may operate under control of the memory controller 11”; memory devices inherently contain some sort of memory controller) comprises:
a first ECC encoder circuit configured to operate an H matrix on 272-bit write data to generate a 16-bit write parity (Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC");
a first data transmission circuit configured to transmit the write data and the write parity to the memory (Lee, col. 4, lines 40-43, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100...”);
a first data reception circuit configured to receive 272-bit read data and a 16-bit read parity transmitted from the memory (Lee, col. 4, lines 40-45, “In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100 or may be transmitted from the memory device 100 to the memory controller 11”); and
a first ECC decoder circuit configured to operate the H matrix on the read data and the read parity to detect and correct an error in the read data (Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC"). The reference does not explicitly teach a (288,272) block code; however, these parameters are treated as a design choice/routine optimization as parameters are typically chosen based on the desired error correction capacity, and do not convey novelty.
Lee fails to teach wherein the H matrix has a size of 16 X 288, a data portion of the H matrix is divided into 22 groups each having a size of 16 X 12 and one group having a size of 16 X 8, each of the 22 groups and the one group comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in each of the 22 groups and the one group, and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups is shifted, where k is an integer equal to or more than 2 and smaller than 23.
However, Myung, in an analogous art, teaches wherein the H matrix has a size of 16 X 288, a data portion of the H matrix is divided into 22 groups each having a size of 16 X 12 and one group having a size of 16 X 8 (Myung, Fig. 4D teaches groups 441-444; col. 2, lines 4-9, “The above LDPC encoding method may further include generating the parity check matrix by performing row permutation and column permutation on a preset parity check matrix; dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a modulation mode”), each of the 22 groups and the one group comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group (Myung, col. 2, lines 4-29 teaches dividing the parity-check matrix into a plurality of groups, where each group includes grouped matrix structures made of sup-groups corresponding to information-word columns, and the grouped matrix structures distinguish one group from another, while the columns and sub-groups within each group distinguish individual bit locations within the corresponding group; while the reference does not explicitly teach the limitation, it would have been obvious to organize the structures taught in Myung into respective portions that distinguish groups and bit locations because organizing portions of a party-check matrix according to their functions would be a predictable implementation choice that allows for matrix organization and hardware processing), the group matrix portion is used by k group matrices that circulate in each of the 22 groups and the one group (Myung, col. 10, lines 57-63, “Accordingly, as illustrated in FIG. 4B, a sub-group 431 among the sub-groups of the parity check matrix 400 may be a matrix with the circulant permutation matrix structure. The circulant permutation matrix is a square matrix, which may have a structure in which the unit matrix [or, identity matrix] is cyclic shifted”), and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups is shifted (Myung, col. 10, lines 37-38, “The row permutation changes an order of rows of the preset parity check matrix”; col. 10, lines 47-51, “Accordingly, the row permutation may be performed in a variety of manners. As the row permutation is performed on the parity check matrix 400 of FIG. 4A in this manner, the parity check matrix 400 of FIG. 4B may be generated”), where k is an integer equal to or more than 2 and smaller than 23 (Myung, col. 8, lines 55-57, “the columns constituting the information word
K
l
d
p
c
sub-matrix 310 are divided into a plurality of groups each having
M
columns”; col. 8, lines 60-65, “Here,
M
denotes an interval at which a same column pattern repeats in the information word sub-matrix 310, and is a size of the cyclic shift appearing in each column
Q
l
d
p
c
of the information word sub-matrix 310. Both
M
and
Q
l
d
p
c
are integers, and are determined to satisfy
Q
l
d
p
c
=
(
N
l
d
p
c
-
K
l
d
p
c
)
/
M
”; col. 12, lines 49-54, “a parity check matrix is divided into a plurality of groups after the row and column permutations so that the number of groups can be an integer multiple of the number of bits constituting a modulation symbol. That is, when the number of bits constituting the modulation symbol is
N
b
, the number of groups may be a multiple of
N
b
”; Myung teaches selecting group parameters in a way where the multiple groups are formed from the overall matrix, which corresponds to the claimed relationship between k and N). The reference does not explicitly teach the H matrix and k group matrices design parameters; however, these parameters are treated as a design choice/routine optimization as parameters are typically chosen based on the desired error correction capacity, and do not convey novelty.
Lee and Myung are both considered to be analogous to the claimed invention because both are in the same field of error correction coding using parity-check matrices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Myung by including the functionality of grouped parity-check matrix structure.
The suggestion/motivation for doing so would be to improve the organization and implementation of the parity-check matrix while still allowing for encoding and decoding functionality.
Claim 23 is a memory system with limitations similar to the memory system of claim 13, and is rejected under the same rationale.
Claim 32 is a memory system with limitations similar to the integrated circuit of claim 9, and is rejected under the same rationale.
Regarding claim 33, Lee teaches a memory system (Lee, Fig. 1, memory system 10) comprising:
a memory core (Lee, Fig. 1, memory device 100; col. 4, lines 50-56, “In an embodiment, the memory device 100 may be a dynamic random access memory (DRAM) device, but the scope of the present disclosure is not limited thereto. For example, the memory device 100 may include a volatile memory such as an SRAM or a non-volatile memory such as a flash memory, a PRAM, and/or an RRAM”); and
an ECC encoder circuit (Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC") configured to operate an H matrix (Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability") on write data to be stored in the memory core to generate a write parity code to be stored in the memory core together with the write data, the write parity code corresponding to the write data (Lee, col. 6, lines 17-19, "The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120").
Lee fails to teach wherein a data portion of the H matrix is divided into N groups, each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group, the group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k.
However, Myung, in an analogous art, teaches wherein a data portion of the H matrix is divided into N groups (Myung, Fig. 4D teaches groups 441-444; col. 2, lines 4-9, “The above LDPC encoding method may further include generating the parity check matrix by performing row permutation and column permutation on a preset parity check matrix; dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a modulation mode”), each of the N groups comprises a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group (Myung, col. 2, lines 4-29 teaches dividing the parity-check matrix into a plurality of groups, where each group includes grouped matrix structures made of sup-groups corresponding to information-word columns, and the grouped matrix structures distinguish one group from another, while the columns and sub-groups within each group distinguish individual bit locations within the corresponding group; while the reference does not explicitly teach the limitation, it would have been obvious to organize the structures taught in Myung into respective portions that distinguish groups and bit locations because organizing portions of a party-check matrix according to their functions would be a predictable implementation choice that allows for matrix organization and hardware processing), the group matrix portion is used by k group matrices that circulate in the N groups (Myung, col. 10, lines 57-63, “Accordingly, as illustrated in FIG. 4B, a sub-group 431 among the sub-groups of the parity check matrix 400 may be a matrix with the circulant permutation matrix structure. The circulant permutation matrix is a square matrix, which may have a structure in which the unit matrix [or, identity matrix] is cyclic shifted”), and each time the k group matrices circulate one round, row positions of the k group matrices inserted in groups are shifted (Myung, col. 10, lines 37-38, “The row permutation changes an order of rows of the preset parity check matrix”; col. 10, lines 47-51, “Accordingly, the row permutation may be performed in a variety of manners. As the row permutation is performed on the parity check matrix 400 of FIG. 4A in this manner, the parity check matrix 400 of FIG. 4B may be generated”), where k is an integer equal to or more than 2 and N is an integer greater than k (Myung, col. 8, lines 55-57, “the columns constituting the information word
K
l
d
p
c
sub-matrix 310 are divided into a plurality of groups each having
M
columns”; col. 8, lines 60-65, “Here,
M
denotes an interval at which a same column pattern repeats in the information word sub-matrix 310, and is a size of the cyclic shift appearing in each column
Q
l
d
p
c
of the information word sub-matrix 310. Both
M
and
Q
l
d
p
c
are integers, and are determined to satisfy
Q
l
d
p
c
=
(
N
l
d
p
c
-
K
l
d
p
c
)
/
M
”; col. 12, lines 49-54, “a parity check matrix is divided into a plurality of groups after the row and column permutations so that the number of groups can be an integer multiple of the number of bits constituting a modulation symbol. That is, when the number of bits constituting the modulation symbol is
N
b
, the number of groups may be a multiple of
N
b
”; Myung teaches selecting group parameters in a way where the multiple groups are formed from the overall matrix, which corresponds to the claimed relationship between k and N).
Lee and Myung are both considered to be analogous to the claimed invention because both are in the same field of error correction coding using parity-check matrices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Myung by including the functionality of grouped parity-check matrix structure.
The suggestion/motivation for doing so would be to improve the organization and implementation of the parity-check matrix while still allowing for encoding and decoding functionality.
Regarding claim 43, Lee teaches an integrated circuit (Lee, Fig. 1, ECC circuit 110) comprising:
an ECC encoder circuit (Lee, Fig. 3, ECC Encoder (ECC-ENC); col. 6, lines 15-17, "Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC") configured to operate an H matrix on data (Lee, col. 2, lines 29-32, "According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability") to generate a parity code corresponding to the data (Lee, col. 6, lines 17-19, "The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120").
Lee fails to teach wherein the H matrix comprises N groups each comprising a plurality of column vectors, each of the column vectors of each of the N groups comprises group index bits with a same value within a same group and non-group index bits with different values within the same group, the group index bits are used by k group index bits that circulate in the N groups, and each time the k group index bits circulate one cycle, positions of the group index bits inserted in column vectors are shifted, where k is an integer equal to or more than 2 and N is an integer greater than k.
However, Myung, in an analogous art, teaches wherein the H matrix comprises N groups (Myung, Fig. 4D teaches groups 441-444; col. 2, lines 4-9, “The above LDPC encoding method may further include generating the parity check matrix by performing row permutation and column permutation on a preset parity check matrix; dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a modulation mode”) each comprising a plurality of column vectors (Myung, col. 8, lines 55-59, “the
K
l
d
p
c
columns constituting the information word sub-matrix 310 are divided into a plurality of groups each having
M
columns, thereby generating a total of
K
l
d
p
c
/
M
column groups. In a same column group, each column is cyclic shifted from a previous column by
Q
l
d
p
c
”), each of the column vectors of each of the N groups comprises group index bits with a same value within a same group (Myung, col. 8 through col. 10 teaches each column group following the same structural pattern, with the columns in a group having the same degree, the rows containing the weight-1 elements are determined according to the same mathematical rule, and a repeated circulant structure within a column group; while the reference does not explicitly teach the limitation, it teaches that the same column group shares the same structural organization and are generated according to the same grouping rules, which equates to identifying information common to the group) and non-group index bits with different values within the same group (Myung, col. 12 teaches circulant permutation matrices being cyclic shifted in a form of
P
a
i
j
, where each column in the group has a different cyclic shift amount [represented by different
a
i
j
exponents; the differing cyclic shift values distinguish one column from another within the same column group), the group index bits are used by k group index bits that circulate in the N groups (Myung, col. 10, lines 57-63, “Accordingly, as illustrated in FIG. 4B, a sub-group 431 among the sub-groups of the parity check matrix 400 may be a matrix with the circulant permutation matrix structure. The circulant permutation matrix is a square matrix, which may have a structure in which the unit matrix [or, identity matrix] is cyclic shifted”), and each time the k group index bits circulate one cycle, row positions of the group index bits inserted in column vectors are shifted (Myung, col. 10, lines 37-38, “The row permutation changes an order of rows of the preset parity check matrix”; col. 10, lines 47-51, “Accordingly, the row permutation may be performed in a variety of manners. As the row permutation is performed on the parity check matrix 400 of FIG. 4A in this manner, the parity check matrix 400 of FIG. 4B may be generated”), where k is an integer equal to or more than 2 and N is an integer greater than k (Myung, col. 8, lines 55-57, “the columns constituting the information word
K
l
d
p
c
sub-matrix 310 are divided into a plurality of groups each having
M
columns”; col. 8, lines 60-65, “Here,
M
denotes an interval at which a same column pattern repeats in the information word sub-matrix 310, and is a size of the cyclic shift appearing in each column
Q
l
d
p
c
of the information word sub-matrix 310. Both
M
and
Q
l
d
p
c
are integers, and are determined to satisfy
Q
l
d
p
c
=
(
N
l
d
p
c
-
K
l
d
p
c
)
/
M
”; col. 12, lines 49-54, “a parity check matrix is divided into a plurality of groups after the row and column permutations so that the number of groups can be an integer multiple of the number of bits constituting a modulation symbol. That is, when the number of bits constituting the modulation symbol is
N
b
, the number of groups may be a multiple of
N
b
”; Myung teaches selecting group parameters in a way where the multiple groups are formed from the overall matrix, which corresponds to the claimed relationship between k and N).
Lee and Myung are both considered to be analogous to the claimed invention because both are in the same field of error correction coding using parity-check matrices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Myung by including the functionality of grouped parity-check matrix structure.
The suggestion/motivation for doing so would be to improve the organization and implementation of the parity-check matrix while still allowing for encoding and decoding functionality.
Regarding claim 44, the combination of Lee in view of Jun teaches the integrated circuit of claim 43, wherein each time the k group index bits circulate one cycle, the row positions of the group index bits inserted in the column vectors are shifted by a number of the group index (Myung, col. 10, lines 37-38, “The row permutation changes an order of rows of the preset parity check matrix”; col. 10, lines 47-51, “Accordingly, the row permutation may be performed in a variety of manners. As the row permutation is performed on the parity check matrix 400 of FIG. 4A in this manner, the parity check matrix 400 of FIG. 4B may be generated”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Myung by including the functionality of the row permutation and cyclic shifting techniques.
The suggestion/motivation for doing so would be to vary the row positions of the grouped matrix elements while keeping the desired parity-matrix structure and improving the matrix organization for encoding and decoding.
Regarding claim 45, the combination of Lee in view of Myung teaches the integrated circuit of claim 43, wherein the N groups are portions corresponding to the data in the H matrix (Myung, col. 8, lines 55-57, “the columns constituting the information word
K
l
d
p
c
sub-matrix 310 are divided into a plurality of groups each having
M
colunms”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Lee to incorporate the teachings of Myung by including the functionality of organizing the H-matrix into groups corresponding to data portions.
The suggestion/motivation for doing so would be to vary the row positions of the grouped matrix elements while keeping the desired parity-matrix structure and improving the matrix organization for encoding and decoding.
Allowable Subject Matter
Claims 2-7, 14-19, 34-42 and 46-48 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jeong et al. (US 2015/0039973) teaches rearranging LDPC groups into group units by changing their locations, and also uses group/block-row interleaving.
Myung et al. (US 2021/0075442) teaches QC-LDPC parity-check matrices organized into row blocks and column blocks containing circulant permutation matrices.
Myung et al. (US 2021/0391946) teaches a QC-LDPC H matrix with row blocks, column blocks, circulant permutation matrices, information-word column blocks, and parity column blocks.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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