DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on August 1, 2025 has been fully considered by the examiner.
Claim Objections
3. Claim 16 is objected to because of the following informalities.
Lines 4-6 recite the limitation, “a first end of the first switching transistor is coupled to the alternating current signal generator, and the second end of the first switching transistor is configured to receive the first alternating current signal.” Examiner believes “the second end of the first switching transistor is configured to receive the first alternating current signal” is a typographical error because the alternating current signal generator is coupled to the first end. Also, compare this limitation to a similar limitation in claim 4, lines 4-6. For these reasons, Examiner believes the limitation should recite, “a first end of the first switching transistor is coupled to the alternating current signal generator, and the first end of the first switching transistor is configured to receive the first alternating current signal.”
Appropriate correction is required.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
5. The abstract of the disclosure is objected to because it recites “are described” in line 2, which can be implied. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 6 and 8 and 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites in lines 2-3 the limitation, “a read/write process of the ferroelectric memory cell,” which is indefinite. For the purpose of this action, the limitation, “a read/write process of the ferroelectric memory cell,” shall be interpreted as “[[a]] the read/write process of the ferroelectric memory cell,” which finds antecedent basis in claim 3, lines 2-3.
Claims 13-20 each recite the limitation “the ferroelectric memory cell.” There is insufficient antecedent basis for this limitation in the claims. For the purpose of this action, in claim 13, line 15, the limitation “the ferroelectric memory cell” shall be interpreted as “[[the]] a ferroelectric memory cell of the plurality of ferroelectric memory cells.” Subsequent instances of “the ferroelectric memory cell” in claims 13-20 shall be interpreted as “the ferroelectric memory cell of the plurality of ferroelectric memory cells.”
Claim 16 recites the limitation, “the second end of the first switching transistor,” in line 5. There is insufficient antecedent basis for this limitation in the claims. For the purpose of this action, the limitation “the second end of the first switching transistor” in line 5 shall be interpreted as “[[the]] a second end of the first switching transistor,” and the limitation, “a second end of the first switching transistor” in line 7 shall be interpreted as “[[a]] the second end of the first switching transistor.”
Claim 18 recites in lines 2-3 the limitation, “a read/write process of the ferroelectric memory cell,” which is indefinite. For the purpose of this action, the limitation, “a read/write process of the ferroelectric memory cell,” shall be interpreted as “[[a]] the read/write process of the ferroelectric memory cell,” which finds antecedent basis in claim 15, lines 2-3.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Mariani, et al (US 20170358370 A1), hereinafter Mariani, in view of Yan (US 9899085 B1).
Regarding independent claim 1, Mariani teaches a control apparatus of a ferroelectric memory (FIG. 7; ¶[0079]).
Mariani does not teach he control apparatus comprising a signal control device (the present application defines “signal control device (unit)” as including switching transistors – see, e.g., ¶[0013]).
Yan teaches in FIG. 4C a control signal (430) coupled to a signal control device (transistors 423 and 429) to select between two voltage sources (VPP and -Vneg) to input to the plate line (Plate-Line).
Mariani as modified by Yan further teaches the signal control device is coupled to a memory controller (Mariani FIG. 7, memory controller 140-b controlling Yan FIG. 4c control signal 430).
Mariani further teaches an alternating current signal generator (FIG. 4, 410 shows AC waveform applied to a plate line during recovery operations as controlled by Biasing Component 710 in FIG. 7; ¶[0029], [0047-0048], [0080]), and a plate line (FIG. 7, 210-a; ¶[0079]) coupled to a ferroelectric memory cell (FIG. 7, 105-c; ¶[0079]), wherein:
the memory controller is configured to implement read/write control on the ferroelectric memory cell (¶[0028] teaches “memory controller 140 may control the operation (e.g., read, write, re-write, refresh, recovery, etc.) of memory cells”);
the alternating current signal generator is configured to generate a first alternating current signal (FIG. 4, e.g. 410); and
the ferroelectric memory cell comprises a ferroelectric capacitor (FIG. 2, 205), and the plate line is connected to one end of the ferroelectric capacitor (FIG. 2, plate line 210 is shown connected to one end of capacitor 205; ¶[0029]); and
the signal control device is configured to switch a signal inputted to the plate line to the first alternating current signal (FIG. 4, recovery operation 410) or a read/write pulse signal (FIG. 4, access operation 405; ¶[0047]) outputted by the memory controller (¶[0023] and [0028] discuss memory controller 140 controlling both access and recovery operations; FIG. 7, memory controller 140-b includes biasing component 710), wherein the read/write pulse signal is used to write data into the ferroelectric memory cell or read data from the ferroelectric memory cell (¶[0022-0023] teach access operations include both read and write operations; ¶[0028] teaches “memory controller 140 may control the operation (e.g., read, write, re-write, refresh, recovery, etc.) of memory cells 105…may also generate and control various voltages used during the operation of memory array 100. In general, the amplitude, shape, or duration of an applied voltage discussed herein may be adjusted or varied and may be different for the various operations for operating memory array 100.”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yan into the method of Mariani to include a plate line signal generator (Yan FIG. 4c, 420). The ordinary artisan would have been motivated to modify Mariani in the above manner for the purpose of providing a selectable plate voltage (Yan, Col. 6, ll. 45-63).
10. Claims 2 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Mariani, et al (US 20170358370 A1), hereinafter Mariani, in view of Yan (US 9899085 B1), and further in view of Mihara, et al (US 5666305 A), hereinafter Mihara.
Regarding claim 2, Mariani teaches the limitations of claim 1.
Mariani further teaches the control apparatus further comprises the memory controller (FIG. 7, 140-b), a read/write interval of the ferroelectric memory cell (FIG. 4, access operation 405), and input the first alternating current signal to the plate line (FIG. 7, Plate Bias on plate line 210-a; ¶[0079]).
Yan further teaches in FIG. 4C a control signal (430) coupled to a signal control device (transistors 423 and 429) to select between two voltage sources (VPP and -Vneg) to input to the plate line (Plate-Line).
Mihara teaches a controller generating read and write pulses to a signal control device (FIGS. 5A, 5C; Col. 5, ll. 61-65).
Therefore, Mariani as modified by Yan and Mihara teaches the control apparatus further comprises the memory controller (Mariani), the memory controller is further configured to send a first enable signal (Mihara) to the signal control device (Yan) in a read/write interval (Mariani) of the ferroelectric memory cell, and the first enable signal is used to control the signal control device (Yan) to input the first alternating current signal to the plate line (Mariani).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Mihara into the method of Mariani to include a read/write pulse generated by a controller. The ordinary artisan would have been motivated to modify Mariani in the above manner for the purpose of applying read and write pulses to a signal control device (FIGS. 5A, 5C; Col. 5, ll. 61-65).
Regarding independent claim 9, Mariani teaches a control apparatus of a ferroelectric memory (FIG. 7; ¶[0079]).
Mariani does not teach he control apparatus comprising a signal control device (the present application defines “signal control device (unit)” as including switching transistors – see, e.g., ¶[0013]).
Yan teaches in FIG. 4C a control signal (430) coupled to a signal control device (transistors 423 and 429) to select between two voltage sources (VPP and -Vneg) to input to the plate line (Plate-Line).
Mariani as modified by Yan further teaches the signal control device is coupled to a memory controller (Mariani FIG. 7, memory controller 140-b controlling Yan FIG. 4c control signal 430).
Mariani further teaches an alternating current signal generator (FIG. 4, 410 shows AC waveform applied to a plate line during recovery operations as controlled by Biasing Component 710 in FIG. 5; ¶[0029], [0047-0048], [0080]), and a plate line (FIG. 7, 210-a; ¶[0079]) coupled to a ferroelectric memory cell (FIG. 7, 105-c; ¶[0079]), wherein:
the memory controller is configured to implement read/write control on the ferroelectric memory cell (¶[0028] teaches “memory controller 140 may control the operation (e.g., read, write, re-write, refresh, recovery, etc.) of memory cells”);
the alternating current signal generator is configured to generate an alternating current signal (FIG. 4, e.g. 410); and
the ferroelectric memory cell comprises a ferroelectric capacitor (FIG. 2, 205), and the plate line is connected to one end of the ferroelectric capacitor (FIG. 2, plate line 210 is shown connected to one end of capacitor 205; ¶[0029]).
Mariani does not teach the signal control device is configured to:
superimpose the alternating current signal and a read/write pulse signal output by the memory controller.
Mihara teaches a controller generating read and write pulses to a signal control device (FIGS. 5A, 5C; Col. 5, ll. 61-65), and superimpose the second alternating current signal and the read/write pulse signal (FIG. 23B shows a pulse train (AC signal) superimposed on a DC level (a pulse is DC within a given period) resulting from the circuit of FIG. 23A; Col. 12, ll. 37-50; see also FIG. 21A).
Mariani as modified by Yan and Mihara teaches input a superimposed signal to the plate line (specifically, Yan teaches in FIG. 4c the output of the transistor multiplexer is connected to the plate line), and
wherein the read/write pulse signal is used to write data into the ferroelectric memory cell or read data from the ferroelectric memory cell (Mariani ¶[0022-0023] teach access operations include both read and write operations; ¶[0028] teaches “memory controller 140 may control the operation (e.g., read, write, re-write, refresh, recovery, etc.) of memory cells 105…may also generate and control various voltages used during the operation of memory array 100. In general, the amplitude, shape, or duration of an applied voltage discussed herein may be adjusted or varied and may be different for the various operations for operating memory array 100.”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yan into the method of Mariani to include a plate line signal generator (Yan FIG. 4c, 420). The ordinary artisan would have been motivated to modify Mariani in the above manner for the purpose of providing a selectable plate voltage (Yan, Col. 6, ll. 45-63).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Mihara into the method of Mariani to include a read/write pulse generated by a controller. The ordinary artisan would have been motivated to modify Mariani in the above manner for the purpose of applying read and write pulses to a signal control device (FIGS. 5A, 5C; Col. 5, ll. 61-65).
Regarding claim 10, Mariani as modified by Yan and Mihara teaches the limitations of claim 9.
Mariani as modified by Yan and Mihara further teaches the control apparatus further comprises the memory controller (Mariani FIG. 7, 140-b), the memory controller is configured to send a first enable signal (Yan, FIG. 4c, 430) to the signal control device (Yan, FIG. 4c, transistors 423 and 429) in a read/write process (Mariani FIG. 4, access operation 405) of the ferroelectric memory cell, and the first enable signal is used to control the signal control device to input superimposition of the alternating current signal and the read/write pulse signal to the plate line (i.e., in the modified device, the superimposed signal is routed to Yan FIG. 4c, Plate-Line, which is mapped to Mariani FIG. 7, Plate Bias on plate line 210-a; ¶[0079]).
Regarding claim 11, Mariani as modified by Yan and Mihara teaches the limitations of claim 9.
Mariani further teaches a frequency of the second alternating current signal is greater than a frequency of the read/write pulse signal (FIG. 4, 405 shows multiple periods of the alternating current signal within the period of a memory access (read/write) operation; ¶[0049]).
Mariani does not teach the range of an amplitude of the second alternating current signal is less than 1/2 of an amplitude of the read/write pulse signal. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A).
11. Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Mariani, et al (US 20170358370 A1), hereinafter Mariani, in view of Yan (US 9899085 B1), further in view of Mihara, et al (US 5666305 A), hereinafter Mihara, and further in view of Amini-Valashani, et al (Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder, Microelectronics Journal, Volume 74, 2018, Pages 49-59), hereinafter Amini-Valashani.
Regarding claim 3, Mariani as modified by Yan and Mihara teaches the limitations of claim 2.
Mariani does not teach the memory controller is further configured to send a second enable signal to the signal control device in a read/write process of the ferroelectric memory cell, and the second enable signal is used to control the signal control device to input the read/write pulse signal to the plate line.
Amini-Valashani teaches a 2:1 transistor multiplexer with independent control signals coupled to the gates of the transistors (FIGS. 8(a) and 8(b), in which, e.g., signal x may be assigned to an alternating current signal generator and signal y may be assigned to a read/write pulse signal).
Therefore, Mariani as modified by Yan, Mihara, and Amini-Valashani teaches the memory controller is further configured to send a second enable signal to the signal control device in a read/write process of the ferroelectric memory cell, and the second enable signal is used to control the signal control device to input the read/write pulse signal to the plate line.
Because both Yan and Amini-Valashani teach a two-transistor 2:1 multiplexer, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the multiplexer of Amini-Valashani with the multiplexer of Yan to yield predictable results. See MPEP § 2143(I)(B).
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Figure A. The 2:1 multiplexers of Yan (left) and Amini-Valashani (right).
Regarding claim 4, Mariani as modified by Yan, Mihara, and Amini-Valashani teaches the limitations of claim 3.
Amini-Valashani further teaches the signal control device comprises a first switching transistor (FIG. 8(a), e.g., top transistor) and a second switching transistor (FIG. 8(a), e.g., bottom transistor) that are connected in series;
a first end of the first switching transistor is coupled to the alternating current signal generator, and the first end of the first switching transistor is configured to receive the first alternating current signal (FIG. 8(a), e.g., signal x may be assigned the alternating current signal);
a second end of the first switching transistor is coupled to a first end of the second switching transistor (FIG. 8(a), node z);
the first enable signal is used to control the first switching transistor to be turned on and the second switching transistor to be turned off (FIG. 8(a), signal “sel bar”); and
the second enable signal is used to control the first switching transistor to be turned off and the second switching transistor to be turned on (FIG. 8(a), signal “sel”).
Mihara and Amini-Valashani together further teach a second end of the second switching transistor is coupled to the memory controller, and the second end of the second switching transistor is configured to receive the read/write pulse signal (Amini-Valashani signal y in FIG. 8(a), which may be assigned to Mihara read and write pulses generated by a controller in FIGS. 5A, 5C);
Regarding claim 5, Mariani as modified by Yan, Mihara, and Amini-Valashani teaches the limitations of claim 4.
Mariani further teaches the alternating current signal generator is configured to generate a second alternating current signal (FIG. 4, e.g., 405).
Mihara further teaches the signal control device is further configured to:
superimpose the second alternating current signal and the read/write pulse signal (FIG. 23B shows a pulse train (AC signal) superimposed on a DC level (a pulse is DC within a given period) resulting from the circuit of FIG. 23A; Col. 12, ll. 37-50; see also FIG. 21A).
Mariani as modified by Yan, Mihara, and Amini-Valashani teaches input a superimposed signal to the plate line (specifically, Yan teaches in FIG. 4c the output of the transistor multiplexer is connected to the plate line).
Regarding claim 6, Mariani as modified by Yan, Mihara, and Amini-Valashani teaches the limitations of claim 5.
Mariani as modified by Yan, Mihara, and Amini-Valashani further teaches the memory controller is further configured to send a third enable signal to the signal control device in a read/write process of the ferroelectric memory cell, and the third enable signal is used to control the signal control device to input the superimposed signal to the plate line (Mihara FIG. 23A, switch 11 controls superimposing signals 13’, 14’, and/or 15’ onto the plate line and may be implemented with additional control signals and transistors of Amini-Valashani).
Regarding claim 7, Mariani as modified by Yan, Mihara, and Amini-Valashani teaches the limitations of claim 5.
Mariani further teaches a frequency of the second alternating current signal is greater than a frequency of the read/write pulse signal (FIG. 4, 405 shows multiple periods of the alternating current signal within the period of a memory access (read/write) operation; ¶[0049]).
Mariani does not teach the range of an amplitude of the second alternating current signal is less than 1/2 of an amplitude of the read/write pulse signal. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A).
12. Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Mariani, et al (US 20170358370 A1), hereinafter Mariani, in view of Yan (US 9899085 B1), and further in view of Harms, et al (US 20210319843 A1), hereinafter Harms.
Regarding independent claim 13, Mariani teaches a ferroelectric memory (FIG. 7, 100-b; ¶[0079]), comprising a memory array (FIG. 1, 100), and a memory controller (FIG. 7, memory controller 140-b).
Mariani does not teach he control apparatus comprising a signal control device (the present application defines “signal control device (unit)” as including switching transistors – see, e.g., ¶[0013]).
Yan teaches in FIG. 4C a control signal (430) coupled to a signal control device (transistors 423 and 429) to select between two voltage sources (VPP and -Vneg) to input to the plate line (Plate-Line).
Mariani as modified by Yan further teaches the signal control device is coupled to a memory controller (Mariani FIG. 7, memory controller 140-b controlling Yan FIG. 4c control signal 430).
Mariani further teaches the memory array comprises a plurality of ferroelectric memory cells (FIG. 1, 100 includes a plurality of memory cells 105), an alternating current signal generator (FIG. 4, 410 shows AC waveform applied to a plate line during recovery operations as controlled by Biasing Component 710 in FIG. 5; ¶[0029], [0047-0048], [0080]), and a plate line (FIG. 7, 210-a; ¶[0079]) coupled to the memory array (¶[0035] teaches “plate line 210 may be connected to multiple memory cells 105”);
the memory controller is configured to implement read/write control on each ferroelectric memory cell (¶[0028] teaches “memory controller 140 may control the operation (e.g., read, write, re-write, refresh, recovery, etc.) of memory cells”);
the alternating current signal generator is configured to generate a first alternating current signal (FIG. 4, e.g. 410);
each ferroelectric memory cell comprises a ferroelectric capacitor (FIG. 2, 205), and the plate line is connected to one end of each ferroelectric capacitor (FIG. 2, plate line 210 is shown connected to one end of capacitor 205; ¶[0029]); and
the signal control device is configured to switch a signal inputted to the plate line to the first alternating current signal (FIG. 4, recovery operation 410) or a read/write pulse signal (FIG. 4, access operation 405; ¶[0047]) outputted by the memory controller (¶[0023] and [0028] discuss memory controller 140 controlling both access and recovery operations; FIG. 7, memory controller 140-b includes biasing component 710), wherein the read/write pulse signal is used to write data into the ferroelectric memory cell or read data from the ferroelectric memory cell (¶[0022-0023] teach access operations include both read and write operations; ¶[0028] teaches “memory controller 140 may control the operation (e.g., read, write, re-write, refresh, recovery, etc.) of memory cells 105…may also generate and control various voltages used during the operation of memory array 100. In general, the amplitude, shape, or duration of an applied voltage discussed herein may be adjusted or varied and may be different for the various operations for operating memory array 100.”).
Mariani does not explicitly teach all ferroelectric memory cells in one memory array are coupled to a same plate line.
Harms teaches all ferroelectric memory cells in one memory array are coupled to a same plate line (¶[0353] teaches “enabling a memory array or applying an array-level biasing (e.g., biasing a common plate of the memory array)”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yan into the method of Mariani to include a plate line signal generator (Yan FIG. 4c, 420). The ordinary artisan would have been motivated to modify Mariani in the above manner for the purpose of providing a selectable plate voltage (Yan, Col. 6, ll. 45-63).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Harms into the method of Mariani to include a common plate of a memory array. The ordinary artisan would have been motivated to modify Mariani in the above manner for the purpose of array-level biasing (Harms ¶[0353]).
Regarding claim 14, Mariani as modified by Yan and Harms teaches the limitations of claim 13.
Mariani as modified by Yan and Harms further teaches the memory controller is further configured to send a first enable signal (Yan, FIG. 4c, 430) to the signal control device in a read/write interval (Mariani FIG. 4, access operation 405) of the ferroelectric memory cell, and the first enable signal is used to control the signal control device (Yan, FIG. 4c, transistors 423 and 429) to input the first alternating current signal to the plate line (i.e., in the modified device, the first alternating current signal is routed to Yan FIG. 4c, Plate-Line, which is mapped to Mariani FIG. 7, Plate Bias on plate line 210-a; ¶[0079]).
13. Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mariani, et al (US 20170358370 A1), hereinafter Mariani, in view of Yan (US 9899085 B1), further in view of Harms, et al (US 20210319843 A1), hereinafter Harms, further in view of Mihara, et al (US 5666305 A), hereinafter Mihara, and further in view of Amini-Valashani, et al (Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder, Microelectronics Journal, Volume 74, 2018, Pages 49-59), hereinafter Amini-Valashani.
Regarding claim 15, Mariani as modified by Yan and Harms teaches the limitations of claim 14.
Mariani does not teach the memory controller is further configured to send a second enable signal to the signal control device in a read/write process of the ferroelectric memory cell, and the second enable signal is used to control the signal control device to input the read/write pulse signal to the plate line.
Mihara teaches a controller generating read and write pulses to a signal control device (FIGS. 5A, 5C; Col. 5, ll. 61-65).
Amini-Valashani teaches a 2:1 transistor multiplexer with independent control signals coupled to the gates of the transistors (FIGS. 8(a) and 8(b), in which, e.g., signal x may be assigned to an alternating current signal generator and signal y may be assigned to a read/write pulse signal).
Therefore, Mariani as modified by Yan, Harms, Mihara, and Amini-Valashani teaches the memory controller is further configured to send a second enable signal to the signal control device in a read/write process of the ferroelectric memory cell, and the second enable signal is used to control the signal control device to input the read/write pulse signal to the plate line.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Mihara into the method of Mariani to include a read/write pulse generated by a controller. The ordinary artisan would have been motivated to modify Mariani in the above manner for the purpose of applying read and write pulses to a signal control device (FIGS. 5A, 5C; Col. 5, ll. 61-65).
Because both Yan and Amini-Valashani teach a two-transistor 2:1 multiplexer, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the multiplexer of Amini-Valashani with the multiplexer of Yan to yield predictable results. See MPEP § 2143(I)(B).
Regarding claim 16, Mariani as modified by Yan, Harms, Mihara, and Amini-Valashani teaches the limitations of claim 15.
Amini-Valashani further teaches the signal control device comprises a first switching transistor (FIG. 8(a), e.g., top transistor) and a second switching transistor (FIG. 8(a), e.g., bottom transistor) that are connected in series;
a first end of the first switching transistor is coupled to the alternating current signal generator, and the second end of the first switching transistor is configured to receive the first alternating current signal (FIG. 8(a), e.g., signal x may be assigned the alternating current signal);
a second end of the first switching transistor is coupled to a first end of the second switching transistor (FIG. 8(a), node Z);
the first enable signal is used to control the first switching transistor to be turned on and the second switching transistor to be turned off (FIG. 8(a), signal “sel bar”); and
the second enable signal is used to control the first switching transistor to be turned off and the second switching transistor to be turned on (FIG. 8(a), signal “sel”).
Mihara and Amini-Valashani together further teach a second end of the second switching transistor is coupled to the memory controller, and the second end of the second switching transistor is configured to receive the read/write pulse signal (Amini-Valashani signal y in FIG. 8(a), which may be assigned to Mihara read and write pulses generated by a controller in FIGS. 5A, 5C);
Regarding claim 17, Mariani as modified by Yan, Harms, Mihara, and Amini-Valashani teaches the limitations of claim 16.
Mariani further teaches the alternating current signal generator is further configured to generate a second alternating current signal (FIG. 4, e.g., 405).
Mihara further teaches the signal control device is further configured to:
superimpose the second alternating current signal and the read/write pulse signal (FIG. 23B shows a pulse train superimposed on a DC level resulting from the circuit of FIG. 23A; Col. 12, ll. 37-50; see also FIG. 21A).
Mariani as modified by Yan, Mihara, and Amini-Valashani teaches input a superimposed signal to the plate line (specifically, Yan teaches in FIG. 4c the output of the transistor multiplexer is connected to the plate line).
Regarding claim 18, Mariani as modified by Yan, Harms, Mihara, and Amini-Valashani teaches the limitations of claim 17.
Mariani as modified by Yan, Harms, Mihara, and Amini-Valashani further teaches the memory controller is further configured to send a third enable signal to the signal control device in a read/write process of the ferroelectric memory cell, and the third enable signal is used to control the signal control device to input the second alternating current signal and the superimposed signal to the plate line (Mihara FIG. 23A, switch 11 controls superimposing signals 13’, 14’, and/or 15’ onto the plate line and may be implemented with additional control signals and transistors of Amini-Valashani).
Regarding claim 19, Mariani as modified by Yan, Harms, Mihara, and Amini-Valashani teaches the limitations of claim 17.
Mariani further teaches a frequency of the second alternating current signal is greater than a frequency of the read/write pulse signal (FIG. 4, 405 shows multiple periods of the alternating current signal within the period of a memory access (read/write) operation; ¶[0049]).
Mariani does not teach the range of an amplitude of the second alternating current signal is less than 1/2 of an amplitude of the read/write pulse signal. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A).
Allowable Subject Matter
14. Claims 8, 12, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
15. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 8, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein:
the signal control device further comprises a third switching transistor and a multiplier;
a first end of the third switching transistor is coupled to the alternating current signal generator, and the first end of the third switching transistor is configured to receive the second alternating current signal;
a second end of the third switching transistor is coupled to a first input end of the multiplier;
a second input end of the multiplier is coupled to the memory controller, and the second input end of the multiplier is configured to receive the read/write pulse signal; and
an output end of the multiplier is coupled to the plate line.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein:
the signal control device comprises a switching transistor and a multiplier;
a first end of the switching transistor is coupled to the alternating current signal generator, and the first end of the switching transistor is configured to receive the alternating current signal;
a second end of the switching transistor is coupled to a first input end of the multiplier;
a second input end of the multiplier is coupled to the memory controller, and the second input end of the multiplier is configured to receive the read/write pulse signal; and
an output end of the multiplier is coupled to the plate line.
Regarding claim 20, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein:
the signal control device further comprises a third switching transistor and a multiplier;
a first end of the third switching transistor is coupled to the alternating current signal generator, and the first end of the third switching transistor is configured to receive the second alternating current signal;
a second end of the third switching transistor is coupled to a first input end of the multiplier;
a second input end of the multiplier is coupled to the memory controller, and the second input end of the multiplier is configured to receive the read/write pulse signal; and
an output end of the multiplier is coupled to the plate line.
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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