DETAILED ACTION
Introduction
Claims 1-20 are pending. This Office action is in response to Application 18/949,085 filed on 11/15/2024.
Other Prior Art
Izenberg (US 11,121,915) teaches configuring a first FPGA-enabled compute instance to satisfy a first workload, and a second FPGA-enabled compute instance to satisfy a second workload. See fig. 13 and accompanying text.
Claim Rejections: 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-10, and 15-17 are rejected under 35 U.S.C. 103 because they are unpatentable over Guim Bernat (US 2019/0121671) in view of Nadathur (US 2022/0206864) and van Rooyen (US 2017/0270245).
Regarding claims 1, 8, and 15, Guim Bernat teaches a system comprising: a plurality of field programmable gate arrays (FPGAs); at least one memory having computer-readable instructions stored thereon; and at least one processor, the at least one processor being configured, in response to the computer-readable instructions, to: receive a first request from a first client subsystem, wherein the first request is configured to request performance of a first workload at a server subsystem (A client device such as a compute platform, data center, edge node, virtual machine, application, or software can submit a first request for performance of a workload by a resource of server system 304. See par. 15, 22), wherein the first request indicates a first constraint associated with the first client subsystem (The first request can specify client-side constraints such as source code or compiled bitstream, acceleration type, SLA requirements, model type, and performance requirements. See par. 31, 41); configure one or more first FPGAs of the plurality of FPGAs for servicing the first request, wherein the one or more first FPGAs are configured to be compatible with the first constraint associated with the first client subsystem for performing the workload (A load balancer receives the first request and selects a first FPGA from FPGA pool 208 based on the client-side constraints specified by the first request. See par. 18, 27. The system generates a bitstream compatible with the selected accelerator, translates source code if needed into a format acceptable to the selected accelerator, and provides the bitstream to the selected accelerator. See par. 34-46); receive a second request from a second client subsystem, wherein the second request is configured to request performance of a second workload (The server system may receive many requests from many different clients, including a second request from a second client. Se par. 11, 27; fig. 1), wherein the second request indicates a second constraint associated with the second client subsystem (Like the first request, the second request may specify client-side constraints. See par. 31, 41); and configure one or more second FPGAs of the plurality of FPGAs for servicing the second request, wherein the one or more second FPGAs are configured to be compatible with the second constraint associated with the second client subsystem for performing the workload (The load balancer receives the second request and selects a second FPGA from FPGA pool 208 based on the client-side constraints specified by the second request. See par. 18, 27. The system generates a bitstream compatible with the selected accelerator, translates source code if needed into a format acceptable to the selected accelerator, and provides the bitstream to the selected accelerator. See par. 34-46); and wherein the one or more first FPGAs and the one or more second FPGAs are configured to respectively process the first workload and the second workload in parallel (The reference discloses a pooled multi-FPGA architecture with FPGAs 1-N and multiple accelerator pools, all fabric-connected, available for use by multiple applications and clients. See par. 10, 18; figs. 1-2. It also teaches many requests from clients and scaling to absorb different loads. See par. 11-15. These paragraphs strongly suggest that different workload requests are dispatched to different selected FPGA resources from the pooled FPGA set, so the first and second workloads are respectively processed by different FPGA resources in parallel within the same pooled server-side fabric architecture).
However, Guim Bernat does not teach that the first and second constraints respectively comprise a first version associated with the first client subsystem and a second version associated with the second client subsystem. Nonetheless, Nadathur teaches initiating, by or on behalf of a software execution entity, a workload to be performed by an FPGA (See par. 11, 15, 19-20); selecting a device image configuration (i.e., FPGA configuration) based on metadata specifying a compatible software stack of the software execution entity (See par. 11, 21-22, 25, and 31-34); and configuring an FPGA with the selected device image configuration so that it is compatible with the software execution entity (See par. 8-9, 25-26, 31-32, and 57-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat so that so that resource selection is based not only on generic request parameters like accelerator type, SLA, and performance, but also on whether the selected FPGA / device image is compatible with the versioned software environment associated with the requesting client subsystem, because doing so would predictably improve workload placement, reduce failed executions and translation mismatches, and ensure that the selected FPGA image and host/software stack interoperate correctly before the workload is dispatched. Both Guim Bernat and Nadathur are in the same accelerator-scheduling space, both are directed to selecting/configuring heterogeneous compute resources for workloads, and Nadathur expressly identifies the compatibility problem that arises when software stacks and programmable-device images are incompatible.
Lastly, Guim Bernat and Nadathur does not teach that the first and second workloads respectively comprise a sequencing analysis of first sequencing data and second sequencing data. However, van Rooyen teaches a performing mapping, aligning, sorting, and/or variant call protocols on genetic sequence data using an FPGA. See par. 20 and 128-131.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat and Nadathur so that the first and second workloads respectively comprise a sequencing analysis of first and second sequencing data, because Guim Bernat teaches offloading compute-intensive workloads to an FPGA, and sequencing analysis is exactly the sort of compute-intensive workload suited for FPGA offload.
Regarding claims 2, 9, and 16, Guim Bernat, Nadathur, and van Rooyen teach the system of claim 1, wherein the one or more first FPGAs and the one or more second FPGAs are each configured with different bioinformatics components to perform different versions of a same sequencing task or to perform different sequencing tasks (van Rooyen teaches performing different sequencing tasks on FPGAs having different modules/subsets of processing engines. See par. 12-16, 18-19, 35-36. Thus, van Rooyen suggests further modifying the system of Guim Bernat, Nadathur, and van Rooyen so that the first FPGA is configured with a first set of sequencing-oriented components, and the second FPGA is configured with a second set of sequencing-oriented components, because doing so allows the system to tailor separate FPGAs to separate sequencing-analysis jobs).
Regarding claims 3, 10, and 17, Guim Bernat, Nadathur, and van Rooyen teach the system of claim 2, wherein the sequencing task or the sequencing tasks comprise a mapping sequencing task, a variant calling sequencing task, or an aligning sequencing task (van Rooyen teaches mapping, aligning, and variant calling as genomics analysis functions performed by an FPGA. See par. 12-19, and 25-26. Thus, van Rooyen suggests further modifying the system of Guim Bernat, Nadathur, and van Rooyen so that mapping, aligning, and variant calling tasks are dispatched to selected FPGA resources that are configured with the corresponding task-specific bioinformatics logic, because doing so allows the system to increase throughput, reduce latency, and better utilize pooled accelerator infrastructure).
Claims 4-7, 11-14, and 18-20 are unpatentable over Guim Bernat, Nadathur, and van Rooyen, as applied to claims 1, 8, and 15 above, in further view of the non-patent literature entitled “Hardware Task Scheduling for Partially Reconfigurable FPGAs” (hereinafter, “Charitopoulos”).
Regarding claims 4, 11, and 18, Guim Bernat, Nadathur, and van Rooyen teach the system of claim 1, wherein the processor is further configured to: receive a third request from a third client subsystem (Guim Bernat teaches receiving a workload request from a client at a network/interface side of the system and passing that request to a scheduler for accelerator selection. That is enough to teach the basic concept of receiving a later, additional request from another client subsystem. The reference does not need to use the literal words “third request” to satisfy this limitation; a disclosure of repeated client workload requests is enough. See par. 31-34), wherein the third request is configured to request performance of sequencing analysis of third sequencing data at the server subsystem (van Rooyen teaches that the workload can be bioinformatics/genomics analysis on genetic sequence data, including a genomics analysis platform that performs sequence-analysis pipeline steps on such data. Guim Bernat supplies the server-side request/scheduling framework, i.e., a client request is received and scheduled to a selected compute/accelerator resource. Together, those references teach a request for sequencing analysis of sequencing data at a server-side system. See van Rooyen par. 20, 128-129; Guim Bernat, par. 31-34), wherein the third request indicates the first version that is also associated with the third client subsystem (Guim Bernat teaches that the request can carry a source-code version or bitstream version of the workload request. Nadathur teaches versioned software-stack compatibility and software execution entities such as applications, VMs, containers, and microservices, with compatibility defined in terms of permitted software-package versions and software-stack profiles. Together, those references teach a request with version-related information associated with the requesting software environment. See Guim Bernat, par. 34; Nadathur, par. 15, 21-22, and 34-37); and determine that the one or more first FPGAs are compatible with the first version that is associated with the third client subsystem (Nadathur teaches that metadata can define software/hardware compatibilities, that software-stack compatibility includes versioned profiles, and that the orchestrator can determine whether a specific FPGA/device image configuration is compatible with the relevant platform/software environment and can select a compatible image/device accordingly. See Nadathur par. 11, 31-34).
However, Guim Bernat, Nadathur, and van Rooyen do not teach wherein the one or more first FPGAs are configured to process the third sequencing data after the processing of the first request has completed. Nonetheless, Charitopoulos teaches that if a task cannot be served immediately, it is placed in a reservation queue for later configuration/execution until a reconfigurable region of an FPGA becomes available (See pg. 3, ln. 40–45); before loading a hardware task, the system checks whether it already resides in a reconfigurable region and can be reused, including where the already configured task is busy processing other data (See pg. 4, ln. 1–2); when a hardware task already exists due to a previous request, the scheduler evaluates reservation, immediate placement, and relocation, including when the existing task is busy executing (See pg. 4, ln. 24–33); when a task completes, the next dependent task becomes an arrived task, and the system checks completed and reserved tasks to decide what should execute next. See pg. 5, ln. 28–32; pg. 6, ln. 4–7. In other words, the system waits for completion of an existing task and reuses the already configured FPGA region when that yields better overall execution than reconfiguring another region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that the system waits for completion of the first request before processing the third sequencing data in the first FPGA, because doing so allows the system to reuse the existing configuration of the first FPGA to process the third sequencing data, thereby avoiding the need to configure a third FPGA to process the third sequencing data.
Regarding claims 5, 12, and 19, Guim Bernat, Nadathur, and van Rooyen teach the system of claim 1, wherein the processor is further configured to: receive a third request from a third client subsystem (Guim Bernat teaches that a client can request execution of a workload through an interface, and that a scheduler selects resources to execute workload requests. That is sufficient to teach receipt of an additional, later request from another client subsystem, even though the reference does not literally say “third request.” Guim Bernat, par. 30-31), wherein the third request is configured to request performance of sequencing analysis of third sequencing data at the server subsystem (van Rooyen teaches a platform for bioinformatics/genomics analysis on genetic sequence data, including a sequence analysis pipeline executed on FPGA-based hardware. Guim Bernat supplies the server-side request/scheduling framework that receives a request and routes it to a selected compute/accelerator resource. Together, they teach a request for sequencing analysis of sequencing data at a server-side system. See van Rooyen par. 20, 128-129; Guim Bernat, par. 30-31), and wherein the third request indicates a third version associated with the third client subsystem (Guim Bernat teaches that the request can include a source-code version or bitstream version of the workload request. Nadathur teaches versioned software-stack compatibility, including permitted software-package versions and version-sensitive software profiles for the environment in which a software execution entity operates. Together, they support a request that carries version-related information associated with the requesting software environment. See Guim Bernat, par. 34; Nadathur, par. 21-22, 34-38, and 50).
However, Guim Bernat, Nadathur, and van Rooyen do not teach determine that the first FPGA and the second FPGA are each configured with versions that are incompatible with the third version associated with the third client subsystem; and after the one or more of the first FPGAs or the one or more of the second FPGAs finish processing, configure the one or more of the first FPGAs or the one or more of the second FPGAs that finish processing with bioinformatics components that are compatible with the third version associated with the third client subsystem for servicing the third request. Nonetheless, Charitopoulos teaches that if a task cannot be served immediately, it is placed in a reservation queue for later configuration/execution until a reconfigurable region becomes available (pg. 3, ln 40–45); before loading a hardware task, the system checks whether it already resides in a reconfiguration region and can be reused, including when the already configured task is busy processing other data (pg. 4, ln. 1–2); when a hardware task already exists due to a previous request, the scheduler evaluates reservation, immediate placement, and relocation, including when the existing task is busy executing (pg. 4, ln 24–33); and to execute a hardware task, the system issues a reconfiguration command and configures the FPGA with the corresponding bitstream, after which execution begins (pg. 10, ln. 5–13). In other words, when existing FPGA resources are not immediately suitable/available for the later request, the system can wait until one finishes, then reconfigure or reuse that FPGA region for the later-arriving task.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that the system determines that the first and second FPGAs are not suitable for processing the third request, and reconfigures the first FPGA or the second FPA to perform the third request once the first FPGA is finished processing the first request or the second FPGA is finished processing the second request, because doing so allows an FPGA to be reconfigured to perform a new request once it has finished performing an existing request.
Regarding claims 6 and 13, Guim Bernat, Nadathur, and van Rooyen teach the system of claim 1, wherein the processor is further configured to configure each of the one or more first FPGAs and the one or more second FPGAs with a respective bitstream (Guim Bernat teaches selecting one or more accelerator resources that meet the workload requirements, generating a bitstream compatible with the selected accelerator, and providing that bitstream to the selected accelerator for execution; it also contemplates single or multiple accelerators. See Guim Bernat, par. 33-36).
However, Guim Bernat, Nadathur, and van Rooyen do not teach that the bitstream is a partially reconfigurable bitstream. Nonetheless, Charitopoulos teaches that the system operates in partially reconfigurable systems with FPGAs and schedules hardware tasks on reconfigurable regions; hardware tasks are implemented as reconfigurable modules; and the input includes the available task mappings, i.e., bitstreams for the different implementations of each hardware task. It also teaches multiple bitstreams per task, where different implementations provide the same functionality but may target different reconfigurable regions or be differently optimized. See pg. 1, ln. 11–21; pg. 3, ln. 8–17 and 35–39; pg. 5, ln. 19–24.
It would have been obvious to one of ordinary skill in the art to modify the system of Guim Bernat, Nadathur, and van Rooyen so that the bitstreams are partially reconfigurable bitstreams because doing so reduces reconfiguration overhead, increases deployment flexibility, and improves FPGA-area utilization.
Regarding claims 7, 14, and 20, Guim Bernat, Nadathur, van Rooyen, and Charitopoulos teach the system of claim 6, wherein the respective partially reconfigurable bitstreams each comprise different images for performing a same or different form of sequencing analysis (Guim Bernat teaches respective bitstreams for first and second selected FPGAs. See par. 33-36. Nadathur teaches that those bitstreams are different device images/image configurations selected for function/compatibility. See par. 11, 31-34, 47-50. van Rooyen teaches that those images perform sequencing analysis, including different forms such as mapping, aligning, and variant calling. See par. 35-36, 128-129. Charitopoulos teaches partially reconfigurable FPGA systems, where hardware tasks are implemented as reconfigurable modules stored in a bitstream repository; and it expressly teaches multiple bitstreams per task, where all versions implement the same functionality but may target different reconfigurable regions or be differently optimized. See pg. 1, ln. 11-21; pg. 3, ln. 8-17 and 35-39; pg. 5, ln. 19-24. Thus, Charitopoulos suggests further modifying the system of Guim Bernat, Nadathur, van Rooyen, and Charitopoulos so that each partially reconfigurable bitstream comprises different images for performing a same or different form of sequencing analysis, because doing so allows different sequencing-analysis images – whether the same function or different sequencing functions – to be loaded efficiently as needed).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew Georgandellis whose telephone number is 571-270-3991. The examiner can normally be reached on Monday through Friday, 7:30-5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tonia Dollinger, can be reached on 571-272-4170. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW C GEORGANDELLIS/Primary Examiner, Art Unit 2459
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