DETAILED ACTION
Status of the Claims
Claims 1-20 are pending. No claims have been canceled. No claims have been withdrawn. No claims are objected to. No claims have been amended. No claims are allowable. Claims 1-20 are rejected under 35 U.S.C. § 103.
Response to Arguments
The arguments of Applicant’s representative filed September 11, 2026 have been fully considered.
Rejection of Claims 1, 8, and 15 under 35 U.S.C. § 103 over Guim Bernat, Nadathur, and van Rooyen.
Applicant’s representative argues that Guim Bernat does not teach or suggest first and second requests for sequencing analysis that indicate versions associated with the client subsystems, and therefore cannot teach or suggest FPGAs configured for servicing those requests, because its load balancer selects FPGAs based on other client-side constraints. However, Examiner respectfully disagrees. The rejection does not rely on Guim Bernat for the version indication or the sequencing analysis, which Nadathur and van Rooyen supply. It relies on Guim Bernat for receiving client workload requests ([0030]-[0031]) and configuring FPGAs to service them, which does not depend on what the requests indicate: for the first request, scheduler (414) selects an accelerator, bitstream generator (418) generates a bitstream executable by it, and network interface (410) provides the bitstream to it ([0031], [0034], and [0036]); for the second, load balancer (312) selects an accelerator and bitstream generator (310) generates a bitstream registered for execution on it ([0026]-[0027]).
Applicant’s representative further argues that Nadathur does not teach or suggest requests for performing sequencing analysis and instead discloses configuring an FPGA with a device image based on a compatible software stack. However, Examiner respectfully disagrees. Nadathur is not relied on for sequencing analysis, and its compatible-software-stack configuration is the teaching the rejection uses. Claim 1 does not require a request to state a version number: the Specification describes a request that “may comprise a product identifier, a version identifier, and/or other information associated with the client subsystem from which the request is received,” from which the monitor subsystem determines the version of the sequencing application operating on the client subsystem ([0056]). In Nadathur, each workload’s pods and manifests request node labels derived from software-stack compatibility metadata that identifies compatible software profiles by minimum and maximum software-package versions, so each request indirectly indicates its requesting entity’s software-stack version requirement ([0034], [0048], [0053], and [0091]), and a device image compatible with that requirement is selected by version range for the device that executes it ([0031], [0058]-[0059], and [0093]). Modifying Guim Bernat in this way prevents either client workload from being dispatched to an incompatible FPGA image.
Applicant’s representative also contends that van Rooyen’s disclosure of performing sequencing analysis using FPGAs does not cure these deficiencies. However, Examiner respectfully disagrees. As explained above, Guim Bernat and Nadathur supply the features said to be missing, and van Rooyen is relied on only for the sequencing analysis, the sequencing data, and, in claim 15, the bioinformatics components: its FPGA processing engines, arranged as hardwired digital logic circuits, perform sequence-analysis functions, including mapping, aligning, and variant calling ([0026]), and its accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]). Because van Rooyen reports this processing as magnitudes faster than standard pipelines implemented in software alone, giving both clients’ sequencing analysis that acceleration increases throughput across multiple sequencing-analysis requests. An argument that each reference lacks a feature the rejection credits to another does not show nonobviousness.
Rejection of Claims 2, 3, 9, 10, 16, and 17 under 35 U.S.C. § 103 over Guim Bernat, Nadathur, and van Rooyen.
Applicant’s representative argues that claim 2 overcomes the art for the reasons given as to claim 1. However, this argument is not persuasive for the reasons provided above with respect to claim 1.
Rejection of Claims 4-7, 11-14, and 18-20 under 35 U.S.C. § 103 over Guim Bernat, Nadathur, van Rooyen, and Charitopoulos.
Applicant’s representative argues that claim 4 overcomes the art for the reasons given as to claim 1. However, this argument is not persuasive for the reasons provided above with respect to claim 1.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-10, and 15-17 are rejected under 35 U.S.C. § 103 as being unpatentable over Guim Bernat (US 2019/0121671 A1; “Guim Bernat”) in further view of Nadathur et al. (US 2022/0206864 A1; “Nadathur”) and van Rooyen et al. (US 2017/0270245 A1; “van Rooyen”).
Regarding claims 1 and 8, Guim Bernat teaches or suggests a system comprising:
a plurality of field programmable gate arrays (FPGAs). Pool (208) contains a plurality of field programmable gate arrays ([0018]).
at least one memory having computer-readable instructions stored thereon.
at least one processor, the at least one processor being configured, in response to the computer-readable instructions, to:
receive a first request from a first client subsystem. Client (402) may be an application, virtual machine, or other software and provides a workload request to interface (412) for accelerator scheduling ([0030]-[0031]).
wherein the first request is configured to request performance of [analysis] of first [data] at a server subsystem. Platform (302) requests performance of a workload by system (304), which can be implemented in a host platform having a CPU, memory, storage, and interconnect ([0022], [0028]).
configure one or more first FPGAs of the plurality of FPGAs for servicing the first request. Scheduler (414) selects an accelerator for the client workload request, bitstream generator (418) generates a bitstream executable by the selected accelerator, and network interface (410) provides the bitstream to the selected accelerator ([0031], [0034], and [0036]).
wherein the one or more first FPGAs are configured … for performing the [analysis] of the first [data]. The selected accelerator provides a result after executing the bitstream ([0037]).
receive a second request from a second client subsystem. The platform makes compute and acceleration resources available to applications 1 and 2 and to other software and clients ([0010]), and software clients provide workload requests for accelerator scheduling ([0030]-[0031]).
wherein the second request is configured to request performance of [analysis] of second [data] at the server subsystem. Platform (302) requests performance of a workload by system (304) ([0022]).
configure one or more second FPGAs of the plurality of FPGAs for servicing the second request. Load balancer (312) selects a suitable accelerator for the workload request, and bitstream generator (310) generates a bitstream executable by that accelerator, which is registered for execution on it ([0026]-[0027]).
wherein the one or more second FPGAs are configured … for performing the [analysis] of the second [data]. The selected accelerator provides a result after executing the bitstream ([0037]).
wherein the one or more first FPGAs and the one or more second FPGAs are configured to respectively process the first [data] and the second [data] in parallel. The architecture makes pool (208) FPGAs available to applications 1 and 2 and to other software and clients, and load balancer (312) selects suitable accelerators using load and estimated time to availability, choosing among several qualifying accelerators by round robin, which, with the stated low-latency and load-scaling objectives, suggests dispatching separate client workloads to respective available FPGAs for parallel processing ([0010], [0011], [0018], and [0027]).
However, Guim Bernat does not teach or suggest, but Nadathur teaches or suggests, wherein the first request indicates a first version associated with the first client subsystem. A workload request indirectly indicates its requesting entity’s software-stack version requirement: workloads are initiated at the request of software execution entities, and their pods and manifests request node labels derived from software-stack compatibility metadata that identifies compatible software profiles by minimum and maximum software-package versions ([0034], [0048], [0053], and [0091]).
wherein the one or more first FPGAs are configured to be compatible with the first version associated with the first client subsystem. A device image compatible with the workload’s software-stack version requirement is selected by version range, and the device executing that image is selected ([0031], [0058]-[0059], and [0093]).
wherein the second request indicates a second version associated with the second client subsystem. Another software execution entity’s workload request likewise indicates that entity’s software-stack version requirement through the node labels its pods and manifests request ([0034], [0048], [0053], and [0091]).
wherein the one or more second FPGAs are configured to be compatible with the second version associated with the second client subsystem. A device image compatible with that workload’s software-stack version requirement is likewise selected by version range, and the device executing it is selected ([0031], [0058]-[0059], and [0093]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat so that the first client workload request indicates the software-stack version requirement of its requesting software execution entity, the FPGA selected for that request executes a device image selected as compatible with that requirement, the second client workload request indicates its own requesting entity’s software-stack version requirement, and the FPGA selected for the second client workload request executes a device image likewise selected as compatible with that entity’s requirement, as taught by Nadathur, because doing so prevents either client workload from being dispatched to an incompatible FPGA image.
Further, the combination of Guim Bernat and Nadathur does not teach or suggest, but van Rooyen teaches or suggests, that the analysis requested by the first request is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling, on genetic data ([0026]).
The first data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
The analysis requested by the second request is sequencing analysis. Accelerated processing engines perform secondary DNA/RNA sequencing analysis, including mapping, aligning, sorting, and variant calling ([0129]).
The second data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat and Nadathur so that the first client workload request requests sequence-analysis functions, including mapping, aligning, and variant calling, the first client workload request’s data is DNA/RNA sequencing data, the second client workload request requests secondary DNA/RNA sequencing analysis, and the second client workload request’s data is also DNA/RNA sequencing data, as taught by van Rooyen, because doing so gives both clients’ sequencing analysis the acceleration van Rooyen reports as magnitudes faster than standard pipelines implemented in software alone, increasing throughput across multiple sequencing-analysis requests.
Regarding claims 2 and 9, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 1, and van Rooyen further teaches or suggests wherein the one or more first FPGAs and the one or more second FPGAs are each configured with different bioinformatics components to perform different versions of a same sequencing task or to perform different sequencing tasks. FPGA integrated circuits are programmable by firmware for genomics-analysis functions, and different pipeline tasks are assigned to distinct hardwired-logic subsets: a first subset maps reads, a second aligns them, and further subsets sort and call variants, satisfying the recited alternative of different bioinformatics components performing different sequencing tasks ([0017]-[0019], [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the pooled FPGA resources are configured with van Rooyen’s distinct hardwired-logic subsets for different genomics-analysis pipeline tasks, because doing so allows the pooled accelerator system to match each client workload to the processing functionality it requires while retaining the pool’s ability to service multiple requests.
Regarding claims 3 and 10, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 2, and van Rooyen further teaches or suggests wherein the sequencing task or the sequencing tasks comprise a mapping sequencing task, a variant calling sequencing task, or an aligning sequencing task. The FPGA processing engines perform mapping, aligning, and variant calling operations on genetic data ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the sequencing-analysis processing engines perform mapping, aligning, or variant calling as taught by van Rooyen, because doing so places those secondary-analysis steps on the pooled FPGAs and reduces processing time for the requested sequencing workloads.
Regarding claim 15, Guim Bernat teaches or suggests a system comprising:
a plurality of field programmable gate arrays (FPGAs). Pool (208) contains a plurality of field programmable gate arrays ([0018]).
at least one memory having computer-readable instructions stored thereon.
at least one processor, the at least one processor being configured, in response to the computer-readable instructions, to.
receive a first request from a first client subsystem. Client (402) may be an application, virtual machine, or other software and provides a workload request to interface (412) for accelerator scheduling ([0030]-[0031]).
wherein the first request is configured to request performance of [analysis] of first [data] at a server subsystem. Platform (302) requests performance of a workload by system (304), which can be implemented in a host platform having a CPU, memory, storage, and interconnect ([0022], [0028]).
configure one or more first FPGAs of the plurality of FPGAs with first [components] for servicing the first request. Scheduler (414) selects an accelerator for the client workload request, and bitstream generator (418) generates, and network interface (410) provides, the bitstream configuring the selected accelerator for that request ([0031], [0034], and [0036]).
receive a second request from a second client subsystem. The platform makes compute and acceleration resources available to applications 1 and 2 and to other software and clients ([0010]), and software clients provide workload requests for accelerator scheduling ([0030]-[0031]).
wherein the second request is configured to request performance of [analysis] of second [data] at the server subsystem. Platform (302) requests performance of a workload by system (304) ([0022]).
configure one or more second FPGAs of the plurality of FPGAs with second [components] for servicing the second request. Load balancer (312) selects a suitable accelerator for the workload request, and bitstream generator (310) generates the bitstream configuring that accelerator, which is registered for execution on it ([0026]-[0027]).
wherein the one or more first FPGAs and the one or more second FPGAs are configured to respectively process the first [data] and the second [data] in parallel. The architecture makes pool (208) FPGAs available to applications 1 and 2 and to other software and clients, and load balancer (312) selects suitable accelerators using load and estimated time to availability, choosing among several qualifying accelerators by round robin, which, with the stated low-latency and load-scaling objectives, suggests dispatching separate client workloads to respective available FPGAs for parallel processing ([0010], [0011], [0018], and [0027]).
However, Guim Bernat does not teach or suggest, but Nadathur teaches or suggests, wherein the first request indicates a first version associated with the first client subsystem. A workload request indirectly indicates its requesting entity’s software-stack version requirement: workloads are initiated at the request of software execution entities, and their pods and manifests request node labels derived from software-stack compatibility metadata that identifies compatible software profiles by minimum and maximum software-package versions ([0034], [0048], [0053], and [0091]).
wherein the first [components] are configured to be compatible with the first version associated with the first client subsystem. The device image carrying the components is selected by version range as compatible with the workload’s software-stack version requirement, and the device executing it is selected ([0031], [0058]-[0059], and [0093]).
wherein the second request indicates a second version associated with the second client subsystem. Another software execution entity’s workload request likewise indicates that entity’s software-stack version requirement through the node labels its pods and manifests request ([0034], [0048], [0053], and [0091]).
wherein the second [components] are configured to be compatible with the second version associated with the second client subsystem. The device image carrying the second components is likewise selected as compatible with that workload’s software-stack version requirement, and the device executing it is selected ([0031], [0058]-[0059], and [0093]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat so that the first client workload request indicates the software-stack version requirement of its requesting software execution entity, the device image carrying the components configured for that request is selected as compatible with that requirement, the second client workload request indicates its own requesting entity’s software-stack version requirement, and the device image carrying the components configured for the second client workload request is likewise selected as compatible with that entity’s requirement, as taught by Nadathur, because doing so prevents either client workload from being dispatched to an incompatible FPGA image.
Further, the combination of Guim Bernat and Nadathur does not teach or suggest, but van Rooyen teaches or suggests, that the analysis requested by the first request is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling, on genetic data ([0026]).
The first data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
The first components are bioinformatics components. FPGA processing engines are arranged as hardwired digital logic circuits for sequence-analysis functions, including mapping, aligning, and variant calling ([0026]).
wherein the first bioinformatics components are configured … for performing the sequencing analysis of the first sequencing data. The FPGA processing engines perform sequence-analysis functions on genetic data, and the accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0026], [0129]).
The analysis requested by the second request is sequencing analysis. Accelerated processing engines perform secondary DNA/RNA sequencing analysis, including mapping, aligning, sorting, and variant calling ([0129]).
The second data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
The second components are bioinformatics components. FPGA processing engines are arranged as hardwired digital logic circuits for sequence-analysis functions ([0026]).
wherein the second bioinformatics components are configured … for performing the sequencing analysis of the second sequencing data. The FPGA processing engines perform sequence-analysis functions, including secondary DNA/RNA sequencing analysis ([0026], [0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat and Nadathur so that the first client workload request requests sequence-analysis functions, including mapping, aligning, and variant calling, the first client workload request’s data is DNA/RNA sequencing data, the FPGA selected for the first client workload request is configured with van Rooyen’s FPGA bioinformatics processing engines, those first engines perform the first workload’s sequencing analysis, the second client workload request requests secondary DNA/RNA sequencing analysis, the second client workload request’s data is also DNA/RNA sequencing data, the FPGA selected for the second client workload request is likewise configured with FPGA bioinformatics processing engines, and those second engines perform the second workload’s sequencing analysis, because doing so gives both clients’ sequencing analysis the acceleration van Rooyen reports as magnitudes faster than standard pipelines implemented in software alone, increasing throughput across multiple sequencing-analysis requests.
Regarding claim 16, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 15, and van Rooyen further teaches or suggests wherein the one or more first bioinformatics components and the one or more second bioinformatics components comprise different versions of a same bioinformatics component for performing a sequencing task or different components for performing different sequencing tasks. Distinct mapping, aligning, and variant-call modules may be formed from separate subsets of processing engines; the limitation is recited in the alternative, and different components performing different sequencing tasks satisfy it ([0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the bioinformatics components used for separate client workload requests are different processing-engine modules, each for a sequencing task, together performing different sequencing tasks as taught by van Rooyen, because doing so allows the pooled FPGA resources to execute different requested sequencing tasks at the same time, increasing throughput across the client workloads.
Regarding claim 17, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 16, and van Rooyen further teaches or suggests wherein the sequencing task or the sequencing tasks comprise a mapping sequencing task, a variant calling sequencing task, or an aligning sequencing task. The FPGA processing engines perform mapping, aligning, and variant calling operations on genetic data ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the sequencing-analysis processing engines perform mapping, aligning, or variant calling as taught by van Rooyen, because doing so places those secondary-analysis steps on the pooled FPGAs and reduces processing time for the requested sequencing workloads.
Claims 4-7, 11-14, and 18-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Guim Bernat, Nadathur, and van Rooyen, as applied to claims 1, 8, and 15 above, in further view of the non-patent literature entitled “Hardware Task Scheduling for Partially Reconfigurable FPGAs” (“Charitopoulos”).
Regarding claims 4 and 11, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 1, and Guim Bernat further teaches or suggests wherein the processor is further configured to receive a third request from a third client subsystem. Software clients provide workload requests through interface (412) for accelerator scheduling ([0030]-[0031]).
Guim Bernat further teaches or suggests wherein the third request is configured to request performance of [analysis] of third [data] at the server subsystem. Platform (302) requests performance of a workload by system (304) ([0022]).
Nadathur further teaches or suggests wherein the third request indicates the first version that is also associated with the third client subsystem. A later workload’s request for the same version-range label as an earlier request indirectly indicates the same software-stack version requirement: workloads are initiated at the request of software execution entities, and pods and manifests, including multi-pod deployments, request node labels derived from software-stack compatibility metadata for compatibility-based placement ([0034], [0048], [0053], and [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request indicates the same software-stack version requirement as the earlier request as taught by Nadathur, because doing so permits reuse of a compatible FPGA configuration for another client software environment requiring that version.
Nadathur further teaches or suggests wherein the processor is further configured to determine that the one or more first FPGAs are compatible with the first version that is associated with the third client subsystem. Compatibility of the prevailing device-image configuration, here the first FPGA’s configuration, with the software-stack version requirement indicated by the third request is determined using software-stack version ranges ([0032], [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the scheduler applies the software-stack version compatibility determination for the later request to the prevailing device-image configuration of the pooled FPGA that serviced the earlier request as taught by Nadathur, because doing so lets the later request reuse that existing configuration instead of waiting for another FPGA to be reconfigured.
van Rooyen further teaches or suggests that the analysis requested by the third request is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling, on genetic data ([0026]).
van Rooyen further teaches or suggests that the third data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request requests sequence-analysis functions, including mapping, aligning, and variant calling, and the later client workload request’s data is DNA/RNA sequencing data, as taught by van Rooyen, because doing so gives the later client’s sequencing analysis the acceleration van Rooyen reports as magnitudes faster than standard pipelines implemented in software alone, reducing sequencing-workload processing time.
However, the combination of Guim Bernat, Nadathur, and van Rooyen does not teach or suggest wherein the one or more first FPGAs are configured to process the third [data] after the processing of the first request has completed. Nonetheless, Charitopoulos teaches or suggests reserving an incoming hardware task for later start on a previously placed core and starting reserved tasks once the executing task completes (pg. 4, lines 34-43; pg. 6, lines 4-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later sequencing workload executes on the previously configured FPGA region after the earlier task completes as taught by Charitopoulos, because doing so reuses an FPGA already configured for the requested version, avoiding the reconfiguration overhead of preparing another pooled FPGA for the later request.
Regarding claims 5 and 12, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 1, and Guim Bernat further teaches or suggests wherein the processor is further configured to receive a third request from a third client subsystem. Software clients provide workload requests through interface (412) for accelerator scheduling ([0030]-[0031]).
Guim Bernat further teaches or suggests wherein the third request is configured to request performance of [analysis] of third [data] at the server subsystem. Platform (302) requests performance of a workload by system (304) ([0022]).
Nadathur further teaches or suggests wherein the third request indicates a third version associated with the third client subsystem. A later workload’s request for a different version-range label (e.g., Centos 7.6 onward rather than Centos 7.1-7.5) indirectly indicates a different software-stack version requirement ([0034], [0048], [0053], and [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request indicates a different software-stack version requirement as taught by Nadathur, because doing so lets the pooled scheduler detect that the later request cannot run on either occupied FPGA image, so the request is not dispatched to an incompatible configuration.
Nadathur further teaches or suggests wherein the processor is further configured to determine that the first FPGA and the second FPGA are each configured with versions that are incompatible with the third version associated with the third client subsystem. Software-stack changes can make prevailing device-image configurations incompatible, and compatibility with them is determined using software-stack version ranges; applied to both occupied FPGAs, this identifies when neither configuration supports the third request’s version requirement ([0008], [0032], and [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the scheduler determines compatibility of each occupied FPGA device-image configuration with the later request’s software-stack version and identifies when both are incompatible as taught by Nadathur, because doing so prevents dispatch of the later sequencing workload to an incompatible FPGA image.
Nadathur further teaches or suggests the [components] are compatible with the third version associated with the third client subsystem. A device is reimaged with a device image configuration chosen as compatible with the new software-stack version requirement; applied to the image carrying the bioinformatics processing engines configured for the third request, those components are compatible with the third version ([0031]-[0032], [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the device image carrying the bioinformatics processing engines configured for the later request is compatible with the workload software-stack version as taught by Nadathur, because doing so prevents the later sequencing workload from being dispatched to a configuration incompatible with the requesting software environment.
van Rooyen further teaches or suggests that the analysis requested by the third request is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling, on genetic data ([0026]).
van Rooyen further teaches or suggests that the third data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request requests sequence-analysis functions, including mapping, aligning, and variant calling, and the later client workload request’s data is DNA/RNA sequencing data, as taught by van Rooyen, because doing so gives the later client’s sequencing analysis the acceleration van Rooyen reports as magnitudes faster than standard pipelines implemented in software alone, reducing sequencing-workload processing time.
van Rooyen further teaches or suggests that the components are bioinformatics components. FPGA hardwired digital logic is arranged as processing engines for sequence-analysis functions, including mapping, aligning, and variant calling ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the FPGA servicing the later request is configured with van Rooyen’s hardwired digital logic arranged as processing engines for sequence-analysis functions, because doing so performs the later request’s sequence-analysis functions in FPGA hardware rather than software, reducing its processing time.
However, the combination of Guim Bernat, Nadathur, and van Rooyen does not teach or suggest wherein the processor is further configured to, after the one or more of the first FPGAs or the one or more of the second FPGAs finish processing, configure the one or more of the first FPGAs or the one or more of the second FPGAs that finish processing with [components] … for servicing the third request. Nonetheless, Charitopoulos teaches or suggests reserving a hardware task when no reconfigurable region is available, so that it waits for later configuration and execution, and checking after each task completes whether reserved tasks should start (pg. 3, lines 41-43; pg. 6, lines 4-7). In the section 4 example, task T3 can be loaded only on reconfigurable region RR2 and is reserved; fig. 4 shows RR2 reconfigured for T3 at t=14, when the task executing there completes (pg. 8, lines 21-25; fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that a reserved hardware task is configured for later execution on a reconfigurable region after the executing task completes as taught by Charitopoulos, because doing so allows a suitable FPGA region to be reconfigured with a compatible configuration for the waiting request as soon as it becomes available, reducing wait time and improving utilization of the pooled FPGA resources.
Regarding claims 6 and 13, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 1, and Guim Bernat further teaches or suggests wherein the processor is further configured to configure each of the one or more first FPGAs and the one or more second FPGAs with a respective [bitstream]. Bitstream generator (418) generates a bitstream compatible with each selected accelerator, and network interface (410) provides it to that accelerator, so each of the separately selected first and second FPGAs is configured with its own bitstream ([0034], [0036]).
However, the combination of Guim Bernat, Nadathur, and van Rooyen does not teach or suggest that each respective bitstream is a partially reconfigurable bitstream. Nonetheless, Charitopoulos teaches or suggests hardware tasks implemented as reconfigurable modules, stored in a bitstream repository and loaded into reconfigurable regions, each hardware task having a hardware version as partial bitstreams that are loaded by partial reconfiguration of the FPGA (pg. 3, lines 13-17; pg. 9, lines 32-33, 37-38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that the generated bitstreams implement Charitopoulos’s reconfigurable modules for execution on reconfigurable regions of an FPGA, because doing so permits a reconfigurable FPGA region to receive a new sequencing-analysis configuration without reconfiguring the whole device.
Regarding claims 7 and 14, the combination of Guim Bernat, Nadathur, van Rooyen, and Charitopoulos teaches or suggests the system of claim 6, and Guim Bernat further teaches or suggests wherein the respective [bitstreams] each comprise different images. Bitstream generator (418) generates for each selected accelerator a bitstream compatible with that accelerator from its workload request, and a workload’s bitstream can be translated into a different format for another accelerator, so the respective bitstreams of the separately selected first and second FPGAs carry different images ([0016], [0034]).
Guim Bernat further teaches or suggests the different images for performing a same or different form of [analysis]. An image-detection workload can be executed from an FPGA-accepted bitstream or, after translation, on another accelerator, so different images perform the same form of analysis; the limitation is recited in the alternative, and the same-form alternative satisfies it ([0016]).
van Rooyen further teaches or suggests that the analysis is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, van Rooyen, and Charitopoulos so that the different images implement van Rooyen’s sequence-analysis functions, including mapping, aligning, and variant calling, because doing so lets the scheduler dispatch a sequencing workload to whichever pooled FPGA can load an image for it, keeping the workload FPGA-accelerated and reducing its completion time.
Regarding claim 18, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 15, and Guim Bernat further teaches or suggests wherein the processor is further configured to receive a third request from a third client subsystem. Software clients provide workload requests through interface (412) for accelerator scheduling ([0030]-[0031]).
Guim Bernat further teaches or suggests wherein the third request is configured to request performance of [analysis] of third [data] at the server subsystem. Platform (302) requests performance of a workload by system (304) ([0022]).
Nadathur further teaches or suggests wherein the third request indicates the first version that is also associated with the third client subsystem. A later workload’s request for the same version-range label as an earlier request indirectly indicates the same software-stack version requirement: workloads are initiated at the request of software execution entities, and pods and manifests, including multi-pod deployments, request node labels derived from software-stack compatibility metadata for compatibility-based placement ([0034], [0048], [0053], and [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request indicates the same software-stack version requirement as the earlier request as taught by Nadathur, because doing so permits reuse of a compatible bioinformatics configuration for another client software environment requiring that version.
Nadathur further teaches or suggests wherein the processor is further configured to determine that the first [components] are compatible with the first version that is associated with the third client subsystem. Compatibility of the prevailing device-image configuration carrying the first bioinformatics components with the software-stack version requirement indicated by the third request is determined using software-stack version ranges ([0032], [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the scheduler applies the software-stack version compatibility determination for the later request to the prevailing device-image configuration carrying the bioinformatics processing engines configured for the earlier request as taught by Nadathur, because doing so lets the later request reuse those existing bioinformatics components instead of waiting for another FPGA to be reconfigured.
van Rooyen further teaches or suggests that the analysis requested by the third request is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling, on genetic data ([0026]).
van Rooyen further teaches or suggests that the third data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request requests sequence-analysis functions, including mapping, aligning, and variant calling, and the later client workload request’s data is DNA/RNA sequencing data, as taught by van Rooyen, because doing so gives the later client’s sequencing analysis the acceleration van Rooyen reports as magnitudes faster than standard pipelines implemented in software alone, reducing sequencing-workload processing time.
However, the combination of Guim Bernat, Nadathur, and van Rooyen does not teach or suggest wherein the one or more first FPGAs are configured to process the third [data] after the processing of the first request has completed. Nonetheless, Charitopoulos teaches or suggests reserving an incoming hardware task for later start on a previously placed core and starting reserved tasks once the executing task completes (pg. 4, lines 34-43; pg. 6, lines 4-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later sequencing workload executes on the previously configured FPGA region after the earlier task completes as taught by Charitopoulos, because doing so reuses an FPGA already configured for the requested version, avoiding the reconfiguration overhead of preparing another pooled FPGA for the later request.
Regarding claim 19, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 15, and Guim Bernat further teaches or suggests wherein the processor is further configured to receive a third request from a third client subsystem. Software clients provide workload requests through interface (412) for accelerator scheduling ([0030]-[0031]).
Guim Bernat further teaches or suggests wherein the third request is configured to request performance of [analysis] of third [data] at the server subsystem. Platform (302) requests performance of a workload by system (304) ([0022]).
Nadathur further teaches or suggests wherein the third request indicates a third version associated with the third client subsystem. A later workload’s request for a different version-range label (e.g., Centos 7.6 onward rather than Centos 7.1-7.5) indirectly indicates a different software-stack version requirement ([0034], [0048], [0053], and [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request indicates a different software-stack version requirement as taught by Nadathur, because doing so lets the pooled scheduler detect that the later request cannot run on either occupied bioinformatics configuration, so the request is not dispatched to an incompatible configuration.
Nadathur further teaches or suggests wherein the processor is further configured to determine that the first [components] and the second [components] are each configured with versions that are incompatible with the third version associated with the third client subsystem. Software-stack changes can make prevailing device-image configurations incompatible, and compatibility with them is determined using software-stack version ranges; applied to the configurations carrying the first and second bioinformatics components, this identifies when neither supports the third request’s version requirement ([0008], [0032], and [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the scheduler determines compatibility of each occupied device-image configuration carrying bioinformatics processing engines with the later request’s software-stack version and identifies when both are incompatible as taught by Nadathur, because doing so prevents dispatch of the later sequencing workload to incompatible bioinformatics components.
Nadathur further teaches or suggests the [components] are compatible with the third version associated with the third client subsystem. A device is reimaged with a device image configuration chosen as compatible with the new software-stack version requirement; applied to the image carrying the bioinformatics processing engines configured for the third request, those components are compatible with the third version ([0031]-[0032], [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the device image carrying the bioinformatics processing engines configured for the later request is compatible with the workload software-stack version as taught by Nadathur, because doing so prevents the later sequencing workload from being dispatched to a configuration incompatible with the requesting software environment.
van Rooyen further teaches or suggests that the analysis requested by the third request is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling, on genetic data ([0026]).
van Rooyen further teaches or suggests that the third data is sequencing data. The accelerated platform performs secondary analysis of DNA/RNA sequencing data ([0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the later client workload request requests sequence-analysis functions, including mapping, aligning, and variant calling, and the later client workload request’s data is DNA/RNA sequencing data, as taught by van Rooyen, because doing so gives the later client’s sequencing analysis the acceleration van Rooyen reports as magnitudes faster than standard pipelines implemented in software alone, reducing sequencing-workload processing time.
van Rooyen further teaches or suggests that the components are bioinformatics components. FPGA hardwired digital logic is arranged as processing engines for sequence-analysis functions, including mapping, aligning, and variant calling ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the FPGA servicing the later request is configured with van Rooyen’s hardwired digital logic arranged as processing engines for sequence-analysis functions, because doing so performs the later request’s sequence-analysis functions in FPGA hardware rather than software, reducing its processing time.
However, the combination of Guim Bernat, Nadathur, and van Rooyen does not teach or suggest wherein the processor is further configured to, after the one or more of the first FPGAs or the one or more of the second FPGAs finish processing, configure the one or more of the first FPGAs or the one or more of the second FPGAs that finish processing with [components] … for servicing the third request. Nonetheless, Charitopoulos teaches or suggests reserving a hardware task when no reconfigurable region is available, so that it waits for later configuration and execution, and checking after each task completes whether reserved tasks should start (pg. 3, lines 41-43; pg. 6, lines 4-7). In the section 4 example, task T3 can be loaded only on reconfigurable region RR2 and is reserved; fig. 4 shows RR2 reconfigured for T3 at t=14, when the task executing there completes (pg. 8, lines 21-25; fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that a reserved hardware task is configured for later execution on a reconfigurable region after the executing task completes as taught by Charitopoulos, because doing so allows a suitable FPGA region to be reconfigured with a compatible configuration for the waiting request as soon as it becomes available, reducing wait time and improving utilization of the pooled FPGA resources.
Regarding claim 20, the combination of Guim Bernat, Nadathur, and van Rooyen teaches or suggests the system of claim 15, and Guim Bernat further teaches or suggests wherein the processor is further configured to configure each of the one or more first FPGAs and the one or more second FPGAs with a respective [bitstream]. Bitstream generator (418) generates a bitstream compatible with each selected accelerator, and network interface (410) provides it to that accelerator, so each of the separately selected first and second FPGAs is configured with its own bitstream ([0034], [0036]).
Guim Bernat further teaches or suggests the respective [bitstream] each comprise different images. Bitstream generator (418) generates for each selected accelerator a bitstream compatible with that accelerator from its workload request, and a workload’s bitstream can be translated into a different format for another accelerator, so the respective bitstreams of the separately selected first and second FPGAs carry different images ([0016], [0034]).
Guim Bernat further teaches or suggests the different images for performing a same or different form of [analysis]. An image-detection workload can be executed from an FPGA-accepted bitstream or, after translation, on another accelerator, so different images perform the same form of analysis; the limitation is recited in the alternative, and the same-form alternative satisfies it ([0016]).
van Rooyen further teaches or suggests that the analysis is sequencing analysis. FPGA processing engines perform sequence-analysis functions, including mapping, aligning, and variant calling ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the system of Guim Bernat, Nadathur, and van Rooyen so that the different images implement van Rooyen’s sequence-analysis functions, including mapping, aligning, and variant calling, because doing so lets the scheduler dispatch a sequencing workload to whichever pooled FPGA can load an image for it, keeping the workload FPGA-accelerated and reducing its completion time.
However, the combination of Guim Bernat, Nadathur, and van Rooyen does not teach or suggest that each respective bitstream is a partially reconfigurable bitstream. Nonetheless, Charitopoulos teaches or suggests hardware tasks implemented as reconfigurable modules, stored in a bitstream repository and loaded into reconfigurable regions, each hardware task having a hardware version as partial bitstreams that are loaded by partial reconfiguration of the FPGA (pg. 3, lines 13-17; pg. 9, lines 32-33, 37-38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Guim Bernat, Nadathur, and van Rooyen so that the generated bitstreams implement Charitopoulos’s reconfigurable modules for execution on reconfigurable regions of an FPGA, because doing so permits a reconfigurable FPGA region to receive a new sequencing-analysis configuration without reconfiguring the whole device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew Georgandellis whose telephone number is 571-270-3991. The examiner can normally be reached on Monday through Friday, 7:30-5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tonia Dollinger, can be reached on 571-272-4170. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW C GEORGANDELLIS/Primary Examiner, Art Unit 2459
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