DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims1-3, 5, 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over MX25L12872F and further in view of Jigour et al. (US 7,558,900).
Claim 1: MX25L12872F teaches a non-volatile memory device comprising:
a first pin configured to receive a command and an address from a controller and to communicate first data with the controller (e.g., MX25L12872F teaches the SI/SIO0 pin. Per the Pin Description (p. 6), SI/SIO0 functions as "Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode)." This pin receives commands and addresses (e.g., Figure 32, 4READ sequence) and communicates data with a controller (e.g., Figure 46, Page Program sequence));
a second pin configured to communicate second data with the controller (e.g., SIO1 operates together with SIO0 during the dual I/O data phase.);
a memory cell array including a plurality of memory cells (e.g., MX25L12872F teaches a "128Mb bits Serial NOR Flash memory" organized as "16,777,216 x 8 internally" (p. 5), constituting a memory cell array); and
control logic configured to control an operation of the plurality of memory cells based on the command and the address (e.g., MX25L12872F teaches internal control logic that "auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed" (p. 5) and a "state machine" that manages operations (p. 8).),
wherein the first data is communicated through the first pin during an idle time and the second data communicated through second pin during the idle time, wherein the idle time starts when the command and the address are received through the first pin and ends after the first data is communicated through the first pin (e.g., MX25L12872F teaches that the 4READ (4 x I/O Read) operation. As shown in Figure 32 (p. 42) and described on p. 41, the sequence comprises: (1) sending the 4READ instruction on SIO[3:0]; (2) sending 3-byte address on SIO[3:0]; (3) 6 dummy cycles (idle time); and (4) data out on SIO[3:0]. During this idle time, no new command, address, or primary data is transferred on the first pin (SIO0). The idle time begins after the address is received and ends when data communication begins. Data is communicated through the same pin (SIO0) as part of the 4-bit wide data output).
Not explicitly taught by MX25L12872F is that the second pin used for communicating the second data is dedicated to data communication and excluded from communicating the command and address.
However, Jigour teaches a Fast Read Dual Output operation wherein an instruction and a 24-bit address are communicated through DIO pin 5, after which DIO pin 5 changes from an input to an output and read data is communicated concurrently through DIO pin 5 and DO pin 2, with alternating data bits being carried by the two pins. For instance, , Jigour defines pin 2 (DO) as a data output pin that is excluded from command/address communication. In the "Fast Read Dual Output" transaction, the command and address are only sent through pin 5 (DIO)."FIG. 14 and FIG. 15 show illustrative serial flash memory devices 80 and 100, both of which are configurable in this manner. The device 80 shown in FIG. 14 is an 8-pin SOIC packaged serial flash memory device which has a configurable data output pin DO shown at 82, a configurable data input/output pin DIO shown at 85, a serial clock input pin CLK shown at 86, a chip select input pin /CS shown at 81, ..." (e.g., col. 11, lines 4-10). The pin assignment table (FIG. 16) confirms this separation: "In SPI mode, which is used for input and which may be used for output, pin 2 is configured for bit-serial output and pin 5 is configured for bit-serial input." (e.g., col. 11, lines 26-29). Crucially, pin 2 (DO) is never used to receive the command or address; it is solely a data output pin in both standard SPI and Enhanced SPI modes.
Furthermore, the patent describes the "Fast Read Dual Output" instruction (3Bh) in detail. The sequence explicitly shows that the DIO pin (pin 5) receives the command and the 24-bit address, and after the address is received, the DIO pin switches from an input to an output, and data is concurrently output on both pins. "FIG. 19 is an instruction sequence diagram for the 'Fast Read Dual Output' instruction 3Bh, which operates under the ESPI protocol to allow one or more data bytes to be sequentially read from the memory at the highest possible frequency, but at effectively twice the rate as the 'Fast Read' instruction because two pins are used to output alternate bits." (e.g., col. 12, lines 4-9). The instruction sequence is described as follows:"The instruction is initiated by driving the /CS pin low and then shifting the instruction code '3Bh' followed by a 24-bit address (A23-A0) into the DIO pin 5 (FIG. 14)." (e.g., col. 12, lines 9-12). After the address and dummy clocks, the DIO pin changes function: "At the end of the string of dummy clocks, the DIO pin 5 switches from an input pin to an output pin, and the data byte of the addressed memory location is shifted out at the falling edge of CLK with the most significant bit first." (e.g., col. 12, lines 15-19). Then, data is output concurrently on both pins: "The shifting out of the bits of the addressed memory location alternate between the DO pin 2 (FIG. 14) and the DIO pin 5 configured as an output pin. While odd bits are shown on the DO pin 2 and even bits are shown on the DIO pin 5, this arrangement may be reversed if desired." (e.g., col. 12, lines 19-24).
Thus, DO pin 2 communicates data but is excluded from communication of the instruction and address in the disclosed Fast Read Dual Output transaction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the multi-I/O serial interface of MX25L12872F according to Jigour so that one pin communicates the command/address and subsequently a first portion of read data while a second pin communicates another portion of the read data and is excluded from communication of the command/address, because Jigour expressly teaches that such dual-output operation increases serial-flash data-transfer speed while retaining the advantages of a low-pin-count serial interface.
Claim 2: MX25L12872F teaches the non-volatile memory device of claim 1, further comprising: a second pin configured to communicate second data with the controller (e.g., The SO/SIO1 pin is disclosed as "Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode)" (p. 6), serving as a second pin), wherein the command is a write command, wherein the idle time ends when the second data is received through the second pin (e.g., the Page Program (PP) instruction (02h) uses the SI pin (first pin) for command, address, and data (p. 51, Figure 46). During this operation, the SO pin (second pin) is not used for data input, and any idle period on the first pin ends when data is received on that same pin. While the claim language requires the idle time to end when second data is received on the second pin, this is an inherent feature of Dual/Quad I/O write operations. More specifically, the 4PP (4 x I/O Page Program) command (p. 53, Figure 48) uses SIO[3:0] for address and data. Data is received on all four pins simultaneously, meaning the idle period on the first pin (SIO0) ends concurrently with data reception on the second pin (SIO1)).
Claim 3: MX25L12872F teaches the non-volatile memory device of claim 1, further comprising: a second pin configured to communicate second data with the controller, wherein the command is a read command, wherein the idle time ends when the second data is transmitted through the second pin (e.g., The 2READ (2 x I/O Read) operation (p. 39, Figure 30) uses SIO0 and SIO1 for address, dummy cycles, and data output. After the command is sent on SI (first pin) and address on both pins, there are 4 dummy cycles (idle time). The idle time ends when data is transmitted on both SIO0 (first pin) and SIO1 (second pin)).
Claim 10: MX25L12872F teaches the non-volatile memory device of claim 1, wherein the first pin is separate from the second pin (e.g., The device is an 8-pin package with physically distinct pins: SI/SIO0 and SO/SIO1 are different pins (p. 6, Pin Configurations)).
Claim 5: MX25L12872F teaches the non-volatile memory device of claim 1, further comprising: a second pin configured to communicate second data with the controller (e.g., MX25L12872F teaches the SO/SIO1 pin as "Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode)" (p. 6), serving as a second pin for data communication); and a clock pin configured to receive a clock signal from the controller (e.g., MX25L12872F teaches the SCLK pin as "Serial clock input" (p. 4) and "Clock Input" (p. 6), which receives the clock signal from the controller), wherein the clock signal toggles only in a period in which the command and the address are received from the controller or in a period in which the first data and the second data are communicated between the controller and the non-volatile memory device (e.g., MX25L12872F teaches this limitation inherently through its SPI operation. As shown in "Figure 1. Serial Modes Supported" (p. 12) and described in Section 8, the device operates such that "Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK." The device enters active mode only when a command is issued and returns to standby mode when CS# is high (p. 12). During standby mode when no command, address, or data is being transferred, the clock signal is not required for device operation and is typically stopped or ignored by the device. The timing diagrams throughout the datasheet (e.g., Figures 27-33) consistently show SCLK toggling only during command/address input periods and data communication periods, with no toggling shown during idle periods when CS# is deasserted).
Claim 6: MX25L12872F teaches the non-volatile memory device of claim 5, wherein the clock signal corresponds to a data input/output clock signal (e.g., The SCLK pin is explicitly described as the "Serial clock input" (p. 4) that provides timing for both input (commands, addresses, data) and output (data) operations. As described in Section 8, "Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK" (p. 12). This confirms that SCLK functions as a data input/output clock signal).
Claim(s) 4, and 8, are rejected under 35 U.S.C. 103 as being unpatentable over MX25L12872F and Jigour et al as applied to claim 3 and further in view of JP2015176616A.
Claim 4: MX25L12872F and Jigour et al teach the non-volatile memory device of claim 3, but fails to teach that the first data includes a parity bit generated by the controller, and the second data includes data except for the parity bit or a piece of data among pieces of data including the parity bit. However, JP2015176616A describes a system where data is protected by an error correction code. For instance, Figures 7-9 and the accompanying text describe a memory architecture with a "regular region" for main data and a "spare region" for storing parity bits (error correction codes). Furthermore, the patent discusses how the controller (or on-chip logic) generates these parity bits (Figure 11, step S204). Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to combine the teaching of MX25L12872F and Jigour et al with the one disclosed by JP2015176616A in order to improve the data reliability of a standard SPI Flash memory like the MX25L12872F.
Claim 8: MX25L12872F and Jigour et al teach the non-volatile memory device of claim 5, wherein: the clock signal corresponds to a data strobe signal (e.g., Section 8, Fig. 1, 2: The MX25L12872F is a standard SPI memory with a dedicated SCLK pin that functions as a clock signal for synchronizing command, address, and data transfers. This inherent function makes it a "data strobe signal"), the command and the address are received from the controller through the first pin (e.g., Section 9, Fig. 27, 46: In standard SPI operation as taught by MX25L12872F, the command and address are indeed received serially through a primary data input pin (SI/SIO0), which serves as the "first pin"), the first data is communicated between the controller and the non-volatile memory device through the first pin during the idle time (e.g., Section 9: After the command and address are sent, the device enters an "active mode" for data transfer. In many commands (like Page Program), the data to be programmed ("first data") is also input through the same SI/SIO0 pin), the second data is communicated between the controller and the non-volatile memory device through the second pin (e.g., Section 9, Fig. 28: For read operations, after the command and address, the output data ("second data") is transmitted out on the dedicated SO/SIO1 pin, which acts as the "second pin").
Not explicitly taught by MX25L12872F is that the first data includes a parity bit generated by the controller, and the second data does not include the parity bit. However, JP2015176616A (in Abstract, [0011], [0022], Fig. 5) teaches a memory system where a controller generates a parity bit (error correction code) for program data. This parity bit is part of the data stream provided by the controller to the memory. In its Figure 5, input data Di (which can include such a parity bit) is loaded into both the page buffer and the ECC circuit. Furthermore, JP2015176616A (in Fig. 7-9, [0031]) describes a memory architecture with a regular region for main data and a spare region for the parity bit. This inherently teaches that when reading data (the "second data" in Claim 8), the main data output from the regular region does not include the parity bits stored separately in the spare region.
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to implement the teaching of MX25L12872F with the one disclosed by JP2015176616A in order to improve the data reliability of a standard SPI Flash memory like the MX25L12872F.
Claim(s) 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over MX25L12872F and Jigour et al as applied to claim 5 and further in view of Dodd et al (US 6,449,213 B1).
Claim 7: MX25L12872F teaches the non-volatile memory device of claim 5, but fails to teach that the clock signal corresponds to a data strobe signal, the clock pin corresponds to a data strobe pin, and the command and the address are received from the controller through the first pin in synchronization with the data strobe signal. However, Dodd et al explicitly teach the concept of using a dedicated strobe signal for source-synchronous transmission of command and address information. As stated in the patent: "the address/command buffer receives address/command information using source-synchronized signaling" and "the memory devices... may be adapted to sample address/command information responsive to a source-synchronous strobe signal". Figures 1-3 show the address/command strobe signal (CMDSTB) being used to sample the command/address signals. Therefore, a POSITA, before the effective filing date of the claimed invention, would have found it obvious to apply the teaching of Dodd et al, where the clock function for command/address is performed by a source-synchronous strobe, to the basic memory structure of the MX25L12872F in order to improve the speed and timing margins of a standard SPI memory like the MX25L12872F.
As per claim 9, the claim is nearly identical to Claim 8, with the only difference being that the "clock signal corresponds to a read enable signal" instead of a data strobe signal. Dodd et al teach the use of a strobe signal for command/address. The specific nomenclature of the signal, whether called a "strobe," "clock," or "read enable", is a trivial design choice. The fundamental function is to provide a timing reference for capturing the command and address. Besides, the concept of a "read enable" signal is common in memory interfaces. Thus, a person of ordinary skill would recognize that the source-synchronous strobe taught in Dodd et al could be implemented and referred to as a "read enable" signal without changing its function.
Claim(s) 11-14, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over MX25L12872F and Jigour et al as applied to claim 1 and further in view of SST26VF064B.
Claim 11: MX25L12872F, when read in context with a standard memory controller, teaches a controller comprising: a first pin configured to transmit a command and an address to a non-volatile memory device, and to communicate first data with the non-volatile memory device (e.g., A controller inherently has an output pin connected to the memory device's SI/SIO0 pin to transmit commands/addresses and communicate data. This is the necessary counterpart to the memory device's operation disclosed throughout MX25L12872F).
Not explicitly taught by MX25L12872F and Jigour et al is a parity bit generator configured to generate a parity bit; and an error correction code (ECC) circuit configured to detect or correct an error based on the first data or the second data, wherein the first data is communicated through the first pin during an idle time, wherein the idle time starts when the controller transmits the command and the address through the first pin and ends after the first data is communicated through the first pin.
However, SST26VF064B, as a memory device, also operates with a controller. The datasheet describes the device's interface but, like MX25L12872F, does not detail controller internals. However, the relevance of SST26VF064B is that it represents the same field of endeavor (serial flash memory) and confirms the standard nature of command/address/data protocols with idle periods (e.g., dummy cycles in Figure 5-9 for SPI Quad I/O Read).
Therefore, a person of ordinary skill in the art (POSITA), before the effective filing date of the claimed invention, designing a memory system would have started with a known memory device, such as the MX25L12872F. To control this device, the POSITA would have necessarily designed or selected a controller capable of generating the required command sequences and timing. It is common general knowledge, and well-documented in the art, that memory controllers for flash memory often include ECC functionality to ensure data integrity over the device's lifetime. The SST26VF064B datasheet confirms the standard nature of the interface protocol, reinforcing that any controller designed for such devices must manage idle periods. Combining the teachings of MX25L12872F (the memory device and its protocol) with the well-known concept of an ECC-equipped controller (as would be understood by a POSITA and confirmed by the existence of similar devices like SST26VF064B) would have been obvious. The inclusion of a parity bit generator and ECC circuit in the controller is a predictable improvement to enhance reliability without altering the fundamental interface timing.
As per claim 18, the claimed features are rejected similarly to claim 11 above.
As per claim 12, the "second pin" limitation is met by the controller's output pin connected to the memory's SO/SIO1 pin. The idle time ending when second data is communicated is inherent to Dual/Quad I/O operations as described for Claims 2 and 3 above.
Claim 13: MX25L12872F and SST26VF064B teach the controller of claim 11, but fail to teach that: the first data includes the parity bit, and the second data includes data except for the parity bit or a piece of data among pieces of data including the parity bit. However, MX25L12872F teaches the basic data communication structure where data is transferred on multiple pins (e.g., 4READ uses SIO[3:0] for data output). It does not teach partitioning data into parity and non-parity bits across different pins. And SST26VF064B similarly teaches multi-pin data transfer without explicit parity partitioning. Nonetheless, the concept of embedding parity or ECC information within a data stream is a fundamental and well-known technique in digital communications and memory systems. A POSITA seeking to improve data reliability would understand that ECC information must be transmitted alongside user data. Partitioning the data such that some pins carry user data and others carry associated parity bits is a straightforward design choice within the capabilities of a multi-pin interface. Once the controller is equipped with ECC circuitry (as per Claim 11), the implementation of transmitting parity bits on one or more of the available I/O pins during the data phase would be an obvious optimization to maximize throughput or simplify design. The exact distribution of bits across pins is a routine matter of design choice.
Claim 14: MX25L12872F and SST26VF064B teach the controller of claim 11, further comprising a clock pin configured to transmit a clock signal to the non-volatile memory device. For instance, SST26VF064B teaches a controller-side interface with a clock pin. The SST26VF064B datasheet describes the controller's perspective of the interface, including the SCK pin's function: "SCK Serial Clock: To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input." This description necessarily implies a controller that has a corresponding clock pin (connected to the memory device's SCK pin) to transmit this clock signal. The controller is the master that generates and transmits the clock; the memory device receives it.Claim 17: MX25L12872F and SST26VF064B teach the controller of claim 11, wherein the first pin is separate from the second pin (e.g., MX25L12872F teaches that the device is an 8-pin package with physically distinct pins: SI/SIO0 and SO/SIO1 are different pins (p. 6, Pin Configurations)).
Claim 19: MX25L12872F and SST26VF064B teach the memory system of claim 18, wherein the idle time ends when the second data is communicated between the controller and the non-volatile memory device through the controller and memory data pins (e.g., MX25L12872F: P. 39, Fi. 30; SST26VF064B: P. 19, Fig. 5-9).
Claim(s) 15, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over MX25L12872F, Jigour et al and SST26VF064B and further in view of Dodd et al (US 6,449,213 B1).
Claim 15: MX25L12872F, Jigour et al and SST26VF064B teach the controller of claim 14, wherein the clock signal corresponds to a data strobe signal (e.g., Section 8, Fig. 1, 2: The MX25L12872F is a standard SPI memory with a dedicated SCLK pin that functions as a clock signal for synchronizing command, address, and data transfers. This inherent function makes it a "data strobe signal"), the command and the address are transmitted to the non-volatile memory device through the first pin (e.g., Section 9, Fig. 27, 46: In standard SPI operation as taught by MX25L12872F, the command and address are indeed received serially through a primary data input pin (SI/SIO0), which serves as the "first pin"), the first data is communicated between the controller and the non-volatile memory device through the first pin during the idle time (e.g., Section 9: After the command and address are sent, the device enters an "active mode" for data transfer. In many commands (like Page Program), the data to be programmed ("first data") is also input through the same SI/SIO0 pin), the second data is communicated between the controller and the non-volatile memory device through the second pin (e.g., Section 9, Fig. 28: For read operations, after the command and address, the output data ("second data") is transmitted out on the dedicated SO/SIO1 pin, which acts as the "second pin").
Not explicitly taught by MX25L12872F, Jigour et al and SST26VF064B is that the first data includes the parity bit, and the second data does not include the parity bit. However, JP2015176616A (in Abstract, [0011], [0022], Fig. 5) teaches a memory system where a controller generates a parity bit (error correction code) for program data. This parity bit is part of the data stream provided by the controller to the memory. In its Figure 5, input data Di (which can include such a parity bit) is loaded into both the page buffer and the ECC circuit. Furthermore, JP2015176616A (in Fig. 7-9, [0031]) describes a memory architecture with a regular region for main data and a spare region for the parity bit. This inherently teaches that when reading data (the "second data" in Claim 8), the main data output from the regular region does not include the parity bits stored separately in the spare region.
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to implement the teaching of MX25L12872F with the one disclosed by JP2015176616A in order to improve the data reliability of a standard SPI Flash memory like the MX25L12872F.
As per claim 16, the claim is nearly identical to Claim 8, with the only difference being that the "clock signal corresponds to a read enable signal" instead of a data strobe signal. Dodd et al teach the use of a strobe signal for command/address. The specific nomenclature of the signal, whether called a "strobe," "clock," or "read enable", is a trivial design choice. The fundamental function is to provide a timing reference for capturing the command and address. Besides, the concept of a "read enable" signal is common in memory interfaces. Thus, a person of ordinary skill would recognize that the source-synchronous strobe taught in Dodd et al could be implemented and referred to as a "read enable" signal without changing its function.
Claim 20: MX25L12872F, Jigour et al and SST26VF064B teach the memory system of claim 18, wherein the first data communicated through the controller and memory input/output (e.g., Section 9: After the command and address are sent, the device enters an "active mode" for data transfer. In many commands (like Page Program), the data to be programmed ("first data") is also input through the same SI/SIO0 pin), during the idle time (see Section 8: "After a correct command is written... it enters active mode... until the next CS# rising edge") and the second data communicated through the controller and memory data pins during the idle time(e.g., Section 9, Fig. 28: For read operations, after the command and address, the output data ("second data") is transmitted out on the dedicated SO/SIO1 pin, which acts as the "second pin").
Not explicitly taught by MX25L12872F and SST26VF064B is that the first data includes the parity bit, and the second data does not include the parity bit. However, JP2015176616A (in Abstract, [0011], [0022], Fig. 5) teaches a memory system where a controller generates a parity bit (error correction code) for program data. This parity bit is part of the data stream provided by the controller to the memory. In its Figure 5, input data Di (which can include such a parity bit) is loaded into both the page buffer and the ECC circuit. Furthermore, JP2015176616A (in Fig. 7-9, [0031]) describes a memory architecture with a regular region for main data and a spare region for the parity bit. This inherently teaches that when reading data (the "second data" in Claim 8), the main data output from the regular region does not include the parity bits stored separately in the spare region.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/10/2026
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