DETAILED ACTION
This office action is in response to Application No. 18/949,192, filed on 15 November 2024. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,175,175. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the application are identical to the corresponding claims of the patent except that the application’s claims omit and broaden limitations, and are thus fully anticipated by the patent’s corresponding claims. Specifically, the application’s independent claims delete the ‘providing RTL design information’ step, the module characteristics (‘same number of wordlines …’), the ‘generating structural information’ step (which is moved to dependent claims 8 and 9), and the ‘creating a set of one or more synthesizable semiconductor device configurations’ step. The application’s claims also broaden ‘first and second’ to ‘plurality’, and ‘wrapping the first and second compilations and the storage to generate a plurality of netlists’ to a generic ‘based on’ relationship of ‘generating a plurality of netlists based on the compilations and a feature of the storage’.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 8, 9, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam (US 2016/0246910) in view of Xilinx (“Command Line Tools User Guide, Chapter 10: SmartXplorer”) and Chung (US 2012/0209888).
Regarding claim 1, Subramaniam discloses a method for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor design (¶¶2, 49, 55) comprising:
generating behavior information associated with at least a portion of an RTL design corresponding to the semiconductor device (¶¶20, 41, 44);
compiling, by a compiler, a set of semiconductor devices based on one or more technologies and power, performance and area (PPA) information across a plurality of technology sizes, wherein the compiling generates a plurality of compilations (¶¶46, 53, 60, 62, 77);
storing at least one setting of the compiler in a storage (¶20);
generating a plurality of netlists based on the compilations and a feature of the storage, wherein each of the netlists corresponds to a respective one of the compilations (¶20, memory parameters stored with RTL; ¶¶44-46, 58, 77);
identifying semiconductor devices within the compiled semiconductor devices that meet predefined PPA conditions by querying the PPA information across the plurality of technology sizes (¶¶62, 77);
generating a design netlist with structure-synthesizable input/output boundary compatible semiconductor device modules (Figs. 1 and 4; ¶¶21, 49, 56, 57; the simulation models, synthesized RTL, timing models, and layout models are used to perform timing analysis and place & route on the design which includes different blocks/modules that interface with each other).
If Subramaniam is found to be unclear regarding generating a plurality of netlists based on the compilations and a feature of the storage, wherein each of the netlists corresponds to a respective one of the compilations, Xilinx discloses the same (p. 136, Phase 1; p. 143, Custom Strategies, strategy file). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam and Xilinx, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of quickly determining performance for various design options. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Subramaniam discloses design space exploration that compiles sets of devices using different parameters such as technology size, determining performance metrics for the devices, and iteratively optimizes the parameter selection through a flow that includes generating netlists of the compiled devices. Xilinx provides additional explicit clarification of generating netlists for compilations through synthesis, MAP, and PAR to determine performance metrics for each compilation. The teachings of Xilinx are directly applicable to Subramaniam, so Subramaniam would similarly generate netlists for the compilations to quickly determine performance metrics for the compilations.
If Subramaniam is found to be unclear regarding structure-synthesizable input/output boundary compatible semiconductor device modules, Chung discloses generating a design netlist with structure-synthesizable input/output boundary compatible semiconductor device modules (¶46). Notably, Chung discloses generating synthesizable files to incorporate the memory macro into an SoC, particularly the I/O ports and their specifications, connectivity, and physical locations so that design tools can merge the memory macro with the rest of the SoC circuits.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, and Chung, because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Subramaniam and Chung are both directed to the design of devices incorporating multiple design blocks, including memories. Furthermore, both Subramaniam and Chung disclose generating information for the memory blocks to be used with conventional design tools/processes such as timing verification, synthesis, and placement & routing. Subramaniam does not appear to explicitly address that structural information allows for the alignment of I/O, though persons having ordinary skill in the art would understand that the structural information would allow such alignment. Chung further provides explicit disclosure of specifying I/O information, including physical locations and boundary layout, so that the memory block can be connected to other elements in the SoC. The teachings of Chung are directly applicable to Subramaniam in the same way, so that Subramaniam’s information would similarly specify structural I/O information of the memory that would allow integration into the complete device design.
Regarding claim 2, Subramaniam discloses selecting one of the synthesizable semiconductor device design for synthesis (¶¶20, 56, 60, 61).
Regarding claim 3, Subramaniam discloses that the semiconductor device is at least one memory device, the method further comprising generating size information for the memory device (¶¶20, 64-65).
Regarding claim 5, Subramaniam discloses wherein compiling the set of semiconductor devices is based further on information about the size of the memory (¶21, 41, 64-65).
Regarding claim 8, Subramaniam discloses after generating the behavior information, generating structural information (Fig. 4; blocks 417, 427, 447; ¶58), but does not appear to explicitly disclose that the structural information is for aligning input/output ports of the semiconductor device. However, persons having ordinary skill in the art would understand that the structural information generated by Subramaniam would allow for aligning the input/output ports of the semiconductor device, since the simulation models, synthesized RTL, timing models, and layout models (as in ¶¶55-57) are used to perform timing analysis and place & route on the design which includes different blocks/modules that interface with each other (Fig. 1).
Nevertheless, Chung discloses generating structural information for aligning the input/output ports of the semiconductor device (¶46). Notably, Chung discloses generating synthesizable files to incorporate the memory macro into an SoC, particularly the I/O ports and their specifications, connectivity, and physical locations so that design tools can merge the memory macro with the rest of the SoC circuits. Motivation to combine remains consistent with claim 1.
Regarding claim 9, Subramaniam discloses after compiling the set of semiconductor devices, generating structural information (Fig. 4; blocks 417, 417, 447; ¶¶20, 58, 77), but does not appear to explicitly disclose that the structural information is for aligning input/output ports of the semiconductor device. However, persons having ordinary skill in the art would understand that the structural information generated by Subramaniam would allow for aligning the input/output ports of the semiconductor device, since the simulation models, synthesized RTL, timing models, and layout models (as in ¶¶55-57) are used to perform timing analysis and place & route on the design which includes different blocks/modules that interface with each other (Fig. 1).
Nevertheless, Chung discloses generating structural information for aligning the input/output ports of the semiconductor device (¶46). Notably, Chung discloses generating synthesizable files to incorporate the memory macro into an SoC, particularly the I/O ports and their specifications, connectivity, and physical locations so that design tools can merge the memory macro with the rest of the SoC circuits. Motivation to combine remains consistent with claim 1.
Regarding claim 20, Subramaniam discloses a system for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor design (¶¶2, 49, 55) comprising:
one or more data processors configured to perform operations commanded by instructions stored on a non-transitory computer-readable medium (Fig. 6), the instructions comprising:
generating behavior information associated with an RTL design corresponding to one or more memory devices associated with the semiconductor device (¶¶20, 41, 44);
compiling, by a compiler, a set of memory devices based on one or more technologies and power, performance and area (PPA) information across a plurality of technology sizes, wherein the compiling generates a plurality of compilations (¶¶46, 53, 60, 62, 77);
storing at least one setting of the compiler in a storage (¶20);
generating a plurality of netlists based on the compilations and a feature of the storage, wherein each of the netlists corresponds to a respective one of the compilations (¶20, memory parameters stored with RTL; ¶¶44-46, 58, 77);
identifying memory devices within the compiled semiconductor devices that meet predefined PPA conditions by querying the PPA information across the plurality of technology sizes (¶¶62, 77); and
generating a design netlist with structure-synthesizable input/output boundary compatible memory device modules (Figs. 1 and 4; ¶¶21, 49, 56, 57; the simulation models, synthesized RTL, timing models, and layout models are used to perform timing analysis and place & route on the design which includes different blocks/modules that interface with each other).
If Subramaniam is found to be unclear regarding generating a plurality of netlists based on the compilations and a feature of the storage, wherein each of the netlists corresponds to a respective one of the compilations, Xilinx discloses the same (p. 136, Phase 1; p. 143, Custom Strategies, strategy file). Motivation to combine remains consistent with claim 1.
If Subramaniam is found to be unclear regarding structure-synthesizable input/output boundary compatible semiconductor device modules, Chung discloses generating a design netlist with structure-synthesizable input/output boundary compatible semiconductor device modules (¶46). Notably, Chung discloses generating synthesizable files to incorporate the memory macro into an SoC, particularly the I/O ports and their specifications, connectivity, and physical locations so that design tools can merge the memory macro with the rest of the SoC circuits. Motivation to combine remains consistent with claim 1.
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam in view of Xilinx, Chung, and Iyer (US 2011/0145777).
Regarding claim 5, Subramaniam does not appear to explicitly disclose that the memory device is a random access memory (RAM MACRO) selected from a group comprising at least one of a single port (SP SRAM), a 2-port (2P) SRAM, a dual-port (DP) SRAM, a single port (1P) register files, and/or a dual-port (2P) register files. However, the listed memory types are conventional in the art. Chung discloses that the memory is a random access memory (¶15). Iyer discloses that the memory is a random access memory (RAM MACRO) selected from a group comprising at least one of a single port (SP SRAM), a 2-port (2P) SRAM, a dual-port (DP) SRAM, a single port (1P) register files, and/or a dual-port (2P) register files (¶73).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, Chung, and Iyer, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of producing designs for specific memory types. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam, Chung, and Iyer are directed to processes for designing memories. While Subramaniam allows users to specify memory parameters, Subramaniam does not appear to explicitly address the specific memory types recited in the claim, and while Chung does disclose that the memory is RAM, Chung also does not appear to explicitly address the specific claimed memory types. Iyer provides further explicit disclosure of specific memory types, which are directly applicable to the design processes of Subramaniam and Chung in the same way, so that Subramaniam and Chung’s processes would similarly be used to produce known memory types.
Claims 6, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam in view of Xilinx, Chung, and Subramaniam (US 2016/0292313, hereinafter, “Nham”).
Regarding claim 6, Subramaniam does not appear to explicitly disclose that the one or more technologies includes fabrication technology corresponding to any combination of one or more of 3um, 1.5um, 1.2um, 1.0um, 0.8um, 0.6um, 0.5um, 0.35um, 0.25um, 0.18um, 0.13um, 90nm, 65nm, 40nm, 28nm, 22nm, 20nm, 16nm, 12nm, 10nm, 7nm, 6nm, 5nm, 3nm fabrication. However, Subramaniam does discloses fabrication technology nodes such as 45nm (¶62), and persons having ordinary skill in the art would recognize that the claimed technologies are conventional technology nodes. Nevertheless, Nham explicitly discloses the claimed fabrication technologies (¶24).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, Chung, and Nham, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of developing designs using conventional technology nodes. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam, Chung, and Nham are directed to memory design processes, and Subramaniam and Nham discloses determining appropriate technology nodes for design blocks. While Subramaniam discloses one conventional design node, Nham provides explicit disclosure of other conventional design nodes, which are directly applicable to Subramaniam in the same way, so that Subramaniam’s process would similarly use other conventional design nodes as well.
Regarding claim 7, Subramaniam discloses that the compiling comprises using one or more databases of information, including a database of physical memory configurations and/or performance, power, and area information (¶¶51, 53). In the event that Subramaniam is found to be unclear regarding this limitation, Nham also discloses the same (¶¶30, 40).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, Chung, and Nham, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using a PPA database to select appropriate designs. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam, Chung, and Nham are directed to memory design processes, and Subramaniam and Nham specifically evaluate design candidates (trial points) against PPA metrics in order to select candidates that meet PPA targets. Nham further teaches using a PPA database to collect PPA information of different designs, which can then be consulted during design selection. The teachings of Nham are directly applicable to Subramaniam in the same way, so that Subramaniam would similarly use a PPA database when selecting designs that meet PPA targets.
Regarding claim 10, Subramaniam does not appear to explicitly disclose that the compiling groups the semiconductor devices based on the technology sizes; Nham discloses these limitations (Fig. 1; ¶¶23, 32). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, Chung, and Nham, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of grouping compilations by compatibility. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam discloses compiling devices across various technology sizes. Nham teaches that devices are grouped by technology size for compatibility. The teachings of Nham are directly applicable to Subramaniam in the same way, so that Subramaniam’s compiling would similarly group devices by technology size, for compatibility.
Claims 11, 13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam in view of Xilinx.
Regarding claim 11, Subramaniam discloses a system for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design (¶¶2, 49, 55) comprising:
one or more data processors configured to perform operations commanded by instructions stored on a non-transitory computer-readable medium (Fig. 6), the instructions comprising:
generating size information associated with at least a portion of an RTL design corresponding to the semiconductor device (¶¶20, 62);
compiling, by a compiler, a set of semiconductor devices based on one or more technologies and power, performance and area (PPA) information across a plurality of technology sizes, wherein the compiling generates a plurality of compilations (¶¶46, 53, 60, 62, 77);
storing at least one setting of the compiler in a storage (¶20);
generating a plurality of netlists based on the compilations and a feature of the storage, wherein each of the netlists corresponds to a respective one of the compilations (¶20, memory parameters stored with RTL; ¶¶44-46, 58, 77);
identifying semiconductor devices within the compiled semiconductor devices that meet predefined PPA conditions by querying the PPA information across the plurality of technology sizes (¶¶62, 77);
generating a design netlist based on the generated size information and the compiled semiconductor devices (Fig. 4; ¶¶21, 49, 56, 57, 60-65, 77).
If Subramaniam is found to be unclear regarding generating a plurality of netlists based on the compilations and a feature of the storage, wherein each of the netlists corresponds to a respective one of the compilations, Xilinx discloses the same (p. 136, Phase 1; p. 143, Custom Strategies, strategy file). Motivation to combine remains consistent with claim 1.
Regarding claim 13, Subramaniam discloses that the semiconductor device is at least one memory device, the instructions further comprising generating behavior information for the memory device (¶¶20, 41, 44).
Regarding claim 15, Subramaniam discloses that the instructions compile the set of semiconductor devices based further on information about the size of the memory device (¶¶21, 41, 64-65).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam in view of Xilinx and Kasat (US 10,437,946).
Regarding claim 3, Subramaniam does not appear to explicitly disclose that the RTL design is obtained from a plurality of sources. However, it is known in the art to have RTL designs developed by multiple designers/teams/entities, as disclosed by Kasat (col. 4, lines 6-15). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, and Kasat, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of handling RTL developed by multiple entities. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam is directed to circuit design processes that use RTL designs as input. Kasat discloses that such RTL designs can be produced by multiple sources and then linked. The teachings of Kasat are directly applicable to Subramaniam in the same way, so that Subramaniam would similarly be able to handle RTL designs produced by multiple designers.
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam in view of Xilinx and Iyer.
Regarding claim 14, Subramaniam does not appear to explicitly disclose that the memory device is a random access memory (RAM MACRO) selected from a group comprising at least one of a single port (SP SRAM), a 2-port (2P) SRAM, a dual-port (DP) SRAM, a single port (1P) register files, and/or a dual-port (2P) register files. However, the listed memory types are conventional in the art. Iyer discloses that the memory is a random access memory (RAM MACRO) selected from a group comprising at least one of a single port (SP SRAM), a 2-port (2P) SRAM, a dual-port (DP) SRAM, a single port (1P) register files, and/or a dual-port (2P) register files (¶73).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, and Iyer, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of producing designs for specific memory types. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam and Iyer are directed to processes for designing memories. While Subramaniam allows users to specify memory parameters, Subramaniam does not appear to explicitly address the specific memory types recited in the claim. Iyer provides further explicit disclosure of specific memory types, which are directly applicable to the design processes of Subramaniam in the same way, so that Subramaniam’s process would similarly be used to produce known memory types.
Claims 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam in view of Xilinx and Nham.
Regarding claim 16, Subramaniam does not appear to explicitly disclose that the one or more technologies includes fabrication technology corresponding to any combination of one or more of 3um, 1.5um, 1.2um, 1.0um, 0.8um, 0.6um, 0.5um, 0.35um, 0.25um, 0.18um, 0.13um, 90nm, 65nm, 40nm, 28nm, 22nm, 20nm, 16nm, 12nm, 10nm, 7nm, 6nm, 5nm, 3nm fabrication. However, Subramaniam does discloses fabrication technology nodes such as 45nm (¶62), and persons having ordinary skill in the art would recognize that the claimed technologies are conventional technology nodes. Nevertheless, Nham explicitly discloses the claimed fabrication technologies (¶24).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, and Nham, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of developing designs using conventional technology nodes. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam and Nham are directed to memory design processes, and Subramaniam and Nham discloses determining appropriate technology nodes for design blocks. While Subramaniam discloses one conventional design node, Nham provides explicit disclosure of other conventional design nodes, which are directly applicable to Subramaniam in the same way, so that Subramaniam’s process would similarly use other conventional design nodes as well.
Regarding claim 17, Subramaniam discloses that the compiling comprises using one or more databases of information, including a database of physical memory configurations and/or performance, power, and area information (¶¶51, 53). In the event that Subramaniam is found to be unclear regarding this limitation, Nham also discloses the same (¶¶30, 40).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, and Nham, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using a PPA database to select appropriate designs. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Subramaniam, and Nham are directed to memory design processes, and Subramaniam and Nham specifically evaluate design candidates (trial points) against PPA metrics in order to select candidates that meet PPA targets. Nham further teaches using a PPA database to collect PPA information of different designs, which can then be consulted during design selection. The teachings of Nham are directly applicable to Subramaniam in the same way, so that Subramaniam would similarly use a PPA database when selecting designs that meet PPA targets.
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subramaniam in view of Xilinx, Hana (US 5,210,701), Tang (US 2018/0253346), and Wakasugi (US 5,742,540).
Regarding claim 18, Subramaniam does not appear to explicitly disclose that the compiling is such that semiconductor devices of the set of semiconductor devices having a same number of wordlines and a same number of bitlines are compiled together. However, these limitations are implied by, or merely an obvious variant of, Subramaniam’s compilation process. As discussed above, Subramaniam discloses compiling semiconductor devices using different combinations of a variety of parameters, including number of wordlines (¶22), number of bitlines (¶23), and process node (¶62), which implies compiling, for example, memories with 1 wordline and 1 bitline on a 28nm process, 1 wordline and 1 bitline on a 14nm process, 2 wordlines and 2 bitlines on a 28nm process, 2 wordlines and 2 bitlines on a 14nm process, etc. In other words, since Subramaniam explicitly contemplates design space exploration where devices are compiled across different combinations of parameters by varying the parameters, Subramaniam’s compilation would include compilations where one parameter is changed (e.g. process node), but another parameter is not (e.g. number of wordlines). Hana further discloses that memory compilation is performed with set parameters defining number of wordlines and bitlines (col. 7, lines 12-17), and provides examples of the same compiled memory at different process technologies (col. 11, Table 2). Tang discloses libraries providing identical cells across different process nodes (¶46), which improves scalability/portability of the components. Persons having ordinary skill in the art would understand that having the same number of words or bits also means having the same number of wordlines or bitlines, respectively, but if Subramaniam and Hana are found to be unclear regarding wordlines and bitlines, Wakasugi clarifies that setting the number of bits/words is equivalent to setting the number of bitlines/wordlines, and is necessary for forming a memory (col. 10, lines 47-50). The combination of Subramaniam, Hana, Tang, and Wakasugi would fairly suggest compiling devices with a set number of wordlines/bitlines (per Hana and Wakasugi) that are identical across a variety of process nodes (per Tang), which is already performed by Subramaniam’s process of compiling devices while varying parameters such as process node.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Subramaniam, Xilinx, Hana, Tang, and Wakasugi, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of compiling devices across a variety of process nodes for the same number of wordlines and bitlines, in order to improve scalability and portability of the compiled devices. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. As discussed above, Subramaniam discloses design space exploration across different trial points for a generic memory model, the trial points including model parameters such as number of wordlines/bitlines and process node. Hana teaches that memories are compiled for given wordline/bitline parameters, with the same memory being compiled for different process nodes. Wakasugi provides clarification that number of words/bits are analogous to number of wordlines/bitlines. Tang teaches that identical devices are provided at different process nodes to improve scalability and portability. The teachings of Hana, Wakasugi, and Tang are directly applicable to Subramaniam, so that Subramaniam’s design space exploration would similarly compile devices at a given number of wordlines/bitlines across different process nodes, in order to improve scalability and portability of the compiled devices.
Regarding claim 19, Subramaniam does not appear to explicitly disclose that the compiling is such that semiconductor devices of the set of semiconductor devices having a number of wordlines the same as a number of bitlines are compiled together. However, this limitation is implied by, or merely an obvious variant of, Subramaniam’s compilation process. As discussed above, Subramaniam discloses compiling semiconductor devices using different combinations of a variety of parameters, including number of wordlines (¶22), number of bitlines (¶23), and process node (¶62), which implies compiling, for example, memories with 1 wordline and 1 bitline on a 28nm process, 1 wordline and 1 bitline on a 14nm process, 2 wordlines and 2 bitlines on a 28nm process, 2 wordlines and 2 bitlines on a 14nm process, etc. In other words, since Subramaniam explicitly contemplates design space exploration where devices are compiled across different combinations of parameters by varying the parameters, Subramaniam’s compilation would include compilations where one parameter is changed (e.g. process node), but another parameter is not (e.g. number of wordlines). Hana further discloses that memory compilation is performed with set parameters defining number of wordlines and bitlines (col. 7, lines 12-17), and provides examples of the same compiled memory at different process technologies (col. 11, Table 2). Tang discloses libraries providing identical cells across different process nodes (¶46), which improves scalability/portability of the components. Persons having ordinary skill in the art would understand that having the same number of words or bits also means having the same number of wordlines or bitlines, respectively, but if Subramaniam and Hana are found to be unclear regarding wordlines and bitlines, Wakasugi clarifies that setting the number of bits/words is equivalent to setting the number of bitlines/wordlines, and is necessary for forming a memory (col. 10, lines 47-50). The combination of Subramaniam, Hana, Tang, and Wakasugi would fairly suggest compiling devices with a set number of wordlines/bitlines (per Hana and Wakasugi) that are identical across a variety of process nodes (per Tang), which is already performed by Subramaniam’s process of compiling devices while varying parameters such as process node. Motivation to combine remains consistent with claim 18.
Conclusion
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4 September 2026
/ARIC LIN/ Examiner, Art Unit 2851
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