Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending, with claims 6 and 9-17 being withdrawn. Bolded claim language below regards newly amended subject matter with a corresponding new rejection citation. Newly amended subject matter that is not bolded does not comprise a new rejection citation (utilizes previous interpretation that is unchanged in view of the new language) or is a newly added claim.
Claim Objections
3. Claim 1 is objected to because of the following informalities: Newly amended subject matter includes “a first electrode” of the driving transistor. Previous subject matter of the write transistor claimed to be “connected between a first electrode of the driving transistor”. The second instance of “a” first electrode should be “the” first electrode for proper antecedent basis.
Claim Rejections - 35 USC § 112
4. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Newly amended subject matter includes a compensation transistor connected between the second node and the third node defined to respectively regard the first and second electrode of the driving transistor. Previously claimed subject matter defined the first node (N1 of applicant’s figure 4 as argued in the remarks filed 6/29/2026) to be the gate of the driving transistor (M1 of applicant’s figure 4). Further, applicant’s remarks labels M4 to be the compensation transistor that is depicted to be directly connected to N1 and N3, the claimed first and third nodes, not the second N2 and third N3 nodes as currently claimed.
It is suggested to amend the subject matter to read: a compensation transistor connected between the first and the third node. Such an amendment would overcome this 112 new matter rejection. Additionally, the art rejection applied below will interpret the newly amended compensation transistor to be connected in a manner as supported by the specification (between the first and third nodes).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7-8 is/are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US Patent Application Publication 2022/0148511), herein after referred to as Kim.
Regarding independent claim 18, Kim discloses an electronic device (Figure 1 100), comprising:
a pixel unit (PX) including a plurality of pixels connected to a plurality of first scan lines (anyone of GB, Gl, GC, GW), a plurality of second scan lines (GW), a plurality of third scan lines, a plurality of fourth scan lines, and a plurality of data lines (DS) (Paragraph [0052]);
a power source generator (Figures 1 and 3 200) configured to generate a single gate high voltage (VGH1), a first gate low voltage (VGL1), and a second gate low voltage (VGL2) using a power source input (VIN) from outside of the power source generator (200), the second gate low voltage (VGL2) having a voltage that is different from the first gate low voltage (VGL1) ([0073] describes voltage VGL2 is greater or higher than VGL1.);
a scan driver (150) configured to generate:
a first scan signal (GB) to be supplied to the plurality of first scan lines (figure 2 GB(j)) using the gate high voltage (Figure 4 VGH1) and the first gate low voltage (VGL1),
a second scan signal (GW) to be supplied to the plurality of second scan lines (GW(j)) using the gate high voltage (VGH1) and the second gate low voltage (VGL2),
a third scan signal (GC) to be supplied to be supply to the plurality of third scan lines (GC(j)) using a second gate high voltage (VGH2) and the second gate low voltage (VGL2), and
a fourth scan signal (GI) to be supplied to the plurality of fourth scan lines (GI(j)) using the second gate high voltage (VGH2) and the second gate low voltage (VGL2); and
a data driver (130) configured to supply a data signal (DS) to the plurality of data lines ([0051]).
Kim does not specifically disclose using the single gate high voltage for the third or fourth scan signals.
Kim discloses to selectively output between two high levels and low levels of the scan signal voltages applied to initialization transistor, write transistor, compensation, and bypass transistors ([0077]-[0080] GI, GW, GC, and GB).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Kim’s single high voltage VGH1 with the known technique of being applied to the third and fourth scan signals (GC and GI) yielding the predictable results of still performing minimizing undesirably power consumption between the various stages improving overall efficiency in power consumption in an alternative design with predictable results as disclosed by Kim ([0077]).
6. Claim(s) 1-5 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (US Patent Application Publication 2022/0358881), herein after referred to as Chae, in view of Kim.
Regarding independent claim 1, Chae discloses a display device (Figure 1 1000), comprising:
a pixel unit (PX) including a plurality of pixels (Paragraph [0042] describes pixels connected to the intersection of scan lines S and data lines D.),
wherein each of the plurality of pixels (PX) includes:
a light emitting element (Figure 3 LD);
a driving transistor (M1) configured to control an amount of current flowing from a first power source line (VDD) to a second power source line (VSS) via the light emitting element (LD) in response to a voltage (Data signal supplied by the data line Dj (paragraphs [0071], [0078], and [0104] describes node N1 to affect node N3), Vint1[0078], Cst stored voltage [0082], or Vobs [0104]; all of said voltages are options described to be applied to gate of M1.) of a first node (N3) ([0070]), the driving transistor (M1) including a first electrode (source [0071]) connected to a second node (N1), and a second electrode (drain) connected to a third node (N2);
a write transistor (M2) connected between a first electrode (M1 source N1) of the driving transistor (M1) and a data line (Dj), and configured to be turned on or off in response to a write scan signal (GWi on S4i) ([0071]);
a first initialization transistor (M8) connected between an anode electrode (LD anode) of the light emitting element (LD) and a first initialization power source line (Vint2), and configured to be turned on or off in response to a first initialization scan signal (GBi on S1i) ([0079]), and
a compensation transistor (M3) connected between the second (see 112 above regarding this node to be interpreted as the first node) node (N3) and the third node (N2) and configured to be turned on or off in response to a compensation scan signal (S2i) ([0072]),
wherein a low voltage (Figure 4 P3 S4i/GWi low [0098]) of the write scan signal (GWi) is set to a first gate low voltage ([0109] in the third period P3 scan driver 20 supplies/sets signal GWi, depicted as low in figure 4), and [ ].
Chae does not specifically disclose a low voltage of each of the first initialization scan signal and the compensation scan signal are set to a second gate low voltage that is different from the first gate low voltage.
Kim discloses to selectively output between two high levels and low levels of the scan signal voltages applied to initialization transistor, write transistor, and compensation transistors ([0077]-[0080] GI, GW, and GC).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Chae’s low voltage of the write scan signal GWi with the known technique of being different from a second gate low voltage set to the first initialization and compensation scan signals yielding the predictable results of minimizing undesirably power consumption between the various stages improving overall efficiency in power consumption as disclosed by Kim ([0077]).
Regarding claim 2, Chae discloses the display device of claim 1, wherein the write transistor (Figure 3 M2) and the first initialization transistor (M8) are P-type transistors (paragraph [0083]).
Regarding claim 3, Chae and Kim discloses the display device of claim 1, wherein a high voltage of the write scan signal (Chae: Figure 4 GBi) and a high voltage of the first initialization scan signal (Chae: Figure 4 GWi) are set to a gate high voltage (Chae: Figure 4 implies the same high voltage for GBi and GWi. Kim: paragraphs [0077]-[0080] selects between two different high levels for the initialization and write scan signals and provides examples when the selected signals are the same (such as figure 4 threshold compensation scan signal GC and initialization scan signal GI both selected to have high level VGH2 of the options VGH1 and VGH2).).
Regarding claim 4, Kim discloses the display device of claim 1, wherein the first gate low voltage is a voltage higher than the second gate low voltage (Paragraph [0073] describes low voltage VGL2 is greater or higher than low voltage VGL1.).
Regarding claim 5, Chae discloses the display device of claim 1, further comprising:
a data driver (Figure 1 400) configured to supply a data signal (data signal) to the data line (Figure 1 D Figure 3 Dj) (paragraph [0054]);
a first scan driver (Figures 1-2 200+280) configured to supply the write scan signal (Figure 3 GWi) to a write scan line (S4i) ([109]); and
a second scan driver (Figures 1-2 200+220) configured to supply the first initialization scan signal (GBi) to a first initialization scan line (S1i) ([0104]).
Regarding claim 7, Chae and Kim discloses the display device of claim 5, wherein the first scan driver (Chae: Figure 2 220) includes a plurality of stage circuits (Chae: S11-S1n), and
wherein each of the plurality of stage circuits includes:
an output unit (Chae: shift register [0050]) configured to generate the write scan signal (Chae: GWi) using a gate high voltage (Chae: Figure 4 GBi depicted high level. Kim: VGH1 or VGH2) and a clock signal (Chae: [0050] shifter register uses clock signals to generate the scan signals. Kim: figure 4 and [0079] describes using clock signals for scan signal generation including GW CLK for write scan signal GW.); and
a control unit (Chae: 600) configured to control the output unit (Chae: [0044]).
Regarding claim 8, Kim discloses the display device of claim 7, wherein a high voltage of the clock signal is set to the gate high voltage, and a low voltage of the clock signal is set to the first gate low voltage (Figure 4 reference each scan signal utilizing a clock signal with respective gate and low high voltage.).
Regarding claim 19, Chae discloses the display device of claim 1, wherein each of the plurality of pixels further includes:
a second initialization transistor (M7) connected between the first node (N3) and a second initialization power source line (Vint1), and configured to be turned on or off in response to a second initialization scan signal (Figure 3 S3i/ figure 4GLi) ([0087]).
Response to Arguments
7. Applicant's arguments filed 6/29/2026 have been fully considered and relate towards newly amended subject matter. In regards to claim 1, Kim figure 4 depicts a particular example of application of VGH1/VGH2 and VGL1/VGL2 to the scan signals of EM, GI, GW, GC, and GB. Paragraph [0080] particularly states that the voltage generator 20 may selectively output one of VGH1/VGH2 and VGL1/VGL2 to each one of EM, GI, GW, GC, and GB to perform the invention improvement of overall efficiency of power consumption. Therefore, while figure 4 is an example of particular ones of said selection applied to said scan signals, the discloser of Kim includes more than said particular example. Said paragraphs describes the ability to use any of said voltages selectively in order to perform the improvement. This includes the above obvious type rejection yielding predictable results of selectively apply ones of said disclosed voltages in the manner claimed. Please refer to the above rejection of claim 1 for rebuttal.
In regards to claim 18, a similar interpretation is taken in regards to the particular application of voltages. Please refer to the above rejection of claim 18 for rebuttal.
This action is final necessitated by amendment.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER E LEIBY/ Primary Examiner, Art Unit 2621
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