Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending, with claims 6 and 9-17 being withdrawn.
Election/Restrictions
3. Applicant's election with traverse of invention II election in the reply filed on 2/19/2026 is acknowledged. The traversal is on the ground(s) that simultaneous examination of all the claims would not present an undue burden, especially since all invention were classified in the same class and sub-class.
This is not found persuasive because: each of inventions I and II respectively corresponding to the circuit of figure 4 with the difference regarding the applied GW signal being a low voltage signal VGL1 (figure 9) or a clock signal s_CLK (figure 10). Invention III comprises additional mutually exclusive difference such that the pixel circuit is n-type, some with double gates, additional switches installed in different manner, utilizing a gate high voltage VGL (Figure 15).
It is well understood and known to one skilled in the art the almost infinite possibilities to making/using a display pixel circuit. Classification G09G3/3233 comprises at least 27,000 pieces of art classified therein. Searching through just those number of references alone requires a substantial amount of searching and consideration; especially in consideration regarding nuisance differences of the particular level of the signal in order for a particular switch installed in a particular manner to operate in the claimed manner.
MPEP 803 immediately states that a restriction is proper when the claims are able to support separate patents. A particular switch installed in a particular manner that comprises different signal levels of varying voltage to open/close describes a mutually exclusive embodiment such that a patent may be support per particular switch installation and signal level to perform the same function of a pixel emitting light. MPEP 803 does not state that an “applicant is entitled to have a reasonable number of species examined”. MPEP 803.04 states that “a reasonable number of such nucleotide sequences to be claimed in a single application” but this does not regard the current application’s claims.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim et al. (US Patent Application Publication 2022/0148511), herein after referred to as Kim.
Regarding independent claim 18, Kim discloses a display device (Figure 1 100), comprising:
a pixel unit (PX) including a plurality of pixels connected to a plurality of first scan lines (anyone of GB, Gl, GC, GW), a plurality of second scan lines (any other of GB, GI, GC, GW), and a plurality of data lines (DS) (Paragraph [0052]);
a power source generator (Figures 1 and 3 200) configured to generate a gate high voltage (VGH1 or VGH2), a first gate low voltage (VGH1), and a second gate low voltage (VGH2) using a first power source input (VIN) from outside of the power source generator (200) and a second power source (VGB) having a voltage lower (VGL1) than the first power source (VIN) ([0073] describes low voltage VGL2 is greater or higher than low voltage VGL1.);
a scan driver (150) configured to generate a first scan signal (GB) to be supplied to the first scan lines (figure 2 GB(j)) using the gate high voltage (Figure 4 VGH1) and the first gate low voltage (VGL1), and configured to generate a second scan signal (GW) to be supplied to the second scan lines (GW(j)) using the gate high voltage (VGH1) and the second gate low voltage (VGL2); and
a data driver (130) configured to supply a data signal (DS) to the data lines ([0051]).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (US Patent Application Publication 2022/0358881), herein after referred to as Chae, in view of Kim.
Regarding independent claim 1, Chae discloses a display device (Figure 1 1000), comprising:
a pixel unit (PX) including a plurality of pixels (Paragraph [0042] describes pixels connected to the intersection of scan lines S and data lines D.),
wherein each of the pixels (PX) includes:
a light emitting element (Figure 3 LD);
a driving transistor (M1) configured to control an amount of current flowing from a first power source line (VDD) to a second power source line (VSS) via the light emitting element (LD) in response to a voltage (Data signal supplied by the data line Dj (paragraphs [0071], [0078], and [0104] describes node N1 to affect node N3), Vint1[0078], Cst stored voltage [0082], or Vobs [0104]; all of said voltages are options described to be applied to gate of M1.) of a first node (N3) ([0070]);
a write transistor (M2) connected between a first electrode (N1) of the driving transistor (M1) and a data line (Dj), and configured to be turned on or off in response to a write scan signal (GWi on S4i) ([0071]); and
an initialization transistor (M8) connected between an anode electrode (LD anode) of the light emitting element (LD) and an initialization power source line (Vint2), and configured to be turned on or off in response to an initialization scan signal (GBi on S1i) ([0079]),
wherein a low voltage (Figure 4 P3 S4i/GWi low [0098]) of the write scan signal (GWi) is set to a first gate low voltage ([0109] in the third period P3 scan driver 20 supplies/sets signal GWi, depicted as low in figure 4), and [ ].
Chae does not specifically disclose a low voltage of the initialization scan signal is set to a second gate low voltage that is different from the first gate low voltage.
Kim discloses to selectively output between two high levels and low levels of the scan signal voltages applied to initialization transistor and write transistors ([0077]-[0080]).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Chae’s low voltages of the initialization scan signal GBi and write scan signal GWi with the known technique of being different yielding the predictable results of minimizing undesirably power consumption between the various stages improving overall efficiency in power consumption as disclosed by Kim ([0077]).
Regarding claim 2, Chae discloses the display device of claim 1, wherein the write transistor (Figure 3 M2) and the initialization transistor (M8) are P-type transistors (paragraph [0083]).
Regarding claim 3, Chae and Kim discloses the display device of claim 1, wherein a high voltage of the write scan signal (Chae: Figure 4 GBi) and a high voltage of the initialization scan signal (Chae: Figure 4 GWi) are set to a gate high voltage (Chae: Figure 4 implies the same high voltage for GBi and GWi. Kim: paragraphs [0077]-[0080] selects between two different high levels for the initialization and write scan signals and provides examples when the selected signals are the same (such as figure 4 threshold compensation scan signal GC and initialization scan signal GI both selected to have high level VGH2 of the options VGH1 and VGH2).).
Regarding claim 4, Kim discloses the display device of claim 1, wherein the first gate low voltage is a voltage higher than the second gate low voltage (Paragraph [0073] describes low voltage VGL2 is greater or higher than low voltage VGL1.).
Regarding claim 5, Chae discloses the display device of claim 1, further comprising:
a data driver (Figure 1 400) configured to supply a data signal (data signal) to the data line (Figure 1 D Figure 3 Dj) (paragraph [0054]);
a first scan driver (Figures 1-2 200+280) configured to supply the write scan signal (Figure 3 GWi) to a write scan line (S4i) ([109]); and
a second scan driver (Figures 1-2 200+220) configured to supply the initialization scan signal (GBi) to an initialization scan line (S1i) ([0104]).
Regarding claim 7, Chae and Kim discloses the display device of claim 5, wherein the first scan driver (Chae: Figure 2 220) includes a plurality of stage circuits (Chae: S11-S1n), and
wherein each of the stage circuits includes:
an output unit (Chae: shift register [0050]) configured to generate the write scan signal (Chae: GWi) using a gate high voltage (Chae: Figure 4 GBi depicted high level. Kim: VGH1 or VGH2) and a clock signal (Chae: [0050] shifter register uses clock signals to generate the scan signals. Kim: figure 4 and [0079] describes using clock signals for scan signal generation including GW CLK for write scan signal GW.); and
a control unit (Chae: 600) configured to control the output unit (Chae: [0044]).
Regarding claim 8, Kim discloses the display device of claim 7, wherein a high voltage of the clock signal is set to the gate high voltage, and a low voltage of the clock signal is set to the first gate low voltage (Figure 4 reference each scan signal utilizing a clock signal with respective gate and low high voltage.).
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E LEIBY whose telephone number is (571)270-3142. The examiner can normally be reached 11-7.
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/CHRISTOPHER E LEIBY/ Primary Examiner, Art Unit 2621
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